CN1071966C - Phase error canceller for QPSK signals using unique word detectors - Google Patents

Phase error canceller for QPSK signals using unique word detectors Download PDF

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Publication number
CN1071966C
CN1071966C CN94101795A CN94101795A CN1071966C CN 1071966 C CN1071966 C CN 1071966C CN 94101795 A CN94101795 A CN 94101795A CN 94101795 A CN94101795 A CN 94101795A CN 1071966 C CN1071966 C CN 1071966C
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mentioned
channel
bit
baseband signal
signal
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CN1096620A (en
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永田一幸
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0024—Carrier regulation at the receiver end
    • H04L2027/0026—Correction of carrier offset
    • H04L2027/003—Correction of carrier offset at baseband only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0044—Control loops for carrier regulation
    • H04L2027/0046—Open loops
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0083—Signalling arrangements
    • H04L2027/0089—In-band signals
    • H04L2027/0093—Intermittant signals
    • H04L2027/0095—Intermittant signals in a preamble or similar structure

Abstract

In a circuit arrangement for correcting phase errors of P-channel and Q-channel baseband signals of a QPSK signal, input registers are provided corresponding respectively to possible bit patterns which the unique words of the P-channel and Q-channel baseband signals may assume. Each input register stores 2N bits of incoming unique words of the P- and Q-channel signals. Reference registers corresponding to the possible bit patterns are provided for individually storing 2N bits of a corresponding one of the possible bit patterns. Mismatches between the bits stored in each input register and the corresponding reference register are detected and compared with thresholds to produce a phase error correcting signal. In response, the connecting paths of the P- and Q-channel baseband signals to output terminals are controlled and bit reversals are effected on the P- and Q-channel baseband signals.

Description

Use the PE arrester of the QPSK signal of THE DETECTION OF UNIQUE device
Relate generally to satellite Quadrature Phase Shift Keying of the present invention (QPSK) transmission system more particularly relates to the PE that is used for the phase calibration mistake and proofreaies and correct, and this mistake is incorporated into the QPSK signal during the transmission.
In the satellite communication system of using the QPSK modulation, P channel and Q channel unique word (or pulse train code word) are inserted in the preamble of each burst transmission, are used for the synchronous purpose of frame or pulse train.During the transmission, signal will be subjected to undesirable influence and produce PE, channel also may occur as bit reversal and be inverted.
PE arrester according to prior art, the QPSK signal is transformed to P channel and Q channel baseband signal, and the N bit of the P channel unique word that sends between the N bit of P channel unique word and the transmission period possible bit format that can present compares and detect inconsistent to produce an inconsistent counting between them.Calculate inconsistent counting with respect to threshold value then, to produce a mistake correction signal.But present technology is unsatisfied for the possible PE of accurate correction and wishes to improve.
The objective of the invention is to proofread and correct for the QPSK signal that uses unique word provides the high-performance PE.
According to a first aspect of the invention, a kind of circuit arrangement is provided, be used for the P channel of correction of orthogonal phase shift keyed signal and the PE of Q channel baseband signal, wherein each above-mentioned baseband signal comprises the N bit unique word that is used to set up the synchronous predetermined bit form of pulse train, this circuit arrangement comprises: first and second inputs are used to receive above-mentioned P channel and Q channel baseband signal; A plurality of input store devices, corresponding to the possible bit format of the unique word of above-mentioned P channel that can present during the transmission and Q channel baseband signal, each input store device receives P and Q channel baseband signal and stores the P channel and the 2N bit of the input unique word of Q channel baseband signal from above-mentioned input respectively; A plurality of reference memory devices, respectively corresponding to above-mentioned possible bit format, the 2N bit of corresponding a kind of form of the above-mentioned possibility of each reference memory device storage bit format; A plurality of error detection occurs apparatuses, respectively corresponding to input store device and reference memory device, each error detection occurs apparatus detects inconsistent between the bit of corresponding input store device storage and the bit stored and produces an inconsistent counting in corresponding reference memory device; A plurality of comparator devices, respectively corresponding to above-mentioned error detection occurs device, each comparator device compares the inconsistent counting of corresponding error detection occurs apparatus and first and second thresholdings, if determine that inconsistent counting is less than first thresholding, produce one first output signal, if determine that perhaps inconsistent counting greater than second thresholding, then produces one second output signal; With the error recovery device of first and second output signals that respond described a plurality of comparator devices, be used for and be coupled to first and second outputs by first and second connecting paths respectively from above-mentioned P and the Q channel baseband signal that above-mentioned first and second outputs are brought in; Reversal connection first and second connecting paths, and on above-mentioned P and Q channel baseband signal, provide bit reversal.
According to a second aspect of the invention, a kind of circuit arrangement is provided, be used for the P channel of correction of orthogonal phase shift keyed signal and the PE of Q channel baseband signal, wherein each above-mentioned baseband signal comprises the N bit unique word that is used to set up the synchronous predetermined bit form of pulse train, this circuit arrangement comprises: first and second inputs are used to receive above-mentioned P and Q channel baseband signal; First and second outputs; Respond the error recovery device of first and second mistake correction signals, be used for being coupled P channel and Q channel signal respectively to above-mentioned first and second outputs by first and second connecting paths; Reversal connection first and second connecting paths also provide bit reversal on above-mentioned P and Q channel baseband signal; Switching device is used for by third and fourth connecting path above-mentioned first and second inputs being connected to above-mentioned error recovery device also according to not having or exist spectrum inversion, reversal connection third and fourth connecting path; A plurality of input store devices, respectively corresponding to the unique word of above-mentioned P channel that can present during the transmission and Q channel baseband signal might bit format half, each input store device receives P and Q channel baseband signal and stores the P channel and the 2N bit of the input unique word of Q channel baseband signal from above-mentioned input; A plurality of reference storage devices, respectively corresponding to above-mentioned half that might bit format, half the 2N bit of a corresponding bit format of each possible bit format of the above-mentioned institute of reference memory device storage; A plurality of error detection occurs apparatuses, respectively corresponding to input store device and reference memory device, each error detection occurs apparatus detects inconsistent between bit of storing and the bit of storing in corresponding reference memory device in corresponding input store device, and produce an inconsistent counting; With a plurality of comparator devices, respectively corresponding to above-mentioned error detection occurs apparatus, each comparator device compares the inconsistent counting and first and second thresholdings of corresponding error detection occurs apparatus, if determine that inconsistent counting is less than first thresholding, produce above-mentioned first mistake correction signal and deliver to described error recovery device, if determine that perhaps inconsistent counting greater than second thresholding, produces second mistake correction signal and delivers to described error recovery device.
The present invention is described in further detail with reference to the accompanying drawings, wherein:
Fig. 1 is the block diagram of THE DETECTION OF UNIQUE device according to a preferred embodiment of the invention;
Fig. 2 A is the phasor diagram of QPSK system when spectrum inversion not taking place; And Fig. 2 B is the phasor diagram of this system during spectrum inversion; With
Fig. 3 is the block diagram of the THE DETECTION OF UNIQUE device of the embodiment of modification according to the present invention.
Referring now to Fig. 1, the figure shows according to the preferred embodiment of the present invention and be used for the circuit arrangement block diagram that PE is proofreaied and correct, this equipment is used to receive QPSK (quadrature modulation quaternary PSK, or 4PSK) burst signal, and this signal comprises sets up the synchronous unique word of pulse train (or pulse train code word).The signal that sends is modulated to homophase (P channel) and quadrature (Q channel) baseband signal by the modulator (not shown), and is added to the input 1 and 2 of this PE correcting circuit equipment respectively.P and Q channel signal are added to serial/parallel converter 3 and 4 respectively, and here the N bit serial unique word of two channels is transformed to parallel data.Circuit arrangement of the present invention comprises the THE DETECTION OF UNIQUE device 5,6,7 and 8 of one group of four same structure.Each THE DETECTION OF UNIQUE device 5,6,7 and 8 comprises a pair of N bit input UW register 20R and 20L; With a pair of N bit with reference to UW register 21R and 21L, and be connected input UW register 20R, 20L and with reference to UW register 21R, a 2N bit error detector 22 between the 21L.All THE DETECTION OF UNIQUE devices 5,6,7 and 8 input UW register 20R, 20L is connected respectively to the output of serial/parallel converter 3 and 4, is used to store the unique word of the input of two channels, and this unique word can suffer bit reversal or spectrum inversion.The reference UW register 21R of each THE DETECTION OF UNIQUE device, 21L are coupled with the reference unique word corresponding to the possible bit format of influence input unique word.
By error detector 22 the reference unique word bit of input unique word bit and relevant position is compared.Specifically, this detector comprises 2N the partial sum gate that is connected between register 20 and the 21 corresponding bits positions, when conforming between the corresponding bit position, produce a bit " O " from each partial sum gate, when between the corresponding bit position when inconsistent, produce a bit " 1 ".Therefore, error detector 22 produces an output M, represents inconsistent quantity or error count.This error count value M is added to comparator 23 and 24, compares the predetermined tolerance of ε representative here with threshold value ε and 2N-ε.If error count M is equal to or less than tolerance ε, comparator 23 produces a logical one on output 5A, shows that the QPSK signal of input has a specific signal phase place.If error count M is equal to or greater than 2N-ε, comparator 24 produces a logical one at output 5B, shows that the phase place of QPSK signal of input is opposite with the signal phase of indicating at output 5A.
In order to produce the reference unique word of parallel form, provide a kind of P channel reference unique word generator 9 and Q channel reference unique word generator 10.These are realized with register with reference to the unique word generator, are used for storing predetermined bit.
The reference register 21L of THE DETECTION OF UNIQUE device 5 and 21R are connected respectively to the output of P channel UW generator 9 and Q channel UW generator 10, with P channel reference unique word bit UP 1, UP 2..., UP NBe stored into the register 21L of UW detector 5 and with Q channel reference unique word bit UQ 1, UQ 2... UQ NBe stored into the register 21R of UW detector 5.If the bit stream of input is not subjected to bit reversal or frequency spectrum having a strong impact on of amount, then P channel unique word bit P 1, P 2..., P NThe input register 20L and the Q channel unique word bit Q of detector 5 will be stored in 1, Q 2..., Q NTo be stored in the input register 20R of detector 5 as shown in Figure 1.If be stored between the interior unique word bit of the register of detector 5 and pursue the error count M of bit comparative result less than tolerance ε, then on output 5A, produce logical one by comparator 23, shown in Fig. 2 A, when not having spectrum inversion to occur, the QPSK signal that its expression receives in the normal phase spirogram of QPSK, have π/4 radians signal phase (P, Q).If error count M is equal to or greater than 2N-ε, comparator 24 produces logical one at output 5B, its expression QPSK signal in the normal phase spirogram, have-3 π/4 radians signal phase (P, Q).
The reference register 21R that the reference register 21L of THE DETECTION OF UNIQUE device 6 is connected for receiving the output of Q channel UW generator 10 and detector 6 is connected for receiving the output of P channel UW generator 10, through phase inverter 11 storage Q channel reference unique word bit UQ 1, UQ 2..., UQ NIn the register 21L of detector 6 and with P channel reference unique word bit U P 1, U P 2... U P NStore the register 21R of detector 6 into.If incoming bit stream is affected, so that Q channel unique word bit Q 1, Q 2..., Q NBe stored in the input register 20L of detector 6 and P channel unique word bit P 1, P 2..., P NIn the input register 20R of this detector shown in being stored in, if and the error count M of detector 6 is less than tolerance ε, then on output 6A, will produce logical one, the QPSK signal that expression receives has signal phase (Q, P) (Fig. 2 A) of 3 π/4 radians in the normal phase spirogram of QPSK system.If error count M is equal to or greater than 2N-ε, then on output 6B, will produce logical one, expression QPSK signal in normal phasor diagram, have a π/4 radians signal phase (Q, P).
The reference register 21L of THE DETECTION OF UNIQUE device 7 is connected for receiving the output of Q channel UW generator 10 and the reference register 21R of detector 7 is connected for receiving the output of P channel UW generator 10, so that store Q channel reference unique word bit UQ 1, UQ 2..., UQ NIn the memory 21L of detector 6 and memory P channel reference unique word bit UP 1, UP 2..., UP NIn the register 21R of detector 7.If incoming bit stream is affected, so that Q channel unique word bit Q 1, Q 2... Q NBe stored among the input register 20L of detector 7 and P channel unique word bit P 1, P 2... P NAmong the input store 20R of the detector 7 shown in being stored in, if and the error count M of detector 6 is less than tolerance ε, on output 7A, will produce logical one, expression is when this system suffers spectrum inversion (seeing Fig. 2 B), the QPSK signal that receives in the anti-phase phasor diagram of QPSK system, have π/4 radians signal phase (Q, P).If error count M is equal to or greater than 2N-ε, then on output 7B, produce logical one, expression QPSK signal in anti-phase phasor diagram, have one 3 π/4 radians signal phase (Q, P).
The reference register 21R that the reference register 21L of THE DETECTION OF UNIQUE device 8 is connected for receiving the output of P channel UW generator 9 and detector 8 is connected for receiving the output of Q channel UW generator 10, through inverter 11 storage P channel reference unique word bit UP 1, UP 2..., UP NRegister 21L and storage Q channel reference unique word bit (U Q to detector 8 1, U Q 2..., U Q N) to the register 21R of detector 8.If the bit stream of input is affected, so that P channel unique word bit P 1, P 2..., P NBe stored among the input register 20L of detector 8, and Q channel unique word bit (Q 1, Q 2..., Q N) among the input register 20R of the detector 8 shown in being stored in.If the error count M of detector 8 less than tolerance ε, will produce logical one at output 8A, the QP-SK signal that expression receives in anti-phase phasor diagram (Fig. 2 B), have 3 π/4 radians signal phase (P, Q).If error count M is equal to or greater than 2N-ε, then produce logical one at output 8B, expression QPSK signal in anti-phase phasor diagram, have a π/4 radians signal phase (P, Q).
Because the QPSK signal only presents 8 kinds of a kind of phase places in the possibility signal phase, THE DETECTION OF UNIQUE device 5,6,8 outputs of 7 and 8 are changed to 3 bit code and are fed to PE arrester 14 as phase correction signal by logical circuit 13, also add P and Q channel baseband signal at this mistake arrester 14.Use 3 bit code, this PE adjuster 14 provides bit reversal and the channel on input P channel and Q channel signal to be inverted, so that their phase ambiguity is corrected on output 15,16.Above-mentioned logical circuit 13 and PE arrester 14 can be referred to as the error recovery device.
Because can know the appearance of spectrum inversion in advance according to the system that uses, and it can not occur during system works, the embodiment of Fig. 1 can be simplified widely, as shown in Figure 3, in Fig. 3 corresponding to those parts of Fig. 1 use with Fig. 1 in the same numbers mark that uses and have the connotation identical with Fig. 1 appropriate section.The embodiment of Fig. 3 is different with the embodiment of front, saved THE DETECTION OF UNIQUE device 7 and 8 in Fig. 3, and an inversion switch 30 is connected between input 1,2 and the mistake arrester 14.
When not requiring spectrum inversion, switch 30 set are in being connected to input 1 and 2 the input 14A and the 14B of mistake arrester 14 respectively, and are connected respectively to serial/parallel converter 3 and 4.THE DETECTION OF UNIQUE device 5 and 6 work with top in conjunction with the phasor diagram of Fig. 2 A describe identical, produce logical one output index signal phase place (P, Q), (P, Q), (Q, P) and (Q, P).
When requiring spectrum inversion, switch 30 work are so that this connecting path of reversal connection shown in numeral 31 and 32 makes input 1 and 2 be connected to input 14B and 14A and serial/parallel converter 4 and 3 of mistake arrester 14 respectively.THE DETECTION OF UNIQUE device 5 and 6 work with top in conjunction with the phasor diagram of Fig. 2 B describe identical, produce logical one output index signal phase place (Q, P), (Q, P), (P, Q) and (P, Q).For example, if produce logical one on output 5A, switch 30 is in the normal position, then signal phase be (P, Q), if during spectrum inversion, switch 30 work is used for this connecting path of reversal connection, then signal phase be (Q, P)
In another embodiment, owing to be maintained fixed with reference to unique word, by the reference unique word shown in the storage map 1 for good and all, unique word generator 9 and 10 can be cancelled.
Described the 4PSK signal above, the present invention equally also can be used for other psk signal.

Claims (4)

1. circuit arrangement, be used for the P channel of correction of orthogonal phase shift keyed signal and the PE of Q channel baseband signal, wherein each above-mentioned baseband signal comprises the N bit unique word that is used to set up the synchronous predetermined bit form of pulse train, it is characterized in that this circuit arrangement comprises:
First and second inputs are used to receive above-mentioned P channel and Q channel baseband signal;
A plurality of input store devices, corresponding to the possible bit format of the unique word of above-mentioned P channel that can present during the transmission and Q channel baseband signal, each input store device receives P and Q channel baseband signal and stores the P channel and the 2N bit of the input unique word of Q channel baseband signal from above-mentioned input respectively;
A plurality of reference memory devices, respectively corresponding to above-mentioned possible bit format, the 2N bit of corresponding a kind of form of the above-mentioned possibility of each reference memory device storage bit format;
A plurality of error detection occurs apparatuses, respectively corresponding to input store device and reference memory device, each error detection occurs apparatus detects inconsistent between the bit of corresponding input store device storage and the bit stored and produces an inconsistent counting in corresponding reference memory device;
A plurality of comparator devices, respectively corresponding to above-mentioned error detection occurs device, each comparator device compares the inconsistent counting of corresponding error detection occurs apparatus and first and second thresholdings, if determine that inconsistent counting is less than first thresholding, produce one first output signal, if determine that perhaps inconsistent counting greater than second thresholding, then produces one second output signal; With
Respond the error recovery device of first and second output signals of described a plurality of comparator devices, the above-mentioned P and the Q channel baseband signal that are used for bringing in from above-mentioned first and second outputs are coupled to first and second outputs by first and second connecting paths respectively; Reversal connection first and second connecting paths, and on above-mentioned P and Q channel baseband signal, provide bit reversal.
2. according to the circuit arrangement of claim 1, wherein above-mentioned second threshold value equals 2N-ε, and ε is first thresholding here.
3. according to the circuit arrangement of claim 1, wherein above-mentioned error recovery device comprises each above-mentioned first and second device that are output as many bit code that is used for the above-mentioned a plurality of comparison means of conversion.
4. according to claim 1,2 or 3 circuit arrangement, also comprise a switching device, be used for above-mentioned first and second inputs being connected to above-mentioned error recovery device also according to there not being or existing spectrum inversion by third and fourth connecting path, reversal connection third and fourth connecting path, the described a plurality of reference storage devices that wherein provide respectively corresponding to above-mentioned half that might bit format.
CN94101795A 1993-01-14 1994-01-14 Phase error canceller for QPSK signals using unique word detectors Expired - Fee Related CN1071966C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP532793A JP2522144B2 (en) 1993-01-14 1993-01-14 Phase disambiguation circuit
JP005327/1993 1993-01-14
JP005327/93 1993-01-14

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CN1096620A CN1096620A (en) 1994-12-21
CN1071966C true CN1071966C (en) 2001-09-26

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EP (1) EP0608717A3 (en)
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CN (1) CN1071966C (en)
AU (1) AU678414B2 (en)
CA (1) CA2113392C (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0838111B1 (en) * 1995-07-07 2001-12-19 Nortel Networks Limited Carrier recovery for digitally phase modulated signals, using a known sequence
EP0804002B1 (en) * 1996-04-25 2004-06-16 Alcatel Method and device for detecting the presence of a codeword in an incoming dataword
KR100238284B1 (en) * 1997-05-12 2000-01-15 윤종용 Phase correction circuit and method therefor
US7197090B1 (en) 1999-01-29 2007-03-27 Northrop Grumman Corporation Adaptive decision regions and metrics
GB2358116B (en) * 1999-02-24 2002-11-06 Nec Corp Demodulation circuit and demodulation method with compensation for sampling offset
US7138882B2 (en) * 2002-11-08 2006-11-21 Northrop Grumman Corp Architecture for universal modulator
JP4655232B2 (en) * 2007-04-27 2011-03-23 ソニー株式会社 Demodulator and method
JP4386135B2 (en) * 2008-01-30 2009-12-16 ソニー株式会社 Decoding device and method, receiving device and method, and program
US8989330B2 (en) * 2010-07-30 2015-03-24 Silicon Laboratories Inc. Method and apparatus to detect a synchronization delimiter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736507A (en) * 1971-08-19 1973-05-29 Communications Satellite Co Phase ambiguity resolution for four phase psk communications systems
US5025455A (en) * 1989-11-30 1991-06-18 The United States Of America As Represented By The Administer, National Aeronautics And Space Administration Phase ambiguity resolution for offset QPSK modulation systems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60227544A (en) * 1984-04-25 1985-11-12 Fujitsu Ltd Unique word detecting device
JPS62292037A (en) * 1986-06-12 1987-12-18 Mitsubishi Electric Corp Synchronizing code detection circuit
US4847869A (en) * 1987-12-04 1989-07-11 Motorla, Inc. Rapid reference acquisition and phase error compensation for radio transmission of data
US4993047A (en) * 1989-09-05 1991-02-12 At&T Bell Laboratories Volterra linearizer for digital transmission
US5095536A (en) * 1990-03-23 1992-03-10 Rockwell International Corporation Direct conversion receiver with tri-phase architecture
FR2662889A1 (en) * 1990-05-31 1991-12-06 Alcatel Transmission Method and device for resolving the phase ambiguity in digital transmission with coherent demodulation
US5136612A (en) * 1990-12-31 1992-08-04 At&T Bell Laboratories Method and apparatus for reducing effects of multiple access interference in a radio receiver in a code division multiple access communication system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736507A (en) * 1971-08-19 1973-05-29 Communications Satellite Co Phase ambiguity resolution for four phase psk communications systems
US5025455A (en) * 1989-11-30 1991-06-18 The United States Of America As Represented By The Administer, National Aeronautics And Space Administration Phase ambiguity resolution for offset QPSK modulation systems

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EP0608717A2 (en) 1994-08-03
CA2113392A1 (en) 1994-07-15
US5500876A (en) 1996-03-19
CN1096620A (en) 1994-12-21
CA2113392C (en) 1998-01-27
JP2522144B2 (en) 1996-08-07
JPH06216953A (en) 1994-08-05
AU678414B2 (en) 1997-05-29
AU5380994A (en) 1994-07-21
EP0608717A3 (en) 1994-09-14

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