CN104599711A - Embedded storage chip, embedded electronic device and program updating method - Google Patents
Embedded storage chip, embedded electronic device and program updating method Download PDFInfo
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- CN104599711A CN104599711A CN201510022880.7A CN201510022880A CN104599711A CN 104599711 A CN104599711 A CN 104599711A CN 201510022880 A CN201510022880 A CN 201510022880A CN 104599711 A CN104599711 A CN 104599711A
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Abstract
The invention relates to an embedded storage chip. The embedded storage chip comprises a body, a first interface contact arranged on the body, control integrated circuit crystal grains encapsulated in the body and Nand Flash storage integrated circuit crystal grains, wherein the Nand Falsh storage integrated circuit crystal grains and the first interface contact are respectively and electrically connected with the control integrated circuit crystal grains; each control integrated circuit crystal grain is provided with an SPI interface, the body is also provided with SPI interface contacts, the SPI interface contacts are electrically connected with the SPI interface, and the SPI interface contacts at least include a power supply wire contact, a ground wire contact, a data output wire contact, a data input wire contact, a chip selection wire contact and clock wire contact. According to the embedded storage chip, the SPI interfaces are additionally arranged on the control integrated circuit crystal grains, code data needed for starting can be rapidly acquired by a peripheral electronic device by virtue of the SPI interfaces, so that the peripheral electronic device does not need to be provided with an additional SPI Nor Flash storage chip, and the production cost of the peripheral electronic device can be reduced.
Description
Technical field
The present invention relates to memory device, particularly relate to a kind of embedded storage chip, EMBEDDED AVIONICS and programme upgrade method thereof.
Background technology
Existing EMBEDDED AVIONICS is as intelligent watch, Intelligent bracelet etc., function gets more and more, but the space holding internal circuit truly has limit, and product is more and more towards lightening, the future development of miniaturization, therefore more and more higher to the integration level necessitates of embedded chip, and existing embedded storage chip in use, all need to configure a SPI Nor Flash memory chip more in addition to store some start-up code supervisors, like this, because embedded storage chip and SPI Nor Flash memory chip all need to occupy certain area on a printed circuit, therefore restriction is caused to the further miniaturization of electronic product.And need employing two kinds of storage chips due to EMBEDDED AVIONICS such as described intelligent watch, Intelligent bracelet, the inevitable cost that also can raise described EMBEDDED AVIONICS.
Summary of the invention
Based on this, be necessary the problem causing restriction for existing embedded storage chip structure to the further miniaturization of EMBEDDED AVIONICS, the embedded storage chip that is novel is provided.
In addition, there is a need to the programme upgrade method that a kind of novel EMBEDDED AVIONICS and this EMBEDDED AVIONICS are provided.
A kind of embedded storage chip, comprise body, be encapsulated in intrinsic control integration circuit die and NandFlash storage integrated-circuit die, and the first interface contact be arranged on body, described control integration circuit die is provided with first interface, described Nand Flash stores integrated-circuit die and is electrically connected with described control integration circuit die, described first interface connects and is electrically connected with described first interface, described embedded storage chip also comprises the second interface contact be arranged on body, described control integration circuit die is also provided with the second interface, described second interface contact is electrically connected with described second interface, described second interface is SPI interface, described second interface contact is SPI interface contact, described second interface contact at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts, described Nand Flash stores integrated-circuit die and marks off the storage space of a part of storage space as external electronic device start-up code, described control integration circuit die comprises for supporting the SPI interface support module of SPI interface communications protocol and obtaining from SPI interface the quick respond module that it starts data for quick response external electronic equipment.
In a specific embodiment, described quick respond module comprise Platform Analysis unit for analyzing external electronic device operation platform and for confirming that external electronic device starts according to described external electronic device operation platform time each step code data, and code data when described external electronic device being started needed for next step stores integrated-circuit die from described Nand Flash in advance and reads the unit and the code be cached in control integration circuit die internal memory prestores.
In a specific embodiment, described second interface contact also comprises state maintaining line contact and write-protect line contact.
In a specific embodiment, described first interface is SD interface, described first interface contact is SD interface contact, and described first interface contact at least comprises power lead, ground wire, data line 0, data line 1, data line 2, data line 3, clock line, order wire eight contacts.
In a specific embodiment, described first interface is USB interface, and described first interface contact is USB interface contact, and described first interface contact at least comprises power lead, ground wire, correction data line, negative data line four contacts.
In a specific embodiment, described first interface is eMMC interface, described first interface contact is eMMC interface contact, and described first interface contact at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.
In a specific embodiment, the body of described embedded storage chip is provided with 30 contacts, except first interface contact and the second interface contact, also comprise the power cord point of core power line contact and reservation, all the other contacts are the stick contact temporarily do not used.
In a specific embodiment, described embedded storage chip length is of a size of 8mm*8mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.
In a specific embodiment, described embedded storage chip length is of a size of 8mm*7.5mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.
In a specific embodiment, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described contact is circular pad contact or spherical contact or dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.
A kind of EMBEDDED AVIONICS, comprises embedded storage chip described above.
A kind of programme upgrade method of EMBEDDED AVIONICS, described EMBEDDED AVIONICS comprises embedded storage chip described above, described method comprises the steps: that copying ROMPaq to NandFlash by first interface stores the storage space that provides of integrated-circuit die, upgrading.
Above-mentioned embedded storage chip, the programme upgrade method of EMBEDDED AVIONICS and EMBEDDED AVIONICS, by arranging a SPI interface on control integration circuit die, and mark off Nand Flash and store the part storage space of integrated-circuit die for storing the start-up code of external electronic device, by the platform that the Platform Analysis element analysis external electronic device of control integration circuit die is run, thus determine that each step of external electronic device needs the code data loaded when starting, and code data when external electronic device being started in advance needed for next step reads and is cached in the internal memory of control integration circuit die from Nand Flash storage integrated-circuit die, thus ensure that control integration circuit die can obtain data required when it starts from SPI interface by response external electronic equipment fast, external electronic device is made only to need use embedded storage chip, just can realize various memory function, thus the area that minimizing external electronic device printed circuit board (PCB) takies, be convenient to the miniaturization of external electronic device, meanwhile, adopt embedded electronic chip provided by the invention, described external electronic device does not need additionally to use a SPI Nor Flash memory chip again, thus further can reduce the hardware cost of external electronic device, further, because described embedded storage chip possesses first interface, therefore the external electronic device of described embedded storage chip is adopted, ROMPaq can be copied to described Nand Flash by first interface and store the storage space that integrated-circuit die provides, carry out copy upgrading, relative to the mode that traditional SPI Nor Flash memory chip is upgraded by burning, greatly facilitate the use of domestic consumer.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of embedded storage chip in an embodiment;
Fig. 2 is the pad distribution schematic diagram of embedded storage chip in an embodiment;
Fig. 3 is the composition schematic diagram of control integration circuit die in embedded storage chip in an embodiment;
Fig. 4 is the physical dimension schematic diagram of embedded storage chip in an embodiment.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 is the electrical block diagram of embedded storage chip in an embodiment; Fig. 2 is the pad distribution schematic diagram of embedded storage chip in an embodiment.As depicted in figs. 1 and 2, this embedded storage chip 10, comprise body 105, be encapsulated in the control integration circuit die 101 in body 105 and Nand Flash storage integrated-circuit die 102, and the first interface contact 103 be arranged on body, described control integration circuit die 101 is provided with first interface, described Nand Flash stores integrated-circuit die 102 and is electrically connected 101 with described control integration circuit die, described first interface contact 103 is electrically connected with described first interface, described embedded storage chip 10 also comprises the second interface contact 104 be arranged on described body 105, described control integration circuit die 101 is also provided with the second interface, described second interface contact and described second interface electrical connection, described second interface is SPI interface, described second interface contact 104 is SPI interface contact, described second interface contact 104 at least comprises power lead (SPI-VCC), ground wire (GND), DOL Data Output Line (SPI-DO), Data In-Line (SPI-DI), chip select line (SPI-CS), clock line (SPI-CLK) 6 contacts.
Described Nand Flash stores integrated-circuit die 102 and marks off the storage space of a part of storage space as external electronic device start-up code.
In the present invention, described external electronic device refers to that EMBEDDED AVIONICS of intelligent watch, Intelligent bracelet, panel computer.
Concrete, as shown in Figure 3, described control integration circuit die 101 comprises the SPI interface support module 1011 for supporting SPI interface communications protocol, and obtains from SPI interface the quick respond module 1012 that it starts data for quick response external electronic equipment.
Described quick respond module 1012 comprises the Platform Analysis unit 1012a for analyzing external electronic device operation platform, and during for determining that described external electronic device starts according to described external electronic device operation platform, each code data needed for step code data when external electronic device being started needed for next step store integrated-circuit die 102 from described Nand Flash in advance and read the unit 1012b and the code be cached in the internal memory of control integration circuit die 101 prestores.Prestored by Platform Analysis unit 1012a and code the setting of unit 1012b, can ensure control integration circuit die 101 fast response external electronic equipment from SPI interface obtain its start required for code data.
Concrete, the size of the start-up code data of each buffer memory is determined according to the size of the internal memory of described control integration circuit die 101, as at every turn can the buffer memory code of buffer memory 8k size, after the code data of the 8k size of buffer memory reads from internal memory, the then start-up code data of the next 8k size of buffer memory.
In a specific embodiment, as shown in Figure 2, described second interface contact 104 also comprises state maintaining line contact (SPI-HOLD) and write-protect line contact (SPI-WP).
In a specific embodiment, as shown in Figure 2, described first interface is SD interface, described first interface contact 103 is SD interface contact, and described first interface contact 103 at least comprises power lead (VCCSD), ground wire (GND), data line 0 (SDD0), data line 1 (SDD1), data line 2 (SDD2), data line 3 (SDD3), clock line (SDCLK), order wire (SDCMD) eight contacts.
In a specific embodiment, not shown, described first interface is USB interface, and described first interface contact 103 is USB interface contact, and described first interface contact 103 at least comprises power lead, ground wire, correction data line, negative data line four contacts.
In a specific embodiment, not shown, described first interface is eMMC interface, described first interface contact 103 is eMMC interface contact, and described first interface contact 103 at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.
In a specific embodiment, as shown in Figure 2, the body 105 of described embedded storage chip 10 is provided with 30 contacts, except first interface contact 103 and the second interface contact 104, the power cord point (VCCS) also comprising core power line contact (VDDK) and retain, all the other contacts are the stick contact (DNU) temporarily do not used.
In a specific embodiment, as shown in Figure 4, described embedded storage chip length is of a size of 8mm*8mm*0.8mm (mm:millimeter millimeter), and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.Certain described embedded storage chip also can be other sizes, at this not in order to limit the present invention.
In a specific embodiment, as shown in Figure 4, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described contact is circular pad contact or spherical contact or dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, and the 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.Certainly, described contact also can be other shapes, at this not in order to limit the present invention.
In another specific embodiment, the size of described embedded storage chip length can also be 8mm*7.5mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.
Above-mentioned embedded storage chip, by arranging a SPI interface on control integration circuit die, and mark off Nand Flash and store the part storage space of integrated-circuit die for storing the start-up code of external electronic device, by the platform that the Platform Analysis element analysis external electronic device of control integration circuit die is run, thus determine that each step of external electronic device needs the code data loaded when starting, and code data when external electronic device being started in advance needed for next step reads and is cached in the internal memory of control integration circuit die from Nand Flash storage integrated-circuit die, thus ensure that control integration circuit die can obtain data required when it starts from SPI interface by response external electronic equipment fast, external electronic device is made only to need use embedded storage chip, just can realize various memory function, thus the area that minimizing external electronic device printed circuit board (PCB) takies, be convenient to the miniaturization of external electronic device, meanwhile, adopt embedded electronic chip provided by the invention, described external electronic device does not need additionally to use a SPI Nor Flash memory chip again, thus further can reduce the hardware cost of external electronic device, further, because described embedded storage chip possesses first interface, therefore the external electronic device of described embedded storage chip is adopted, ROMPaq can be copied to described Nand Flash by first interface and store the storage space that integrated-circuit die provides, carry out copy upgrading, relative to the mode that traditional SPI Nor Flash memory chip is upgraded by burning, greatly facilitate the use of domestic consumer.
The present invention also provides a kind of EMBEDDED AVIONICS, and this EMBEDDED AVIONICS comprises embedded storage chip described above.
EMBEDDED AVIONICS provided by the invention, owing to not needing to configure separately a SPI Nor Flash memory chip again, can not only greatly reduce its hardware cost, more can also be convenient to the Miniaturization Design of its structure.
The present invention also provides a kind of programme upgrade method of EMBEDDED AVIONICS, this EMBEDDED AVIONICS comprises embedded storage chip described above, the method comprises the steps: that copying ROMPaq to Nand Flash by first interface stores the storage space that provides of integrated-circuit die, upgrading.
The programme upgrade method of EMBEDDED AVIONICS provided by the invention, adopts the mode of copy upgrading, relative to the mode of traditional SPI Nor Flash memory chip burning upgrading, greatly facilitates the use of domestic consumer.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an embedded storage chip, comprise body, be encapsulated in intrinsic control integration circuit die and Nand Flash storage integrated-circuit die, and the first interface contact be arranged on body, described control integration circuit die is provided with first interface, described Nand Flash stores integrated-circuit die and is electrically connected with described control integration circuit die, described first interface contact is electrically connected with described first interface, it is characterized in that, described embedded storage chip also comprises the second interface contact be arranged on body, described control integration circuit die is also provided with the second interface, described second interface contact is electrically connected with described second interface, described second interface is SPI interface, described second interface contact is SPI interface contact, described second interface contact at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts, described Nand Flash stores integrated-circuit die and marks off the storage space of a part of storage space as external electronic device start-up code, described control integration circuit die comprises for supporting the SPI interface support module of SPI interface communications protocol and obtaining the quick respond module of data for quick response external electronic equipment from SPI interface.
2. embedded storage chip according to claim 1, it is characterized in that, described quick respond module comprise Platform Analysis unit for analyzing external electronic device operation platform and for confirming that external electronic device starts according to described external electronic device operation platform time each step code data, and code data when described external electronic device being started needed for next step stores integrated-circuit die from described Nand Flash in advance and reads the unit and the code be cached in control integration circuit die internal memory prestores.
3. embedded storage chip according to claim 1, is characterized in that, described second interface contact also comprises state maintaining line contact and write-protect line contact.
4. embedded storage chip according to claim 1, it is characterized in that, described first interface is SD interface, described first interface contact is SD interface contact, and described first interface contact at least comprises power lead, ground wire, data line 0, data line 1, data line 2, data line 3, clock line, order wire eight contacts; Or
Described first interface is USB interface, and described first interface contact is USB interface contact, and described first interface contact at least comprises power lead, ground wire, correction data line, negative data line four contacts; Or
Described first interface is eMMC interface, and described first interface contact is eMMC interface contact, and described first interface contact at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.
5. the embedded storage chip according to any one of claim 1-4, it is characterized in that, the body of described embedded storage chip is provided with 30 contacts, except first interface contact and the second interface contact, also comprise the power cord point of core power line contact and reservation, all the other contacts are the stick contact temporarily do not used.
6. embedded storage chip according to claim 5, is characterized in that, described embedded storage chip length is of a size of 8mm*8mm*0.8mm, and wherein the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.
7. embedded storage chip according to claim 5, is characterized in that, described embedded storage chip length is of a size of 8mm*7.5mm*0.8mm, and wherein the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.
8. the embedded storage chip according to any one of claim 6 or 7, it is characterized in that, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described contact is circular pad contact or for spherical contact or for dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, and the 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.
9. an EMBEDDED AVIONICS, is characterized in that, described EMBEDDED AVIONICS comprises the embedded storage chip according to any one of claim 1-8.
10. the programme upgrade method of an EMBEDDED AVIONICS, it is characterized in that, described EMBEDDED AVIONICS is EMBEDDED AVIONICS as claimed in claim 9, described method comprises the steps: that copying ROMPaq to Nand Flash by first interface stores the storage space that provides of integrated-circuit die, upgrading.
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Cited By (2)
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| CN108256269A (en) * | 2018-02-23 | 2018-07-06 | 晶晨半导体(上海)股份有限公司 | A kind of processor chips and printed circuit board |
| CN113312071A (en) * | 2021-06-10 | 2021-08-27 | 山东英信计算机技术有限公司 | SSD device firmware upgrading method and related device |
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| CN104599711B (en) | 2018-01-26 |
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Address after: 518057 A, B, C, D, E, F1, 8 Building, Financial Services Technology Innovation Base, No. 8 Kefa Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen jiangbolong electronic Limited by Share Ltd Address before: 518057 A, B, C, D, E, F1, 8th floor, Kefa Road Financial Base, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen jiangbolong Electronic Co., Ltd. |