CN104267910B

CN104267910B - FPGA-based (field programmable gate array based) Arinc708 data processing IP (intellectual property) core design method

Info

Publication number: CN104267910B
Application number: CN201410407450.2A
Authority: CN
Inventors: 毛峡; 韩兴邦; 薛雨丽; 陈立江; 李添; 赵鹏飞
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2014-08-19
Filing date: 2014-08-19
Publication date: 2017-05-24
Anticipated expiration: 2034-08-19
Also published as: CN104267910A

Abstract

The invention provides an FPGA-based (field programmable gate array based) Arinc708 data processing IP (intellectual property) core design method. The method includes the steps of 1, decoding a single Arinc708 bit stream to obtain NRZ (non-return zero) codes and synchronous clock signals; 2, extracting head information from the NRZ codes according to the Arinc708 data frame format through the obtained synchronous clock signals, and temporarily storing the head information; 3, extracting and recombining information of 512 distance cells from the NRZ codes according to the Arinc708 data frame format through the obtained synchronous clock signals, and temporarily storing the information; 4, subjecting the head information and the information of distance cells, both temporarily stored, to Ping Pong storage in units of data frame; and 5, establishing a reading and writing time sequence for a Ping Pong storage module and a back-end driver. The method has the advantages that designing is performed according to structural features of the Arinc708 bit streams and data frames, real-time processing speed is ensured, and required data is extracted and recombined into a data structure allowing convenient back-end display calling.

Description

A kind of Arinc708 data processing IP core design methods based on FPGA

Technical field：

The present invention relates to aviation electronics, field of signal processing, the integrated circuit IP kernel of FPGA signal transactings is based particularly on Method for designing.

Background technology：

Arinc708 is primarily used for the airborne pulse Doppler weather radar protocol specification of commercial aircraft.It uses a kind of Transformer coupled manchester encoded signals carry out data transmission, such as MIL-STD-1553 bus protocols；Bit stream is Single channel is continuous；Data frame is that (interframe has the low level intervals of Microsecond grade to 1600 bit lengths, is still Manchester's code knot per frame Structure), 1MHz code checks, including the header being made up of state parameters such as angle of inclination, scope, gains and corresponding each scan angle (each range cell is represented in the position 512 be organized into data messages of range cell of degree comprising a color value Intensity).

The single channel output bit flow of Arinc708 contains the full detail that airborne weather radar is gathered, but can not be straight Connect visualization display.At present, single channel Arinc708 information is extracted and is recombinated and be organized into the data structure beneficial to display, The country is also without corresponding scheme.

The content of the invention：

In order to solve to carry out Arinc708 bitstream datas the demand of real-time processing, it is utilized rear end equipment The data structure of display, the present invention proposes a kind of Arinc708 data processing IP core design methods based on FPGA.The present invention Multiple programming feature based on FPGA, for the data frame structure of Arinc708, the IP kernel of the design treatment single channel bit stream is right Its data is extracted and recombinated, and makes the data structure beneficial to display.

In order to reach object above, the present invention uses following specific design method：

Step one：Single channel Arinc708 data bit flows are decoded, NRZ yards and synchronizing clock signals are obtained；

Step 2：Extracted from NRZ yards according to Arinc708 data frame formats using the synchronizing clock signals for obtaining and lifted one's head Information is simultaneously kept in；

Step 3：Extracted from NRZ yards according to Arinc708 data frame formats using the synchronizing clock signals for obtaining and laid equal stress on 512 range cell information of group are simultaneously kept in；

Step 4：Header that will be temporary and range cell information with data frame be unit Pingpang Memory；

Step 5：Set up the read-write sequence of Pingpang Memory module and backend driver.

Wherein, in step one, Arinc708 data are sampled using the sampling clock for being not less than 2MHz, according to adopting Sample clock frequency sets decoding counter cycle, and decoding judgment threshold and synchronizing clock signals are set by the sample counter cycle Judgment threshold, NRZ yards and synchronizing clock signals are obtained by the decoding of judgement sampled value；Using the low level interframe space of Microsecond grade And the starting of the special synchronous head structure judgment frame of Arinc708 data frames, before Arinc708 data frame valid data Whether 8 fixed signal positions are correct to judge data source transmission data；

In step 2, the 9th to the 64th information header is all extracted according to Arinc708 data frame formats is gone forward side by side Row segmentation is arranged, kept in；

In step 3, according to Arinc708 data frame formats, from the 65th start to process remaining 65th to 1536 range cell information between 1600, the serioparallel exchange that 1536 data carry out 3 group is obtained 512 groups away from From the color value of unit, 512 color values of range cell are kept in array；

In step 4, binary channels Pingpang Memory device is set up, two memories are alternately stored and data cover, it is ensured that two are deposited Reservoir stores the header of adjacent two frame and the range cell information of restructuring respectively；For rear end read operation, it is ensured that in front end When being alternately written into memory, synchronization is alternately read not in the memory of write-in in rear end, it is ensured that read-write does not conflict；

In step 5, the Pingpang Memory pattern according to step 4 is set up during read-write and is with backend driver Main communication sequential, it is ensured that read data reliable and stable.

Advantages of the present invention and good effect are：Bit stream feature for Arinc708 is designed, and uses FPGA ensures real-time processing speed, and sample frequency can be adjusted according to actual conditions, and design is according to Arinc708 data frame lattice Formula is customized, and makes full use of the design feature and data organizational form of Arinc708 data frames to efficiently extract required data, And restructuring shows the data structure called for convenience of rear end, while error detection can be carried out.

Brief description of the drawings：

Fig. 1 is data decoder module state transition graph in the present invention

Fig. 2 is referenced Arinc708 data-frame syncs header structure schematic diagram in the present invention

Fig. 3 is valid data extraction in the present invention and recombination module state transition graph

Fig. 4 is Pingpang Memory function structure chart in the present invention

Fig. 5 is overall architecture of the invention and module assignment (dotted box portion)

Specific embodiment：

The present invention is a kind of Arinc708 data processing IP core design methods based on FPGA, height of the present invention based on FPGA The parallel processing capability and programming feature of speed, are designed for Arinc708 data frame features, and specific implementation is the present invention need To be based on the IP kernel development environment of FPGA.

Main contents of the invention are：According to Arinc708 data forms, original Arinc708 bitstream datas are led to Crossing FPGA carries out real-time processing, and by header therein, range cell information extraction is simultaneously recombinated for convenience of rear end display program tune Data structure is simultaneously kept in, and below in conjunction with the accompanying drawings, technical scheme is described further.Key step is as follows：

Step one：Carry out the single error detection of every frame and manchester decoder in real time to single channel bit stream, obtain NRZ yards and same Step clock signal；This step can form a module, utilization state machine frame, set as shown in Figure 13 states " idle ", " head " and " data ", respectively corresponding data interframe gap, data-frame sync head (the 3 bit bit wide in Fig. 2 with special construction Part) and 1600 valid data；Data for the state under each state are processed, and set corresponding flag bit Carry out redirecting for state of a control.

Step 2, step 3：Carried from NRZ yards according to Arinc708 data frame formats using the synchronizing clock signals for obtaining Take out header and keep in, extracted simultaneously from NRZ yards according to Arinc708 data frame formats using the synchronizing clock signals for obtaining 512 range cell information of restructuring are simultaneously kept in；Two step can form a module, and utilization state machine frame sets as shown in Figure 3 Put 6 states " idle ", " head ", " check ", " prepare ", " angle " and " pix "；Wherein " idle ", " head " are corresponding Difference corresponding data interframe gap, the data-frame sync head with special construction is identical with step one；“check”、 " prepare ", " angle " then correspond to header part (being arranged here as three sections)；" pix " respective distances unit information Section；Data for the state under each state are processed, and are set corresponding flag bit and are carried out redirecting for state of a control；Head letter Cease and need to keep in header in corresponding state, usable shift register is kept in；Range cell part needs Carry out 3 one group of serioparallel exchange and translated data is sequentially stored into dimension group.

Step 4：Header that will be temporary and range cell information with data frame be unit Pingpang Memory；The step can shape Into a module, as shown in figure 4, set up two identicals memory channel A and B, deposit adjacent two data frame header and away from From unit information, select 1MUX by write operation 2 to be alternately written into, by read operation 2 select 1MUX carry out alternately reading, and Read memory channel B during control write-in memory channel A, memory channel A is read during write-in memory channel B.

Step 5：Set up the read-write sequence of Pingpang Memory module and backend driver；Need to show program according to rear end Call Demand Design, need to consider rear end show program the relation for calling speed and FPGA processing speeds, need to consider whether need Multiplexed signals line is wanted to save hardware resource.

Master-plan framework is as shown in Figure 5.

The English occurred in Figure of description and abbreviation, its implication are as follows：

Fig. 1：

idle：Data interframe gap state；

head：Data-frame sync head status with special construction；

data：1600 valid data states；

reset：Systematic reset signal；

idle_check：Synchronous head starting is not found in synchronous head search condition signal, ' 0 ' expression, and synchronization is found in ' 1 ' expression Head starting；

data_start：Valid data are not arrived in data opening flag signal, ' 0 ' expression, and ' 1 ' represents valid data state；

data_end：Data frame decoding end mark signal, ' 0 ' represents that the data frame does not complete decoding, and ' 1 ' represents the number Terminate according to frame decoding；

Fig. 2：

3bits wide：The synchronous head of the special construction of 2 bit bit wides；

Transmission 1600bits：1600 valid data；

Fig. 3：

idle：Data interframe gap state；

head：Data-frame sync head status with special construction；

check：1600 valid data 1-8 potential heads information (fixed signal position) states in Arinc708 data frames；

prepare：1600 valid data 9-51 potential head information states in Arinc708 data frames；

angle：1600 valid data 52-64 potential heads information (containing scanning angle) states in Arinc708 data frames；

pix：1600 valid data range cell states in Arinc708 data frames；

word_en：The flag bit that starts of word is represented, into being in high level, remaining state low level during head states；

data_cnt：1600 valid data counters, characterize current decoder progress；

shifter_check：1600 valid data 1-8 potential heads information (fixed signal position) inspection in Arinc708 data frames Survey shift register, can be used to detect whether to be correctly decoded.

Claims

1. a kind of Arinc708 data processing IP core design methods based on FPGA, the method is comprised the following steps that：

Step 2：Using the synchronizing clock signals for obtaining header is extracted according to Arinc708 data frame formats from NRZ yards And keep in；

Step 3：512 are extracted from NRZ yards according to Arinc708 data frame formats and recombinated using the synchronizing clock signals for obtaining Individual range cell information is simultaneously kept in；

2. method according to claim 1, its step one includes：Using being not less than the sampling clock of 2MHz to Arinc708 numbers According to being sampled, decoding counter cycle is set according to sample clock frequency, setting decoding by the sample counter cycle judges Threshold value and synchronizing clock signals judgment threshold, NRZ yards and synchronizing clock signals are obtained by the decoding of judgement sampled value；Using microsecond The starting of the special synchronous head structure judgment frame of low level interframe space and Arinc708 data frames of level, by Arinc708 Whether preceding 8 fixed signals position of data frame valid data is correct to judge data source transmission data.

3. method according to claim 1, its step 2 includes：According to Arinc708 data frame formats by the 9th to the 64th Information header is all extracted and carries out segmentation arrangement, keeps in.

4. method according to claim 1, its step 3 includes：According to Arinc708 data frame formats, since the 65th 1536 range cell information between remaining 65th to the 1600th are processed, 3 one group is carried out to 1536 data Serioparallel exchange obtain 512 groups of color values of range cell, with array keep in 512 color values of range cell.

5. method according to claim 1, its step 4 includes：Binary channels Pingpang Memory device is set up, two memory channels replace Storage and data cover, it is ensured that two memory channels store the header of adjacent two frame and the range cell letter of restructuring respectively Breath；For reading memory, it is ensured that when front end is alternately written into memory, synchronization is alternately read not in the storage of write-in in rear end Device, it is ensured that read-write stabilization.

6. method according to claim 1, its step 5 includes：Pingpang Memory pattern according to step 4, in read-write process Communication sequential of the middle foundation based on backend driver, it is ensured that read data reliable and stable.