CN104267910A - FPGA-based (field programmable gate array based) Arinc708 data processing IP (intellectual property) core design scheme - Google Patents
FPGA-based (field programmable gate array based) Arinc708 data processing IP (intellectual property) core design scheme Download PDFInfo
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- CN104267910A CN104267910A CN201410407450.2A CN201410407450A CN104267910A CN 104267910 A CN104267910 A CN 104267910A CN 201410407450 A CN201410407450 A CN 201410407450A CN 104267910 A CN104267910 A CN 104267910A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
Abstract
The invention provides an FPGA-based (field programmable gate array based) Arinc708 data processing IP (intellectual property) core design scheme. The scheme includes the steps of 1, decoding a single Arinc708 bit stream to obtain NRZ (non-return zero) codes and synchronous clock signals; 2, extracting head information from the NRZ codes according to the Arinc708 data frame format through the obtained synchronous clock signals, and temporarily storing the head information; 3, extracting and recombining information of 512 distance cells from the NRZ codes according to the Arinc708 data frame format through the obtained synchronous clock signals, and temporarily storing the information; 4, subjecting the head information and the information of distance cells, both temporarily stored, to Ping Pong storage in units of data frame; and 5, establishing a reading and writing time sequence for a Ping Pong storage module and a back-end driver. The scheme has the advantages that designing is performed according to structural features of the Arinc708 bit streams and data frames, real-time processing speed is ensured, and required data is extracted and recombined into a data structure allowing convenient back-end display calling.
Description
Technical field:
The present invention relates to aviation electronics, signal transacting field, particularly based on the integrated circuit IP kernel method for designing of FPGA signal transacting.
Background technology:
Arinc708 is the airborne pulse Doppler weather radar protocol specification being mainly used in commercial aircraft.It uses a kind of transformer-coupled manchester encoded signals to carry out data transmission, such as MIL-STD-1553 bus protocol; Bit stream is single channel continuous print; Frame is 1600, and long (interframe has the low level intervals of Microsecond grade, every frame is still Manchester's cde structure), 1MHz code check, comprises the data message (each range unit comprises a color value and represents intensity in this position) of 512 range units that the header that is made up of state parameters such as angle of inclination, scope, gains and corresponding each scanning angle are organized into.
The single channel output bit flow of Arinc708 contains the full detail that airborne weather radar gathers, but can not direct visual display.At present, carry out extracting to single channel Arinc708 information and recombinate and be organized into the data structure being beneficial to display, domestic also do not have corresponding scheme.
Summary of the invention:
In order to solve the demand of Arinc708 bitstream data being carried out to process in real time, making rear end equipment can obtain utilizing the data structure of display, the present invention proposes a kind of Arinc708 data processing IP kernel design proposal based on FPGA.The present invention is based on the multiple programming feature of FPGA, for the data frame structure of Arinc708, the IP kernel of this single channel bit stream of design treatment, carries out extracting to its data and recombinates, making it into the data structure for the benefit of shown.
In order to reach above object, the present invention adopts following technical scheme:
Step one: decode to single channel Arinc708 data bit flow, obtains NRZ code and synchronizing clock signals;
Step 2: utilize the synchronizing clock signals obtained extract header according to Arinc708 data frame format from NRZ code and keep in;
Step 3: the synchronizing clock signals that utilization obtains extracts from NRZ code according to Arinc708 data frame format and 512 range unit information of recombinating are also temporary;
Step 4: by temporary header and range unit information Pingpang Memory in units of Frame;
Step 5: the read-write sequence setting up Pingpang Memory module and rear end driver.
Wherein, in step, the sampling clock being not less than 2MHz is used to sample to Arinc708 data, according to sample clock frequency, decoding counter cycle is set, arrange decoding judgment threshold and synchronizing clock signals judgment threshold by the sample counter cycle, being decoded by judgement sampled value obtains NRZ code and synchronizing clock signals; Utilize the initial of the low level interFrameGap of Microsecond grade and the special synchronous head structure judgment frame of Arinc708 Frame, whether correctly judge that data source sends data by front 8 fixed signal positions of Arinc708 Frame valid data;
In step 2, according to Arinc708 data frame format the 9th to the 64th information header information all extracted and carry out segmentation arrangement, temporary;
In step 3, according to Arinc708 data frame format, (to the 1600th) 1536 distance of positions that process is remaining from the 65th are from unit information, the serioparallel exchange carrying out 3 one group to this 1536 bit data obtains the color value of 512 groups of range units, keeps in the color value of 512 range units by array;
In step 4, set up binary channels Pingpang Memory device, two storeies alternately store and data cover, guarantee that two storeies store the header of adjacent two frames and the range unit information of restructuring respectively; For rear end read operation, when ensureing alternately to write storer in front end, synchronization is alternately read not at the storer of write in rear end, guarantees that read-write does not conflict;
In step 5, according to the Pingpang Memory pattern of step 4, in read-write process, set up the communication sequential based on rear end driver, guarantee that read data is reliable and stable.
Advantage of the present invention and good effect are: the bit stream feature for Arinc708 designs, FPGA is used to guarantee real-time processing speed, sample frequency can adjust according to actual conditions, design proposal customizes according to Arinc708 data frame format, desired data extracts by design feature and Organization of Data form effectively that make full use of Arinc708 Frame, and restructuring shows for convenience of rear end the data structure called, error detection can be carried out simultaneously.
Accompanying drawing illustrates:
Fig. 1 is data decode module status transition diagram in the present invention
Fig. 2 is referenced Arinc708 data-frame sync header structure schematic diagram in the present invention
Fig. 3 is that in the present invention, valid data extract and recombination module state transition graph
Fig. 4 is Pingpang Memory function structure chart in the present invention
Fig. 5 is overall architecture of the present invention and module assignment (dotted box portion)
Embodiment:
The present invention is a kind of Arinc708 data processing IP kernel design proposal based on FPGA, this programme is based on the parallel processing capability of the high speed of FPGA and programming feature, design for Arinc708 Frame feature, the concrete the present invention of enforcement needs the IP kernel development environment based on FPGA.
Main contents of the present invention are: according to Arinc708 data layout, original Arinc708 bitstream data is processed in real time by FPGA, by header wherein, the range unit information extraction data structure that also restructuring is called for convenience of rear end display routine is also kept in, below in conjunction with accompanying drawing, technical scheme of the present invention is described further.Key step is as follows:
Step one: the independent error detection of every frame and manchester decoder are carried out in real time to single channel bit stream, obtains NRZ code and synchronizing clock signals; This step can form a module, utilization state machine frame, 3 states " idle ", " head " and " data " are set as shown in Figure 1, corresponding data interframe gap, has data-frame sync head (in Fig. 23 bit bit wide parts) and 1600 valid data of special construction respectively; Data for this state under each state process, and arrange the redirect that corresponding zone bit carrys out state of a control.
Step 2, step 3: utilize the synchronizing clock signals obtained from NRZ code, extract header according to Arinc708 data frame format and keep in, utilize the synchronizing clock signals obtained to extract from NRZ code according to Arinc708 data frame format and 512 range unit information of recombinating are also temporary; This two step can form a module, utilization state machine frame, arranges 6 states " idle ", " head ", " check ", " prepare ", " angle " and " pix " as shown in Figure 3; Wherein " idle ", " head " correspondence corresponding data interframe gap respectively, have the data-frame sync head of special construction, identical with step one; " check ", " prepare ", " angle " be corresponding header part (arranged here is three sections) then; " pix " respective distances unit information section; Data for this state under each state process, and arrange the redirect that corresponding zone bit carrys out state of a control; Need in the state that header is corresponding to keep in header, shift register can be used to keep in; Range unit part need to carry out 3 one group serioparallel exchange and by translated data successively stored in dimension group.
Step 4: by temporary header and range unit information Pingpang Memory in units of Frame; This step can form a module, as shown in Figure 4, set up two identical memory channel A and B, deposit header and the range unit information of adjacent two Frames, 1MUX is selected to carry out alternately write by write operation 2, select 1MUX to carry out alternately reading by read operation 2, and read memory channel B when controlling write memory channel A, during write memory channel B, read memory channel A.
Step 5: the read-write sequence setting up Pingpang Memory module and rear end driver; Need to call Demand Design according to rear end display routine, the speed of calling of rear end display routine and the relation of FPGA processing speed need be considered, need consider the need of multiplexed signals line to save hardware resource.
Overall design framework as shown in Figure 5.
The English occurred in Figure of description and abbreviation, its implication is as follows:
Fig. 1:
Idle: gap state between Frame;
Head: the data-frame sync head status with special construction;
Data:1600 position valid data state;
Reset: systematic reset signal;
Idle_check: synchronous head search condition signal, ' 0 ' expression does not find synchronous head initial, and ' 1 ' expression finds synchronous head initial;
Data_start: data opening flag signal, ' 0 ' expression does not arrive valid data, and ' 1 ' represents valid data state;
Data_end: Frame decoding end mark signal, ' 0 ' represents that this Frame does not complete decoding, and ' 1 ' represents that the decoding of this Frame terminates;
Fig. 2:
The synchronous head of the special construction of 3bits wide:2 bit bit wide;
Transmission 1600bits:1600 position valid data;
Fig. 3:
Idle: gap state between Frame;
Head: the data-frame sync head status with special construction;
1600 valid data 1-8 potential head information (fixed signal position) states in check:Arinc708 Frame;
1600 valid data 9-51 potential head information states in prepare:Arinc708 Frame;
1600 valid data 52-64 potential head information (containing scanning angle) states in angle:Arinc708 Frame;
1600 valid data range unit states in pix:Arinc708 Frame;
Word_en: represent and be in high level when entering head state, all the other state low levels by the zone bit that word starts;
Data_cnt:1600 position valid data counter, characterizes current decoder progress;
Whether 1600 valid data 1-8 potential head information (fixed signal position) detection shift registers in shifter_check:Arinc708 Frame, can be used for detection and be correctly decoded.
Claims (6)
1. the present invention proposes a kind of Arinc708 data processing IP kernel design proposal based on FPGA, the concrete steps of the program are as follows:
Step one: decode to single channel Arinc708 data bit flow, obtains NRZ code and synchronizing clock signals;
Step 2: utilize the synchronizing clock signals obtained extract header according to Arinc708 data frame format from NRZ code and keep in;
Step 3: the synchronizing clock signals that utilization obtains extracts from NRZ code according to Arinc708 data frame format and 512 range unit information of recombinating are also temporary;
Step 4: by temporary header and range unit information Pingpang Memory in units of Frame;
Step 5: the read-write sequence setting up Pingpang Memory module and rear end driver.
2. method according to claim 1, principal character in its step one is: use the sampling clock being not less than 2MHz to sample to Arinc708 data, according to sample clock frequency, decoding counter cycle is set, arrange decoding judgment threshold and synchronizing clock signals judgment threshold by the sample counter cycle, being decoded by judgement sampled value obtains NRZ code and synchronizing clock signals; Utilize the initial of the low level interFrameGap of Microsecond grade and the special synchronous head structure judgment frame of Arinc708 Frame, whether correctly judge that data source sends data by front 8 fixed signal positions of Arinc708 Frame valid data.
3. method according to claim 1, the principal character in its step 2 is: the 9th to the 64th information header information all to be extracted according to Arinc708 data frame format and carry out segmentation arrangement, temporary.
4. method according to claim 1, principal character in its step 3 is: according to Arinc708 data frame format, (to the 1600th) 1536 distance of positions that process is remaining from the 65th are from unit information, the serioparallel exchange carrying out 3 one group to this 1536 bit data obtains the color value of 512 groups of range units, keeps in the color value of 512 range units by array.
5. method according to claim 1, principal character in its step 4 is: set up binary channels Pingpang Memory device, two memory channels alternately store and data cover, guarantee that two memory channels store the header of adjacent two frames and the range unit information of restructuring respectively; For memory read, when ensureing alternately to write storer in front end, synchronization is alternately read not at the storer of write in rear end, guarantees that read-write is stable.
6. method according to claim 1, the principal character in its step 5 is: according to the Pingpang Memory pattern of step 4, sets up the communication sequential based on rear end driver, guarantee that read data is reliable and stable in read-write process.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633428B1 (en) * | 2004-12-15 | 2009-12-15 | Rockwell Collins, Inc. | Weather data aggregation and display system for airborne network of member aircraft |
| CN103279055A (en) * | 2013-04-08 | 2013-09-04 | 北京航空航天大学 | Design scheme of adaptor board for connecting Arinc708 board card with field programmable gate array (FPGA) development board |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633428B1 (en) * | 2004-12-15 | 2009-12-15 | Rockwell Collins, Inc. | Weather data aggregation and display system for airborne network of member aircraft |
| CN103279055A (en) * | 2013-04-08 | 2013-09-04 | 北京航空航天大学 | Design scheme of adaptor board for connecting Arinc708 board card with field programmable gate array (FPGA) development board |
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