CN103633038B - Encapsulating structure and forming method thereof - Google Patents

Encapsulating structure and forming method thereof Download PDF

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Publication number
CN103633038B
CN103633038B CN201310628982.4A CN201310628982A CN103633038B CN 103633038 B CN103633038 B CN 103633038B CN 201310628982 A CN201310628982 A CN 201310628982A CN 103633038 B CN103633038 B CN 103633038B
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layer
insulating barrier
hole
groove
chip
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CN103633038A (en
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王之奇
喻琼
王蔚
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China Wafer Level CSP Co Ltd
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China Wafer Level CSP Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A kind of encapsulating structure and forming method thereof, wherein, the forming method of encapsulating structure includes: the first surface of chip layer has protective layer and soldering pad layer, and the second surface of chip layer has some grooves exposing protective layer；Form the first insulating barrier at the second surface of chip layer and the sidewall of groove and lower surface, be positioned at the thickness of the first insulating barrier of channel bottom, thinner than the thickness of the first insulating barrier of the second surface being positioned at chip layer；The through hole running through the first insulating barrier, protective layer and soldering pad layer is formed at channel bottom；Remove part the first insulating barrier around through hole, and expose channel bottom；Afterwards, conductive layer is formed at the first surface of insulating layer, the lower surface of groove and the sidewall of through hole and lower surface.The encapsulating structure electrical property formed and stability improve.

Description

Encapsulating structure and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of encapsulating structure and forming method thereof.
Background technology
Crystal wafer chip dimension encapsulation (Wafer Level Chip Size Packaging, WLCSP) technology Be wafer is packaged test after again cutting obtain the technology of single finished product chip, the chip chi after encapsulation Very little completely the same with nude film.Crystal wafer chip dimension encapsulation technology has thoroughly overturned conventional package, such as, make pottery Porcelain leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier) etc., complied with market the lightest to microelectronic product, little, Short, thinning and the requirement of low priceization.Chip size energy after crystal wafer chip dimension encapsulation technology encapsulates Enough reaching to be highly miniaturized, chip cost is notable along with the reduction of chip size and the increase of wafer size Reduce.Crystal wafer chip dimension encapsulation technology be IC can be designed, wafer manufacture, packaging and testing, base The end, manufactures the technology integrated, and is the focus in current encapsulation field and following development trend.
Refer to Fig. 1, Fig. 1 is that a kind of of prior art uses crystal wafer chip dimension encapsulation technology to seal The structure of dress.The method forming described encapsulating structure includes: semiconductor crystal wafer 10 has the surface of device Bond with the first substrate 20 of same size；To semiconductor crystal wafer 10 relative to the back of the body of first substrate 20 Face 10a carries out thinning, and selects the back side 10a of described semiconductor crystal wafer 10 with photoetching and etching technics Property etching, formed multiple first groove as Cutting Road, described first groove exposes chip pad 11； Insulating materials is used to fill described first groove, and at described semiconductor crystal wafer 10 back side 10a pressing the second base Plate 30；Electric heating insulated solder layer 40 is formed on second substrate 30 surface；Use the cutting of mechanical cutting processes plate Described first groove position, forms the second groove in electric heating insulated solder layer 40 and second substrate 30, The sidewall of described second groove exposes chip pad 11；Use sputtering technology deposition metal film, and pass through Photoetching, to described metallic film pattern, forms outer lead 12 and is positioned at the ball of semiconductor crystal wafer 10 back side 10a Lower metal layer 13, chip pad 11 is electrically connected by described outer lead 12 with ball lower metal layer 13；At semiconductor Wafer 10 back side 10a forms insulating protective layer 14, and formation defines opening of soldered ball position in protective layer 14 Mouthful, form soldered ball tin cream by screen printing technique, and reflux solder forms soldered ball 15, described soldered ball shape Cheng Yuqiu lower metal layer 13 surface.After completing above-mentioned technique, by described semiconductor crystal wafer 10 along back side 10a The second groove cutting separate, to be formed with wafer-level packaging (CSP) chip of BGA.
But, the stability and reliability of the encapsulating structure that prior art is formed is relatively low, there is reliability and loses The risk of effect.
Summary of the invention
The problem that the present invention solves is to provide a kind of encapsulating structure and forming method thereof, improves the envelope formed The electrical property of assembling structure and stability.
For solving the problems referred to above, the present invention provides the forming method of a kind of encapsulating structure, including: core is provided Lamella, the first surface of described chip layer has protective layer, and described protective layer has soldering pad layer, institute Stating protective layer and soldering pad layer surface has substrate, the second surface of described chip layer has and some exposes guarantor The groove of sheath, the second surface of described chip layer is relative with first surface, the position of described groove and weldering Bed course is corresponding；The is formed at the second surface of described chip layer and the sidewall of groove and lower surface One insulating barrier, is positioned at the thickness of part the first insulating barrier of described channel bottom, ratio is positioned at chip layer second The thickness of part first insulating barrier on surface is thin；Described channel bottom formed run through described first insulating barrier, Protective layer and the through hole of soldering pad layer, the sidewall of described through hole is vertical relative to soldering pad layer surface；Remove described Part the first insulating barrier around through hole, and expose bottom part of trench；Removing around described through hole Part the first insulating barrier after, at described first surface of insulating layer, the lower surface of groove and through hole Sidewall and lower surface formed conductive layer.
Optionally, after part the first insulating barrier removed around through hole, described first insulating layer exposing Go out the partial protection layer of channel bottom.
Optionally, the technique of part the first insulating barrier around described removal through hole is that plasma dry removes photoresist Technique, the gas of described plasma dry degumming process includes oxygen.
Optionally, also include: remove part the first insulating barrier around through hole and protective layer, and expose The part of solder pads layer of channel bottom.
Optionally, the technique of part the first insulating barrier around described removal through hole and protective layer is plasma Body etching technics, the parameter of described plasma etch process includes: etching gas includes CF4、C4F8, Wherein, CF4Volume ratio in etching gas is 25%～40%.
Optionally, plasma dry degumming process is used to remove part the first insulating barrier around through hole, institute The gas stating plasma dry degumming process includes oxygen；After described plasma dry degumming process, Using plasma etching technics removes part the first insulating barrier around through hole and protective layer, described grade from The parameter of daughter etching technics includes: etching gas includes CF4、C4F8, wherein, CF4At etching gas In volume ratio be 25%～40%.
Optionally, the etching gas of described plasma etch process includes CF4, described CF4At etching gas Volume ratio in body is 25%～35%.
Optionally, after forming the first insulating barrier, before removing part the first insulating barrier around through hole, Thickness between the thickness of part first insulating barrier of the second surface of chip layer and be positioned at trench bottom The thickness ratio of part first insulating barrier in portion is more than or equal to 2:1.
Optionally, the formation process of described first insulating barrier is coating process or depositing operation.
Optionally, described coating process is spraying coating process, spin coating proceeding, typography；Described deposition work Skill is physical gas-phase deposition, chemical vapor deposition method.
Optionally, the material of described first insulating barrier is inorganic thin film material or high-molecular organic material.
Optionally, described inorganic thin film material is silica, silicon nitride, silicon oxynitride and metal oxide In one or more combination；Described high-molecular organic material is polyimide resin, benzocyclobutene, gathers Paraxylene, naphthalene polymer, fluorocarbon or acrylate.
Optionally, the sidewall of described groove tilts relative to substrate surface, and the size of described channel bottom Size less than groove top.
Optionally, also include: remove partial electroconductive layer by photoetching and etching technics, make described conductive layer Realize graphical, to form circuit；After described conductive layer forms circuit, at described conductive layer surface Form the second insulating barrier；Be positioned at chip layer second surface second insulating barrier formed opening, described in open Mouth exposes partial electroconductive layer surface；Conductive layer surface in described opening forms soldered ball.
Accordingly, the present invention also provides for a kind of encapsulating structure using any of the above-described method to be formed, bag Including: chip layer, the first surface of described chip layer has protective layer, and described protective layer has weld pad Layer, described protective layer and soldering pad layer surface have substrate, the second surface of described chip layer have some cruelly Exposing the groove of protective layer, the second surface of described chip layer is relative with first surface, the position of described groove Put corresponding with soldering pad layer；It is positioned at the second surface of described chip layer and the sidewall of groove and bottom table First insulating barrier in face；Being positioned at the through hole of described channel bottom, described through hole runs through described protective layer and weldering Bed course, the sidewall of described through hole is vertical relative to soldering pad layer surface, and is positioned at the part around described through hole First insulating layer exposing goes out bottom part of trench；It is positioned at the bottom table of described first surface of insulating layer, groove Face and the sidewall of through hole and the conductive layer of lower surface.
Optionally, part the first insulating layer exposing being positioned at around described through hole goes out the part of channel bottom and protects Sheath.
Optionally, part the first insulating barrier being positioned at around described through hole and protective layer expose channel bottom Part of solder pads layer.
Compared with prior art, technical scheme has the advantage that
In the forming method of described encapsulating structure, there is in chip layer the protection exposing soldering pad layer surface Layer groove, and be formed at the thickness of part the first insulating barrier of described channel bottom, ratio is positioned at chip list The thickness of part first insulating barrier of face or trench sidewall surface is thin, is then formed at channel bottom and runs through institute After stating the through hole of the first insulating barrier, protective layer and soldering pad layer, it is possible to remove the part first of channel bottom Insulating barrier, part the first insulating barrier being simultaneously formed at chip layer second surface and trench sidewall surface can Retained, in order in subsequent technique, to protect described chip layer surface.In the portion removed around described through hole After dividing the first insulating barrier, at described channel bottom, from the stepped structure of trenched side-wall to through-hole side wall Decline so that the linking trend of channel bottom to through-hole side wall slows down, and therefore, is subsequently formed conductive layer Material easily enters inside through hole, so that conductive layer is good at sidewall and the lower surface adhesive ability of through hole, And in making to be formed at through hole, the thickness of the conductive layer of the sidewall of groove and lower surface uniform.Therefore, The mechanical strength of the conductive layer formed improves, stability improves.
Further, the technique removing part the first insulating barrier around through hole is plasma dry degumming process, Then after part the first insulating barrier removed around through hole, it is possible to expose around the through hole of channel bottom Partial protection layer.Described degumming process has selectivity for the first insulating barrier and protective layer, it is possible to While removing the first insulating barrier, retain the protective layer on soldering pad layer surface, enable described protective layer rear In continuous technique, butt welding mat surface is protected.Meanwhile, described degumming process has directionality, it is possible to Time be perpendicular to chip layer surface and be parallel to the direction on chip layer surface described first insulating barrier is carved Erosion, i.e. can be simultaneously to be perpendicular to direction etching first insulation on trench bottom surfaces and through-hole side wall surface Layer, therefore, it is possible to make part the first insulating barrier around described through hole be removed.Thus improve follow-up shape The mechanical strength of the conductive layer become and stability.
Further, after part the first insulating barrier removed around through hole, remove the part around through hole Protective layer, and expose the part first around the part of solder pads layer of channel bottom, and described removal through hole The technique of insulating barrier and protective layer is plasma etch process.Described plasma etch process can be same Time the first insulating barrier and protective layer are performed etching, therefore can expose logical after plasma process Soldering pad layer surface around hole, increases the contact area between the conductive layer being subsequently formed and soldering pad layer with this, Thus strengthen the electrical connection properties between conductive layer and soldering pad layer.And, described plasma etch process There is directionality, it is possible to be perpendicular to chip layer surface and be parallel to the direction on chip layer surface to institute simultaneously State the first insulating barrier and protective layer performs etching, i.e. can be perpendicular to trench bottom surfaces and through hole simultaneously Described first insulating barrier and protective layer are performed etching by the direction of sidewall surfaces, so that the portion around through hole The first insulating barrier and protective layer is divided to be removed, it is possible to increase the mechanical strength of the conductive layer being subsequently formed is with steady Qualitative.
Further, after part the first insulating barrier removed around through hole, remove the part around through hole Protective layer, and expose the part of solder pads layer of channel bottom；Wherein, the part around described removal through hole The technique of the first insulating barrier is plasma dry degumming process, and the technique removing protective layer is that plasma is carved Etching technique.Described degumming process has selectivity for the first insulating barrier and protective layer, exhausted removing first Reservation protection layer while edge layer；And, described degumming process has directionality, it is possible to simultaneously with vertically Etch the first insulating barrier in the direction of trench bottom surfaces and through-hole side wall surface, make around described through hole Part the first insulating barrier is removed.After described degumming process, the most right with plasma etch process Described first insulating barrier and protective layer perform etching, to remove the protective layer around through hole and the first insulating barrier And expose the part of solder pads layer around the through hole of channel bottom, it is possible to strengthen the conductive layer that is subsequently formed with Electrical-contact area between soldering pad layer.And, described plasma etch process also has directionality, energy Enough etch the first insulating barrier and protection being perpendicular to the direction on trench bottom surfaces and through-hole side wall surface simultaneously Layer, the first insulating layer exposing after etching goes out partial protection layer surface, and described protective layer exposes part Soldering pad layer surface so that the transition of the first insulating barrier, protective layer and the soldering pad layer of channel bottom to through hole is more For gently so that the material being subsequently formed conductive layer is easier to enter inside through hole, then the conduction formed Mechanical strength and the stability of layer improve further.
In described encapsulating structure, there is in chip layer the groove exposing soldering pad layer sealer, institute State channel bottom to have and run through described first insulating barrier, protective layer and the through hole of soldering pad layer, be positioned at described logical Part the first insulating layer exposing around hole goes out bottom part of trench, and described channel bottom is from trenched side-wall extremely The stepped structure of through-hole side wall declines so that the linking trend of channel bottom to through-hole side wall slows down, because of This conductive layer is good at sidewall and the lower surface adhesive ability of through hole, thickness is uniform.Therefore, described conduction The mechanical strength of layer improves, stability improves.
Accompanying drawing explanation
Fig. 1 is a kind of section using crystal wafer chip dimension encapsulation technology to be packaged knot of prior art Structure schematic diagram；
Fig. 2 is the cross-sectional view of a kind of encapsulating structure embodiment；
Fig. 3 to Fig. 8 is the cross-section structure signal of the forming process of the encapsulating structure of first embodiment of the invention Figure；
Fig. 9 is the encapsulating structure of second embodiment of the invention cross-sectional view in forming process；
Figure 10 is the cross-sectional view in the forming process of the encapsulating structure of third embodiment of the invention.
Detailed description of the invention
As stated in the Background Art, the stability and reliability of the encapsulating structure that prior art is formed is relatively low, deposits Risk in reliability failures.
Finding through research, please continue to refer to Fig. 1, the sidewall of described second groove exposes chip pad The sidewall of 11, described outer lead 12 is formed at the sidewall surfaces of described second groove, and welds with described chip The sidewall electrical connection of pad 11, described outer lead 12 is " T " shape with the junction of chip pad 11.So And, owing to described "T"-shaped junction physical strength is more weak, during carrying out chip package, institute State "T"-shaped junction and be easily subject to stress effect and chipping, cause outer lead 12 to weld with chip Electrical connection properties between pad 11 is unstable, and the reliability of encapsulating structure is poor.
In order to improve stability and the reliability of encapsulating structure, it is proposed that a kind of encapsulating structure, refer to Fig. 2, The forming method of described encapsulating structure includes: provide half encapsulating structure, described half encapsulating structure to include pressing Wafer 100 and substrate 101, described wafer 100 is formed relative to the back side 100a of substrate 101 The groove 103 of expose portion chip pad 102；First is formed exhausted at the back side 100a of described wafer 100 Edge layer 104；Formed in the bottom of described groove 103 and penetrate the first insulating barrier 104 and chip pad 102 Through hole 105, described through hole 105 is positioned on line of cut, and penetrates the chip weldering of adjacent semiconductor chips simultaneously Pad 102；Described wafer 100 back side 100a make outer lead 106, ball lower metal layer 107 and Soldered ball 108, one end of described outer lead 106 is formed in through hole 105, and the other end passes through ball lower metal layer 107 with soldered ball 108 electric connection.
Wherein, described through hole 105 only needs to penetrate described chip pad layer 103, the one of described outer lead 106 End is formed at sidewall and the lower surface of through hole 105, it is possible to strengthen outer lead 106 and chip pad layer 103 Between concatenation ability.
But, please continue to refer to Fig. 2, owing to through hole 105 sidewall that formed is relative to the end of groove 103 Surface, portion is vertical, the most easily makes outer lead 106 corner to through hole 105 sidewall bottom groove 103 Place's skewness, the electrical connection properties causing outer lead 106 is unstable, is even easily subject to excessive answering Power and rupture.And, the outer lead being formed in through hole 105 is only capable of sudden and violent with through hole 105 sidewall The chip pad 102 exposed contacts so that the contact surface between outer lead 106 and chip pad 102 Long-pending little, more it is easily caused electrical connection properties between outer lead 105 and chip pad 102 unstable, the most disconnected Open.
In order to solve the problems referred to above, the present invention proposes the forming method of a kind of encapsulating structure, including: provide Chip layer, the first surface of described chip layer has protective layer, and described protective layer has soldering pad layer, Described protective layer and soldering pad layer surface have substrate, and the second surface of described chip layer has some exposing The groove of protective layer, the second surface of described chip layer is relative with first surface, the position of described groove with Soldering pad layer is corresponding；Formed at the second surface of described chip layer and the sidewall of groove and lower surface First insulating barrier, is positioned at the thickness of part the first insulating barrier of described channel bottom, ratio is positioned at chip surface Or the thickness of part first insulating barrier of trench sidewall surface is thin；Formed at described channel bottom and run through described The through hole of the first insulating barrier, protective layer and soldering pad layer, the sidewall of described through hole hangs down relative to soldering pad layer surface Directly；Remove part the first insulating barrier around described through hole, and expose bottom part of trench, make described The thickness of the first insulating barrier is the thinnest the closer to through hole, and the first surface of insulating layer being positioned at channel bottom is relative Tilt in the surface of soldering pad layer；After part the first insulating barrier removed around described through hole, described First surface of insulating layer, the lower surface of groove and the sidewall of through hole and lower surface form conductive layer.
Wherein, there is in chip layer the groove of the protective layer exposing soldering pad layer surface, and be formed at described The thickness of part first insulating barrier of channel bottom, ratio are positioned at the part of chip surface or trench sidewall surface The thickness of the first insulating barrier is thin, then channel bottom formed run through described first insulating barrier, protective layer and After the through hole of soldering pad layer, it is possible to remove part first insulating barrier of channel bottom, be simultaneously formed at chip Part first insulating barrier of layer second surface and trench sidewall surface can be retained, in order at subsequent technique Middle protection described chip layer surface.After part the first insulating barrier removed around described through hole, described Channel bottom declines from the stepped structure of trenched side-wall to through-hole side wall so that channel bottom is to through-hole side The linking trend of wall slows down, and therefore, the material being subsequently formed conductive layer easily enters inside through hole, thus Make conductive layer good at sidewall and the lower surface adhesive ability of through hole, and in making to be formed at through hole, groove Sidewall and the thickness of conductive layer of lower surface uniform.Therefore, the mechanical strength of the conductive layer formed Improve, stability improves.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from The specific embodiment of the present invention is described in detail.
First embodiment
Fig. 3 to Fig. 8 is the cross-section structure signal of the forming process of the encapsulating structure of first embodiment of the invention Figure.
Refer to Fig. 3, it is provided that chip layer 201, the first surface I of described chip layer 201 has protective layer 203, described protective layer 203 surface has soldering pad layer 202, described protective layer 203 and soldering pad layer 202 table Mask has substrate 200, the second surface II of described chip layer 201 to have some to expose protective layer 203 Groove 204, the second surface II of described chip layer 201 is relative with first surface I, described groove 204 Position corresponding with soldering pad layer 202.
Described chip layer 201 is the substrate being formed with semiconductor devices, and described substrate is silicon substrate, SiGe Substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or iii-v Compound substrate (such as gallium nitride substrate or gallium arsenide substrate etc.), described semiconductor devices includes CMOS Device, passive device, memory device, graphical sensory device etc..
The first surface I of described chip layer 201 is formed with protective layer 203, the material of described protective layer 203 For insulating materials, it the present embodiment is silica.Soldering pad layer 202, institute it is formed with in described protective layer 203 State soldering pad layer 202 can and chip layer 201 in semiconductor devices between realize being electrically connected with, and described Between soldering pad layer 202 and described chip layer 201, the part without being electrically connected with is carried out by protective layer 203 Isolation.
Described chip layer 201 has some device regions being arranged in array, for cutting between adjacent devices district District, the device region of described chip layer 201 is formed with described semiconductor devices；And described soldering pad layer 202 shape The cutting area surface of chip layer 201 described in Cheng Yu, and described soldering pad layer prolongs to the device region of chip layer 201 Stretch, to realize realizing between soldering pad layer 202 and semiconductor devices being electrically connected with.
Described substrate 200 is used for carrying chip layer 201, in order to be packaged described chip layer 201.Institute State substrate 200 and include naked silicon chip, substrate of glass, resin base or ceramic bases, described substrate 200 Size can be identical with chip layer 201.In the present embodiment, the first surface I of described chip layer 201 Being formed with sensor devices, the most described substrate 200 is substrate of glass, in order to make sensor devices 207 to connect Receive light.Described substrate 200 surface has tack coat, and the material of described tack coat includes resin material Deng the sticking material of tool, described chip 201 is integrated by described tack coat pressing with substrate 200.
After described chip layer 201 and substrate 200 pressing is fixing, in the of described chip layer 201 Two surface II perform etching, and expose protective layer 203 to be formed at the second surface II of described chip layer 201 Groove 204, the position of described groove 204 is corresponding to the position of described soldering pad layer 202, the most described groove The protective layer 203 of the bottom of 204 is positioned at soldering pad layer 202 surface；And described groove 204 is positioned at chip layer The cutting area of 201, the most described groove 204 is for splitting the adjacent devices district of chip layer 201 to constitute solely Vertical chip.In the present embodiment, the sidewall of described groove 204 tilts relative to substrate 200 surface, and institute State the size being smaller in size than groove 204 top bottom groove 204.It is subsequently formed in described groove 204 The conductive layer of sidewall surfaces and chip layer 201 second surface II is capable of soldering pad layer 202 and is subsequently formed Electrical connection between the soldered ball of chip layer 201 second surface.
In the present embodiment, the first surface I of chip layer 201 is formed with sensor devices 207, in order to make State sensor devices 207 in encapsulation process from ectocine, need in described chip layer 201 and substrate Form cavity 206 between 200, and described sensor devices 207 is arranged in described cavity 206, with reality The now protection to described sensor devices 207.
Concrete, some discrete cover layers 205, and described cover layer is formed on described substrate 200 surface The position of 205 is corresponding with soldering pad layer 202, it is possible to make some soldering pad layers 202 lay respectively at some cover layers 205 surfaces；And between adjacent cover layer 205, constitute cavity 206, and the position of described cavity 206 and core The position of the sensor devices 207 of lamella 201 is corresponding, by chip layer 201 being carried out with substrate 200 Pressing, it is possible to described sensor devices 207 is arranged in described cavity 206.
In one embodiment, the material of described cover layer 205 is photosensitive resin, owing to photosensitive resin has Viscosity, it is possible to for anchoring base 200 and chip layer 201.By being exposed showing to described photosensitive resin Shadow is i.e. capable of graphically, to form some discrete cover layers 205.
In another embodiment, described cover layer 205 is a part for substrate 200, by substrate 200 Carry out photoetching and etching technics is formed.
Refer to Fig. 4, at the second surface II of described chip layer 201 and the sidewall of groove 204 and the end Surface, portion forms the first insulating barrier 208, is positioned at part the first insulating barrier 208 bottom described groove 204 The thickness of part the first insulating barrier 208 that thickness, ratio are positioned at chip layer 201 second surface II is thin.
The material of described first insulating barrier 208 is inorganic thin film material or high-molecular organic material；Described nothing Machine thin-film material is one or more combinations in silica, silicon nitride, silicon oxynitride and metal oxide； Described high-molecular organic material be polyimide resin, benzocyclobutene, Parylene, naphthalene polymer, Fluorocarbon or acrylate.
The formation process of described first insulating barrier 208 is coating process or depositing operation.In the present embodiment, Described coating process is spraying coating process, spin coating proceeding, typography.Described depositing operation is physical vapor Depositing operation, chemical vapor deposition method.
Being formed after the first insulating barrier 208, described first insulating barrier 208 is positioned at the of chip layer 201 The part of two surface II and the segment thickness ratio being positioned at bottom groove 204 are more than or equal to 2:1.It is subsequently used for The etching technics directionality of part the first insulating barrier 208 around removal through hole is poor, i.e. for not Tongfang To being respectively provided with etch rate, due to the first insulating barrier 208 thickness relatively chip layer 201 bottom groove 204 First insulating barrier 208 thickness of second surface II is thin, therefore, it is possible to make to be positioned at bottom groove 204 First one insulating barrier 208 is removed, and can retain second surface II and the groove 204 of chip layer 201 simultaneously The first insulating barrier 208 of sidewall surfaces, make remaining first insulating barrier 208 can be right in subsequent technique Chip layer 201 surface is protected.
In the present embodiment, spraying coating process is used to form described first insulating barrier 208, due to described coating work Artistic skill enough make the material of formation the first insulating barrier 208 be preferentially covered in chip layer 201 second surface II, And groove 204 sidewall surfaces tilted, therefore, it is possible to make the first insulating barrier 208 bottom groove 204 Thinner thickness.In the present embodiment, it is positioned at part first insulating barrier 208 of the second surface II of chip layer 201 Thickness be 20 microns, it is 10 micro-for being positioned at the thickness of part the first insulating barrier 208 bottom groove 204 Rice, i.e. thickness ratio is for 2:1.
In other embodiments, part first insulating barrier 208 of the second surface II of chip layer 201 it is positioned at The thickness ratio of thickness and part the first insulating barrier 208 being positioned at bottom groove 204 more than 2:1.
Refer to Fig. 5, formed bottom described groove 204 and run through described first insulating barrier 208, protective layer 203 and the through hole 209 of soldering pad layer 202, the sidewall of described through hole 209 hangs down relative to soldering pad layer 202 surface Directly.
Described through hole 209 runs through described first insulating barrier 208, protective layer 203 and soldering pad layer 202, thus The sidewall making described through hole 209 exposes soldering pad layer 202, follow-up is formed after conductive layer in described through hole, Described conductive layer can be made for the soldered ball electrically connecting soldering pad layer 202 be subsequently formed.In the present embodiment, Described through hole 209 uses laser boring technique to be formed, and described laser manual labour skill is also removed described in part Cover layer 205, to ensure that the through hole 209 formed can be completely through soldering pad layer 202；Described laser is beaten Hole technological operation is simple, and for the position of through hole 209 and be sized to accurately control, trepanning velocity is fast, Be conducive to improving process efficiency.In other embodiments, additionally it is possible to use photoetching process and each to different The dry etch process of property forms described through hole 209.
The sidewall of the through hole 209 owing to being formed is vertical, when follow-up needs relative to chip layer 201 surface When forming conductive layer in groove 204 and through hole 209, it is not easy to enter for forming the material of conductive layer In described through hole 209 and be attached to the sidewall surfaces of described through hole 209, then easily cause and be subsequently formed Uneven in the conductive layer thickness of through hole 209 sidewall surfaces, even rupture, cause formed to lead Electric layer bad mechanical strength, less stable.Therefore, in order to improve the conductive layer quality being formed in through hole, Follow-up needs removes the first insulating barrier around partial through holes 209, with increase groove 204 lower surface with Angle between through hole 209 sidewall, in making the material of conductive layer easily enter through hole 209 and be attached to lead to Hole 209 sidewall surfaces.
Refer to Fig. 6, use plasma dry degumming process to remove the part first around described through hole 209 Insulating barrier 208(is as shown in Figure 5), form the first insulating barrier 208a and expose bottom groove 204 Partial protection layer 203.
In the present embodiment, the technique of part the first insulating barrier 208 around described removal through hole 209 is Plasma dry degumming process, the gas of described plasma dry degumming process includes oxygen.
The directionality of described plasma dry degumming process is more weak, it is possible to be certainly perpendicular to being parallel to chip layer The all directions on 201 surfaces are respectively provided with etch rate, and therefore, described degumming process can be from described groove Described first insulating barrier 208 is performed etching by the sidewall surfaces of 204 lower surface and described through hole 209, The first insulating barrier 208 being positioned at around described through hole 209 can be etched by multiple directions, from And make the first insulating barrier 208 around through hole 209 first be removed.And, described plasma dry goes Adhesive process has selectivity, and the etch rate for the first insulating barrier 208 is very fast, and to protective layer 203 Etch rate slower so that during described plasma dry degumming process, protective layer 203 energy Enough retained.Therefore, it is possible to after removing part the first insulating barrier 208, and expose through hole 209 weeks Protective layer 203 surface enclosed.
Owing to the first insulating barrier 208 around through hole 209 is removed to expose protective layer 203 surface, And bottom described groove 204, part the first insulating barrier 208 away from described through hole 209 is the most retained, Therefore, bottom described groove 204, from groove 204 sidewall to the through hole 209 stepped structure of sidewall Decline so that bottom groove 204, the linking trend to through hole 209 sidewall slows down；It is being subsequently formed conduction During Ceng, be conducive to the material making conductive layer to enter in through hole 209, and be fully covered in described logical The sidewall surfaces in hole 209, thus enhance mechanical strength and the stability of formed conductive layer, and then Improve the electrical connection properties between soldering pad layer 202 and the soldered ball being subsequently formed.
It should be noted that the thickness of the first insulating barrier 208 owing to being positioned at chip layer 201 second surface II Spend thicker than being positioned at the first insulating barrier 208 thickness bottom groove 204, therefore, removing photoresist described in process After technique, the first insulating barrier 208a of chip layer 201 second surface II and groove 204 sidewall surfaces is still Can be retained, to protect described chip layer 201 in subsequent technique.
Refer to Fig. 7, after described plasma dry degumming process, at described first insulating barrier 208a Surface, the lower surface of groove 204 and the sidewall of through hole 209 and lower surface form conductive layer 210； Remove partial electroconductive layer 210 by photoetching and etching technics, make described conductive layer 210 realize graphically, with Form circuit.
The material of described conductive layer 210 is aluminium, titanium, copper, CTB alloy or titanium-aluminium alloy.Described conduction Layer 210 be formed by depositing operation, electroplating technology；Wherein, described depositing operation is physical vapor Depositing operation or chemical vapor deposition method.The conductive layer 210 formed by the first insulating barrier 208a with The sidewall of groove 204 and the second surface II electric isolution of chip layer 201.
After described depositing operation or electroplating technology, use photoetching process on described conductive layer 210 surface Forming photoresist layer, described photoresist layer defines the figure of circuit；With described photoresist layer as mask, Etch described conductive layer 210, make described conductive layer 210 form circuit.Electricity is formed at described conductive layer 210 After road, remove described photoresist layer.
In the present embodiment, described etching technics is dry plasma etch technique, the conductive layer 210 after etching For electrically connecting soldering pad layer 202 and described soldered ball, as the semiconductor devices in chip layer 201 to outside Lead-in wire.
In the present embodiment, owing to eliminating part the first insulating barrier 208 around through hole 209, and expose Go out the partial protection layer 203 around through hole so that in the bottom of groove 204, from groove 204 sidewall to logical The hole 209 stepped structure of sidewall declines, to the transition of through hole 209 sidewall bottom the most described groove 204 Gently, the material of described conductive layer 210 easily enters in through hole 209, and is fully covered in described through hole The sidewall of 209 and lower surface, so that being positioned at the sidewall of through hole 209 and the conductive layer 210 of lower surface Thickness is uniform, and the mechanical strength of the most described conductive layer 210 improves the electrical connection between soldering pad layer 202 Stable performance.
Refer to Fig. 8, after described conductive layer 210 forms circuit, formed on described conductive layer 210 surface Second insulating barrier 211；Opening is formed at the second insulating barrier 211 being positioned at chip layer 201 second surface II (not shown), described opening exposes partial electroconductive layer 210 surface；Conductive layer 210 in described opening Surface forms soldered ball 212.
Described second insulating barrier 211, as welding resisting layer, is used for protecting described conductive layer 210, and makes conductive layer 210 electrically insulate with external circuit.The material of described second insulating barrier 211 is epoxy resin.Described second exhausted The formation process of edge layer 211 is spraying coating process or spin coating proceeding.
After described spraying coating process or spin coating proceeding, by photoetching process at described second insulating barrier 211 Interior formation opening, described opening exposes the conductive layer 210 of chip layer 201 second surface II, makes described Soldered ball 212 is formed at the second surface II of described chip layer 201, and described soldered ball 212 can pass through institute The pad stating conductive layer and be formed at chip layer 201 first surface electrically connects.
In the present embodiment, the formation process of described soldered ball 212, for using silk-screen printing technique, uses silk screen Typography is printing solder in the opening of described second insulating barrier 211, thus the conductive layer in opening 211 surfaces form soldered ball 212；Wherein, described solder can be tin cream.Described silk-screen printing technique it After, described soldered ball 212 is refluxed, to form pedestal.After forming soldered ball 212, right Described chip packing-body cuts.
In the forming method of the present embodiment, there is in chip layer the protective layer exposing soldering pad layer surface Groove, and be formed at part first insulating barrier of described channel bottom thickness, than be positioned at chip surface or The thickness of part first insulating barrier of trench sidewall surface is thin, is then formed at channel bottom and runs through described the After the through hole of one insulating barrier, protective layer and soldering pad layer, it is possible to the part first removing channel bottom insulate Layer, part the first insulating barrier being simultaneously formed at chip layer second surface and trench sidewall surface can be protected Stay, in order in subsequent technique, protect described chip layer surface.In the part removed around described through hole the After one insulating barrier, at described channel bottom, decline from the stepped structure of trenched side-wall to through-hole side wall, Channel bottom is slowed down to the linking trend of through-hole side wall, and therefore, the material being subsequently formed conductive layer is easy In entering inside through hole, so that conductive layer is good at sidewall and the lower surface adhesive ability of through hole, and Make to be formed in through hole, the thickness of the conductive layer of the sidewall of groove and lower surface uniform.Therefore, institute's shape The mechanical strength of the conductive layer become improves, stability improves.
Accordingly, the first embodiment of the present invention also provides for a kind of encapsulating structure, please continue to refer to Fig. 8, bag Including: chip layer 201, the first surface I of described chip layer 201 has protective layer 203, described protective layer 203 surfaces have soldering pad layer 202, described protective layer 203 and soldering pad layer 202 surface and have substrate 200, The second surface II of described chip layer 201 has some grooves 204 exposing protective layer 203, described The second surface II of chip layer 201 is relative with first surface I, the position of described groove 204 and soldering pad layer 202 is corresponding；It is positioned at the second surface II of described chip layer 201 and the sidewall of groove 204 and bottom The first insulating barrier 208a on surface, the second surface II of described chip layer 201 is relative with first surface I； Being positioned at the through hole 209 bottom described groove 204, described through hole 209 runs through described protective layer 203 and weld pad Layer 202, the sidewall of described through hole 209 is vertical relative to soldering pad layer 202 surface, and is positioned at described through hole Part the first insulating barrier 208a around 209 exposes bottom part of trench 204；It is positioned at described first exhausted Edge layer 208a surface, the lower surface of groove 204 and the sidewall of through hole 209 and the conduction of lower surface Layer 210.
In the present embodiment, the partial protection layer 203 being positioned at around described through hole 209 is exposed, and away from Protective layer 203 surface of described through hole 209 has the first insulating barrier 208 and covers.Due at described groove Bottom 204, decline from groove 204 sidewall to the through hole 209 stepped structure of sidewall, described groove 204 Bottom is mild to the surface transition of through hole 209 sidewall, makes described conductive layer 210 thickness uniformly and can Fully it is covered in the sidewall surfaces of described through hole 209, the mechanical strength of the most described conductive layer 210 improves, And the electrical connection properties between soldering pad layer 202 is stable, and then improves soldering pad layer 202 and be subsequently formed Electrical connection properties between soldered ball.
Secondly, described conductive layer 210 is patterned conductive layer, is used for electrically connecting soldering pad layer and described weldering Ball 212, as the semiconductor devices in chip layer 201 to outside lead-in wire.
Additionally, described conductive layer 210 surface has the second insulating barrier 211；Described chip layer 201 second table Having opening (not shown) in second insulating barrier 211 of face II, described opening exposes partial electroconductive layer 210 Surface；It is positioned at the soldered ball 212 on conductive layer 210 surface of described opening.
In the encapsulating structure of the present embodiment, there is in chip layer the groove exposing soldering pad layer sealer, Described channel bottom has and runs through described first insulating barrier, protective layer and the through hole of soldering pad layer, is positioned at described Part the first insulating layer exposing around through hole goes out bottom part of trench, and described channel bottom is from trenched side-wall Decline to the stepped structure of through-hole side wall so that the linking trend of channel bottom to through-hole side wall slows down, Therefore conductive layer is good at sidewall and the lower surface adhesive ability of through hole, thickness is uniform.Therefore, lead described in The mechanical strength of electric layer improves, stability improves.
Second embodiment
Fig. 9 is the encapsulating structure of second embodiment of the invention cross-sectional view in forming process.
On the basis of first embodiment Fig. 5, please continue to refer to Fig. 9, using plasma etching technics goes Except part the first insulating barrier 208(around described through hole 209 as shown in Figure 5) and protective layer 203(is such as Shown in Fig. 5), form the first insulating barrier 208b and protective layer 203b, and expose bottom groove 204 Part of solder pads layer 202, makes the thickness of described first insulating barrier 208b and protective layer 203b the closer to through hole 209 is the thinnest, and is positioned at the surface relative to soldering pad layer 202, the protective layer 203b surface bottom groove 204 Tilt.
Part the first insulating barrier 208 and the technique of protective layer 203 around described removal through hole 209 are Plasma etching technique, the parameter of described plasma etch process includes: etching gas includes CF4、 C4F8, wherein, CF4Volume ratio in etching gas is 25%～40%.
Wherein, top crown is for controlling the generation of plasma, and bottom crown is for controlling the side of plasma To, by top crown and the regulation of bottom crown power, the power making top crown is higher, it is possible to ensure to fill The plasma density of foot, and the power of bottom crown is relatively low, makes isoionic directionality more weak, it is thus possible to The directionality enough making described plasma etch process is poor, and the most described plasma etch process can be It is parallel to soldering pad layer 202 to all directions being parallel to soldering pad layer 202, to the first insulating barrier 208 He Protective layer 203 performs etching, and makes part the first insulating barrier 208 around through hole and protective layer 203 with this It is removed, and exposes part of solder pads layer 202 surface around through hole 209.
Described plasma etch process is respectively provided with etch rate to the first insulating barrier 208 and protective layer 203, Therefore the first insulating barrier 208 bottom groove 204 and protective layer 203 all can be performed etching.And, The directionality of described plasma etch process is poor, it is possible to simultaneously to bottom groove 204 and through hole First insulating barrier 208 of 209 sidewalls and protective layer 203 perform etching so that first bottom groove 204 Insulating barrier 208 and protective layer 203 start gradually to groove 204 sidewall direction quilt from the sidewall of through hole 209 Remove, thus expose part of solder pads layer 202 surface around through hole 209；When follow-up at described groove 204 and through hole 209 in form conductive layer after, described conductive layer can simultaneously with groove 204 bottom and through hole The soldering pad layer 202 that 209 sidewalls expose contacts so that the electrical connection between conductive layer and soldering pad layer 202 Area increases, then the electrical connection properties between conductive layer and soldering pad layer 202 improves.
And after described plasma etch process can make etching, described protective layer 203 surface relative to Soldering pad layer 202 surface tilts, and the thickness of described protective layer 203 is the thinnest the closer to through hole 209；Rear During continuous formation conductive layer, easily enter in through hole 209 for forming the material of described conductive layer, And can fully be covered in the sidewall surfaces of described through hole 209, make to be formed at bottom groove 204 and through hole The conductive layer thickness of 209 sidewall surfaces is uniform, thus enhances the mechanical strength of formed conductive layer with steady Qualitative, make the electrical connection properties between soldering pad layer 202 and conductive layer.
Additionally, by the composition regulating described etching gas, it is possible to described plasma etch process Selectivity is adjusted, and i.e. can improve the etch rate bottom for groove 204, and reduce for core Lamella 201 second surface II and the etch rate of groove 204 sidewall such that it is able to removing groove 204 Bottom the first insulating barrier 208b and protective layer 203 while, retain chip layer 201 second surface II and First insulating barrier 208b of groove 204 sidewall surfaces and protective layer 203.
In the present embodiment, the etching gas of described plasma etch process includes CF4, described CF4 Volume ratio in etching gas is 25%～35%, it is possible to make to be more than the etch rate bottom groove 204 To chip layer 201 second surface II and the etch rate of groove 204 sidewall such that it is able to removing groove While first insulating barrier 208 of bottom and protective layer 203, retain this groove 204 sidewall surfaces and core The first insulating barrier 208b of lamella 201 second surface II.
After part the first insulating barrier 208 removed around described through hole 209 and protective layer 209, in institute State the first insulating barrier 208b surface, the lower surface of groove 204 and the sidewall of through hole 209 and bottom table Face forms conductive layer (not shown).The material of described conductive layer and formation process with described in first embodiment Identical, do not repeat at this.
In the present embodiment, due to 209 quilts after the first insulating barrier 208 around through hole 209 and protective layer Remove, and expose bottom groove 204 and the part of solder pads layer 202 of through hole 209 sidewall, therefore formed Conductive layer and described soldering pad layer 202 between electrical-contact area increase, make described conductive layer and soldering pad layer Electrical connection properties between 202 improves.And, protective layer 203 surface bottom groove 204 is relative to weldering Bed course 202 surface tilts, and the thickness of described protective layer 203 is the thinnest the closer to through hole 209 so that shape Bottom groove 204 described in Cheng Yu and through hole 209 sidewall surfaces conductive layer covering power improve, thickness equal Even, then the conductive layer mechanical strength formed strengthens, stability improves.
Etching is positioned at the partial electroconductive layer of chip layer 201 second surface II, makes described conductive layer realize figure Change；After etched portions conductive layer, form the second insulating barrier (not shown) at described conductive layer surface； Be positioned at chip layer 201 second surface II second insulating barrier formed opening (not shown), described in open Mouth exposes partial electroconductive layer surface；Conductive layer surface in described opening forms soldered ball (not shown).
The technique of described patterned conductive layer, the technique of the second insulating barrier that formed, shape in the second insulating barrier Become opening technique and formed soldered ball technique identical with described in first embodiment, refer to Fig. 8 and Related description, does not repeats at this.
In the present embodiment, after part the first insulating barrier removed around through hole, remove around through hole Partial protection layer, and expose the part around the part of solder pads layer of channel bottom, and described removal through hole The technique of the first insulating barrier and protective layer is plasma etch process.Described plasma etch process energy Enough the first insulating barrier and protective layer are performed etching simultaneously, therefore can expose after plasma process Go out the soldering pad layer surface around through hole, increase the contact between the conductive layer being subsequently formed and soldering pad layer with this Area, thus strengthen the electrical connection properties between conductive layer and soldering pad layer.And, described plasma is carved Etching technique has directionality, it is possible to is being perpendicular to chip layer surface and is being parallel to the side on chip layer surface simultaneously Perform etching to described first insulating barrier and protective layer, i.e. can be perpendicular to trench bottom surfaces simultaneously With the direction on through-hole side wall surface, described first insulating barrier and protective layer are performed etching, so that through hole is all Part the first insulating barrier enclosed and protective layer are removed, and the thinnest the closer to the thickness of the protective layer of through hole, And the surface being positioned at the protective layer of channel bottom tilts relative to the surface of soldering pad layer, it is possible to increase follow-up shape The mechanical strength of the conductive layer become and stability.
Accordingly, the second embodiment of the present invention also provides for a kind of encapsulating structure, please continue to refer to Fig. 9, this The encapsulating structure inventing the second embodiment is compared to first embodiment, difference: be positioned at described through hole 209 Part the first insulating barrier 208b around and protective layer 203b exposes the part of solder pads bottom groove 204 Layer 202, the thickness of described protective layer 203b is the thinnest the closer to through hole 209, and is positioned at bottom groove 204 Protective layer 203b surface relative to soldering pad layer 202 surface tilt.
Compared to first embodiment, in the present embodiment, it is positioned at bottom groove 204 and through hole 209 sidewall table The conductive layer in face increases with the electrical-contact area of soldering pad layer 202, and the mechanical strength of conductive layer strengthens, stablizes Property improve.
3rd embodiment
Figure 10 is the cross-sectional view in the forming process of the encapsulating structure of third embodiment of the invention.
On the basis of first embodiment Fig. 6, please continue to refer to Figure 10, using described plasma dry Degumming process removes part the first insulating barrier 208(around through hole 209 as shown in Figure 5) after, use Plasma etch process removes part the first insulating barrier 208 around described through hole 209 and protective layer 209, form the first insulating barrier 208c and protective layer 209c, and expose the part weldering bottom groove 204 Bed course 202, the thickness making described protective layer 209c is the thinnest the closer to through hole 209, and is positioned at groove 204 The protective layer 209c surface of bottom tilts relative to the surface of soldering pad layer 202.
In the present embodiment, remove around described through hole 209 initially with plasma dry degumming process Part the first insulating barrier 208(is as shown in Figure 5), and expose the partial protection layer bottom groove 204 203.Plasma dry degumming process is used to remove part the first insulating barrier 208 around through hole 209, institute State the identical with described in first embodiment of plasma dry degumming process, do not repeat at this.
After described plasma dry degumming process, then continue to remove through hole with plasma etch process Part the first insulating barrier 208 around 209 and protective layer 203, described plasma etch process and second Described in embodiment identical, do not repeat at this.
In the present embodiment, gradually go to groove 204 sidewall from through hole 209 sidewall initially with degumming process Except the first insulating barrier 208 bottom groove 204, it is possible to expose the partial protection layer around through hole 209 203；Afterwards, then with plasma etch process simultaneously to the first insulating barrier 208 and protective layer 203 with logical Hole 209 sidewall performs etching to the direction of groove 204 sidewall, it is possible to expose the weldering around through hole 209 Bed course 202 surface, and the first insulating barrier 208c can be made to expose the part protection near through hole 209 Layer 203c.After described plasma dry degumming process and plasma etch process, the first insulating barrier 208c exposes partial protection layer 203c near through hole 209, and protective layer 203c exposes through hole 209 Part of solder pads layer 202 around, therefore, groove 204 sidewall to through hole 209 sidewall, described first insulation The surface transition of layer 208c, protective layer 203c and soldering pad layer 202 is the mildest, makes the conduction being subsequently formed Layer is easier to be covered in bottom groove 204 and the sidewall surfaces of through hole 209, further enhancing conductive layer Mechanical strength and stability；Simultaneously as the soldering pad layer 202 around through hole 209 is exposed, institute State conductive layer can contact with the soldering pad layer 202 of through hole 209 sidewall with bottom groove 204, institute simultaneously The electrical-contact area stating conductive layer and soldering pad layer 202 increases.
After plasma etch process, at described first insulating barrier 208c surface, the end of groove 204 Surface, portion and the sidewall of through hole 209 and lower surface form conductive layer.The material of described conductive layer and shape Become technique identical with described in first embodiment, do not repeat at this.
After forming conductive layer, etching is positioned at the partial electroconductive layer of chip layer 201 second surface II, makes Described conductive layer realizes graphical；After etched portions conductive layer, form the at described conductive layer surface Two insulating barriers；Be positioned at chip layer 201 second surface II second insulating barrier formed opening, described in open Mouth exposes partial electroconductive layer surface；Conductive layer surface in described opening forms soldered ball.
The technique of described patterned conductive layer, the technique of the second insulating barrier that formed, shape in the second insulating barrier Become opening technique and formed soldered ball technique identical with described in first embodiment, refer to Fig. 8 and Related description, does not repeats at this.
In the present embodiment, after part the first insulating barrier removed around through hole, remove around through hole Partial protection layer, and expose the part of solder pads layer of channel bottom；Wherein, around described removal through hole The technique of part the first insulating barrier is plasma dry degumming process, and the technique removing protective layer is plasma Body etching technics.Described degumming process has selectivity for the first insulating barrier and protective layer, is removing the Reservation protection layer while one insulating barrier；And, described degumming process has directionality, it is possible to simultaneously with The direction being perpendicular to trench bottom surfaces and through-hole side wall surface etches the first insulating barrier, makes described through hole week Part the first insulating barrier enclosed is removed.After described degumming process, same with plasma etch process Time described first insulating barrier and protective layer are performed etching, to remove the protective layer around through hole and first exhausted Edge layer also exposes the part of solder pads layer around the through hole of channel bottom, it is possible to strengthen the conduction being subsequently formed Electrical-contact area between layer and soldering pad layer.And, described plasma etch process also has directionality, Simultaneously can etch the first insulating barrier and guarantor being perpendicular to the direction on trench bottom surfaces and through-hole side wall surface Sheath, so that the surface of the protective layer after Ke Shi tilts relative to soldering pad layer surface.After etching first Insulating layer exposing goes out partial protection layer surface, and described protective layer exposes part of solder pads layer surface so that First insulating barrier, protective layer and the soldering pad layer of channel bottom are the mildest to the transition of through hole so that follow-up The material forming conductive layer is easier to enter inside through hole, then the mechanical strength of the conductive layer formed is with steady Qualitative further raising.
Accordingly, the third embodiment of the present invention also provides for a kind of encapsulating structure, please continue to refer to Figure 10, The encapsulating structure of third embodiment of the invention is compared to the second embodiment, difference: be positioned at described through hole Part the first insulating barrier 208c and protective layer 203c around 209 expose the part weldering bottom groove 204 Bed course 202.Wherein, bottom described groove 204, described first insulating barrier 208c also exposes close Partial protection layer 203c of through hole 209, and protective layer 203c exposes the part of solder pads around through hole 209 Layer 202.
Compared to first embodiment and the second embodiment, in the present embodiment, from the sidewall of described groove 204 To described through hole 209 sidewall, described first insulating barrier 208c, protective layer 203c and the table of soldering pad layer 202 Face transition is the mildest, is conducive to enhancing the mechanical strength of conductive layer and stability.Simultaneously as it is logical Soldering pad layer 202 around hole 209 is exposed, described conductive layer and the electrical-contact area of soldering pad layer 202 Increase.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention The scope of protecting should be as the criterion with claim limited range.

Claims (16)

1. the forming method of an encapsulating structure, it is characterised in that including:
Thering is provided chip layer, the first surface of described chip layer has protective layer, and described protective layer has Soldering pad layer, described protective layer and soldering pad layer surface have substrate, if the second surface of described chip layer has The dry groove exposing protective layer, the second surface of described chip layer is relative with first surface, described groove Position corresponding with soldering pad layer；
The first insulating barrier is formed at the second surface of described chip layer and the sidewall of groove and lower surface, It is positioned at the thickness of part first insulating barrier of described channel bottom, than the part being positioned at chip layer second surface The thickness of the first insulating barrier is thin；
Formed at described channel bottom and run through described first insulating barrier, protective layer and the through hole of soldering pad layer, institute The sidewall stating through hole is vertical relative to soldering pad layer surface；
Remove part the first insulating barrier around described through hole, and expose bottom part of trench, from groove Sidewall declines to the stepped structure of through-hole side wall；
After removing part the first insulating barrier around described through hole, described first surface of insulating layer, The lower surface of groove and the sidewall of through hole and lower surface form conductive layer.
2. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that removing around through hole After part the first insulating barrier, described first insulating layer exposing goes out the partial protection layer of channel bottom.
3. the forming method of encapsulating structure as claimed in claim 2, it is characterised in that around described removal through hole The technique of part the first insulating barrier be plasma dry degumming process, described plasma dry removes photoresist work The gas of skill includes oxygen.
4. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include: remove through hole Part the first insulating barrier around and protective layer, and expose the part of solder pads layer of channel bottom.
5. the forming method of encapsulating structure as claimed in claim 4, it is characterised in that around described removal through hole Part the first insulating barrier and the technique of protective layer be plasma etch process, described plasma is carved The parameter of etching technique includes: etching gas includes CF4、C4F8, wherein, CF4In etching gas Volume ratio is 25%～40%.
6. the forming method of encapsulating structure as claimed in claim 4, it is characterised in that use plasma dry to go Adhesive process removes part the first insulating barrier around through hole, the gas of described plasma dry degumming process Including oxygen；After described plasma dry degumming process, using plasma etching technics is removed Part the first insulating barrier around through hole and protective layer, the parameter of described plasma etch process includes: Etching gas includes CF4、C4F8, wherein, CF4Volume ratio in etching gas is 25%～40%.
7. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that forming the first insulating barrier Afterwards, before removing part the first insulating barrier around through hole, it is positioned at the portion of the second surface of chip layer The thickness of point the first insulating barrier be positioned at channel bottom part the first insulating barrier thickness than more than or etc. In 2:1.
8. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that described first insulating barrier Formation process is coating process or depositing operation.
9. the forming method of encapsulating structure as claimed in claim 8, it is characterised in that described coating process is spray It is coated with technique, spin coating proceeding, typography；Described depositing operation is physical gas-phase deposition, chemistry Gas-phase deposition.
10. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that described first insulating barrier Material is inorganic thin film material or high-molecular organic material.
The forming method of 11. encapsulating structures as claimed in claim 10, it is characterised in that described inorganic thin film material For one or more combinations in silica, silicon nitride, silicon oxynitride and metal oxide；Described have Machine macromolecular material is polyimide resin, benzocyclobutene, Parylene, naphthalene polymer, carbon fluorine Compound or acrylate.
The forming method of 12. encapsulating structures as claimed in claim 1, it is characterised in that the sidewall phase of described groove Substrate surface is tilted, and the size being smaller in size than groove top of described channel bottom.
The forming method of 13. encapsulating structures as claimed in claim 1, it is characterised in that also include: pass through photoetching Remove partial electroconductive layer with etching technics, make described conductive layer realize graphical, to form circuit；? After described conductive layer forms circuit, form the second insulating barrier at described conductive layer surface；It is being positioned at core Forming opening in second insulating barrier of lamella second surface, described opening exposes partial electroconductive layer surface； Conductive layer surface in described opening forms soldered ball.
14. 1 kinds use the encapsulating structure formed such as claim 1 to 13 any one method, it is characterised in that Including:
Chip layer, the first surface of described chip layer has protective layer, and described protective layer has weld pad Layer, described protective layer and soldering pad layer surface have substrate, the second surface of described chip layer have some cruelly Exposing the groove of protective layer, the second surface of described chip layer is relative with first surface, the position of described groove Put corresponding with soldering pad layer；
It is positioned at the first insulating barrier of the second surface of described chip layer and the sidewall of groove and lower surface；
Being positioned at the through hole of described channel bottom, described through hole runs through described protective layer and soldering pad layer, described logical The sidewall in hole is vertical relative to soldering pad layer surface, and part the first insulating barrier being positioned at around described through hole is sudden and violent Exposed portion channel bottom, declines from the stepped structure of trenched side-wall to through-hole side wall；
It is positioned at described first surface of insulating layer, the lower surface of groove and the sidewall of through hole and lower surface Conductive layer.
15. encapsulating structures as claimed in claim 14, it is characterised in that the part first being positioned at around described through hole Insulating layer exposing goes out the partial protection layer of channel bottom.
16. encapsulating structures as claimed in claim 14, it is characterised in that the part first being positioned at around described through hole Insulating barrier and protective layer expose the part of solder pads layer of channel bottom.
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