CN103531484B - The manufacture method of chip bearing board structure - Google Patents
The manufacture method of chip bearing board structure Download PDFInfo
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- CN103531484B CN103531484B CN201210233005.XA CN201210233005A CN103531484B CN 103531484 B CN103531484 B CN 103531484B CN 201210233005 A CN201210233005 A CN 201210233005A CN 103531484 B CN103531484 B CN 103531484B
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- layer
- projection cube
- cube structure
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- metallic substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides the manufacture method of a kind of chip bearing board structure, comprise metallic base structure making step, photoresist design layer forming step, etching step, photoresist design layer removal step, insulation material layer pressing step, brushing step, line layer making step and welding resisting layer making step, metallic base structure making step is to produce two metallic substrate layer to have the multilayer structure of a barrier layer, etch depth can be efficiently controlled in an etching step, make each position and the shape of projection cube structure and the degree of depth that are formed each time the most identical, and can be widely used in the processing procedure of volume production, and effectively solve prior art because the degree of depth differs, the skew caused, position cannot the constant and problem of delamination.
Description
Technical field
The present invention relates to the manufacture method of a kind of chip bearing board structure, mainly by substrate
Increase barrier layer, to maintain the making homeostasis of projection (Paddle) structure, and make chip bearing substrate
It is not susceptible to delamination problems.
Background technology
With reference to Figure 1A and Figure 1B, respectively prior art chip bearing board structure the first example and
The generalized section of the second example.As shown in Figure 1A, prior art chip bearing board structure 100
The projection cube structure (paddle) 15 that comprise a metallic substrate layer 10, is formed in metallic substrate layer 10,
Insulation material layer 30, line layer 40 and welding resisting layer 60, insulation material layer 30 inserts projection cube structure
Space between 15 and metallic substrate layer 10, but a plane of projection cube structure 15 is from insulation material layer
30 expose, and form a coplanar flat.Line layer 40 is formed on this coplanar flat, with projection
Structure 15 connects, and welding resisting layer 60 is formed on insulation material layer 30 and line layer 40, bag
Cover part line layer 40, in order to avoid when forming weld pad (not shown), causing short circuit.
As shown in Figure 1B, prior art chip bearing board structure 150, in the structure of the first example
As change, it is in insulation material layer 30, imbed carbon fibre initial rinse fabric 50 and formed thereon
Conductive layer 55, circuit laminar is formed at projection cube structure 15, insulation material layer 30 and conductive layer 55
A coplanar flat on, be connected with this projection cube structure 15 and this conductive layer 50.
Existing chip bearing plate structure disadvantageously, projection cube structure 15 is typically with etching mode,
Directly producing from line layer 40, owing to being all same material, the degree of depth of etching is difficult to, in volume production
Time the shape of projection cube structure 15, the degree of depth of vacancy be difficult to remain certain, this makes follow-up
Insulation material layer 30 is difficult to maintain flat surfaces, carbon fibre initial rinse fabric 50 and formed thereon
The position of conductive layer 55 is also difficult to constant, and this chip bearing substrate when by external force is susceptible to take off
The phenomenon of layer so that yield is difficult to promote.
Summary of the invention
Present invention is primarily targeted at the manufacture method that a kind of chip bearing board structure is provided, should
Method comprises: a metallic base structure making step, comprises a plating steps and a pair pressure step,
This plating steps is to plate a barrier layer in a metallic substrate layer, and this is by another gold to pressure step
Belong to basal layer pressing on this barrier layer, and form a multilayer structure；One photoresist design layer forms step
Suddenly, this metallic substrate layer on upper strata produces a photoresist design layer；One etching step, with an erosion
Quarter, liquid was etched, and the part that this metallic substrate layer on upper strata is not covered by this photoresist design layer was gone
Remove, and this metallic substrate layer on upper strata be formed as a projection cube structure, wherein this etching solution not with this
Barrier layer reacts；One photoresist design layer removal step, removes this photoresist design layer；One is exhausted
Edge material lamination closes step, is pressure bonded on this projection cube structure by an insulation material layer, and this insulation material
The bed of material fills up the space between this barrier layer and this projection cube structure；One brushing step, by this insulation material
The upper surface planarizing of the bed of material, reveals the upper surface of this projection cube structure simultaneously, and makes this
Projection cube structure forms a coplanar flat with the upper surface of this insulation material layer；One line layer making step,
This coplanar flat is formed in the way of image transfer a line layer, this line layer covering part
This insulation material layer and the upper surface of this projection cube structure, and be connected with this projection cube structure；And one prevent
Layer making step, is to form a welding resisting layer in this coplanar flat, and this welding resisting layer is by this insulation material
The part that the bed of material and this projection cube structure are not covered by this line layer covers, and is covered by the line layer of part
Lid.
The feature of the present invention essentially consists in the degree of depth utilizing barrier layer to control etching, and can be accurate
Control wet etching so that each projection cube structure of same substrate, and every time shape the most in the same manner
Shape and the degree of depth of the projection cube structure become are the most identical, and can be widely used in the processing procedure of volume production,
And effectively solving prior art because the degree of depth differs, the skew, the position that are caused cannot be constant
And the problem of delamination.
Accompanying drawing explanation
Figure 1A is the generalized section of prior art chip bearing board structure the first example；
Figure 1B is the generalized section of prior art chip bearing board structure the first example；
Fig. 2 is the flow chart of the manufacture method of chip bearing board structure of the present invention；And
Fig. 3 A to Fig. 3 I, Fig. 4 A and Fig. 4 B and Fig. 5 A to Fig. 5 C are chip bearings of the present invention
The progressively generalized section of the manufacture method of board structure.
Primary clustering symbol description
10 metallic substrate layer
11 metallic substrate layer
13 projection cube structures
15 projection cube structures
20 barrier layers
22 barrier layers
30 insulation material layers
40 line layers
50 carbon fibre initial rinse fabrics
55 conductive layers
60 welding resisting layers
100 chip bearing board structures
150 chip bearing board structures
200 photoresist design layers
The manufacture method of S1 chip bearing board structure
S10, S11, S13, S20, S30, S35, S40, S50, S60, S70, S80 step
Detailed description of the invention
Hereinafter coordinate graphic and element numbers that embodiments of the present invention are done more detailed description, with
Make those skilled in the art can implement according to this after studying this specification carefully.
With reference to Fig. 2, Fig. 3 A to Fig. 3 I, Fig. 4 A and Fig. 4 B, and Fig. 5 A to Fig. 5 C, respectively
For the flow chart of the manufacture method of chip bearing board structure of the present invention, and chip bearing of the present invention
The progressively generalized section of the manufacture method of board structure.As in figure 2 it is shown, chip bearing of the present invention
Manufacture method S1 of board structure comprises a metallic base structure making step S10, photoresist design layer
Forming step S20, etching step S30, photoresist design layer removal step S40, insulant are laminated
Close step S50, brushing step S60, line layer making step S70 and welding resisting layer making step
S80。
Plating is comprised referring concurrently to Fig. 2, Fig. 3 A and Fig. 3 B, metallic base structure making step S10
Layer step S11 and to pressure step S13.Plating steps S11 is to plate in a metallic substrate layer 11
A upper barrier layer 20, to pressure step S13 be by another metallic substrate layer 11 on this barrier layer 20
Pressing, and form a multilayer structure.As shown in Figure 3 C, photoresist design layer forming step S20 be
The metallic substrate layer 11 on upper strata produces photoresist design layer 200, as shown in Figure 3 D, etching step
S30 is to be etched with etching solution, by the metallic substrate layer 11 on upper strata not by photoresist design layer 200
The part covered is removed, and due to the characteristic of wet etching, can the metallic substrate layer 11 on upper strata be formed as
Projection cube structure (paddle) 13, owing to etching solution does not reacts with this barrier layer 20, therefore, erosion
Carve step S30 and arrive this barrier layer 20 just termination, the most as shown in FIGURE 3 E, photoresist design layer
Removal step S40 is to be removed by the photoresist design layer 200 on projection cube structure 13.
As illustrated in Figure 3 F, insulation material layer pressing step S50 is to be pressure bonded to by insulation material layer 30
On projection cube structure 13, and make insulation material layer 30 fill up barrier layer 20 and projection cube structure 13 it
Between space.Brushing step S60 is by smooth for the upper surface of insulation material layer 30 as shown in Figure 3 G
Change, the upper surface of projection cube structure 13 is revealed simultaneously, and make projection cube structure 13 exhausted with this
The upper surface of edge material layer 30 forms a coplanar flat.As shown in figure 3h, line layer making step
S70 is to form a line layer 40 in this coplanar flat in the way of image transfer, this line layer 40
The insulation material layer 30 of covering part and projection cube structure 13, and be connected with this projection cube structure 13.As
Shown in Fig. 3 I, welding resisting layer making step S80, is to form a welding resisting layer 60 in this coplanar flat,
The part that insulation material layer 30 and projection cube structure 13 are not covered by this welding resisting layer 60 by line layer 40,
And the line layer 40 of part covers, during to wait the formation of weld pad (not shown) after preventing, produce short circuit
Problem.
Further, as shown in Fig. 3 and Fig. 4 A, one can be carried out after etching step S30
Two etching step S35, the second etching step S35 be with one second etching solution by barrier layer 20 not by
The part that projection cube structure 13 covers is removed, and forms barrier layer 22 as shown in Figure 4 A, the second erosion
Carve liquid and do not produce reaction, therefore, the second etching step with metallic substrate layer 11 with projection cube structure 13
S35 just terminates in the metallic substrate layer 11 arriving lower floor.And form structure as shown in Figure 4 A.
Then, photoresist design layer removal step S40, insulation material layer pressing step are the most sequentially carried out
Rapid S50, brushing step S60, line layer making step S70 and welding resisting layer making step S80,
And form structure as shown in Figure 4 B, wherein insulation material layer 30 fills up barrier layer 22 and Metal Substrate
Space between bottom 11 and projection cube structure 13.
Further, as shown in Figure 5A, in insulation material layer pressing step S50, will insulate
When material lamination conjunction step S50 is that insulation material layer 30 is pressure bonded to projection cube structure 13, press simultaneously
It is bonded to a few carbon fibre initial rinse fabric 50, and is arranged at least one conduction on carbon fibre initial rinse fabric
Layer 55, after pressing, insulation material layer 30 fills up the space between barrier layer 20 and projection cube structure 13,
So that at least one carbon fibre initial rinse fabric 50, and it is arranged on carbon fibre initial rinse fabric at least
One conductive layer 55 edge is embedded among insulation material layer 30.
Then, brushing step S60 is sequentially carried out so that this at least one conductive layer 55 and this projection
Structure 13 exposes, and makes this insulation material layer 30, this at least one conductive layer 55 and be somebody's turn to do
Surface co-planar on projection cube structure 13, and form a coplanar flat.Then carry out line layer and make step
Rapid S70, and form structure as shown in Figure 5 B, wherein line layer 40 be formed at projection cube structure 13,
On this at least one conductive layer 55 and this insulation material layer 30 in a coplanar flat of surface co-planar,
The projection cube structure 13 of covering part, this at least one conductive layer 55 and this insulation material layer 30.?
After carry out welding resisting layer making step, make this welding resisting layer 60 covering insulating material layer 30, projection cube structure
13 and the part that do not covered by line layer 40 of conductive layer 55, and the line layer 40 of part.More
Further, if this mode is through the second etching step S35, then structure as shown in Figure 5 C is formed.
Wherein metallic substrate layer 11, projection cube structure 13, line layer 40 and the material of conductive layer 55
For copper, aluminum at least one, and the material of barrier layer 20 be stannum, nickel, titanium, palladium at least
One of them, comprise Jie's metallic compound that the material with metallic substrate layer 11 is formed further, and
The scope of barrier layer thickness is 3 μm～10 μm.Insulation material layer 30 be BT resin, glass fibre,
ABF (Ajinomoto Build-Up Film) glued membrane etc..
The feature of the present invention essentially consists in the degree of depth utilizing barrier layer to control etching, and can be accurate
Control wet etching so that each position male block structure and the projection held with the same terms shape each time
Shape and the degree of depth of structure are the most identical, and can be widely used in the processing procedure of volume production, and have
Effect solves prior art because the degree of depth differs, and the skew, the position that are caused cannot constant and delaminations
Problem.
As described above is only in order to explain presently preferred embodiments of the present invention, is not intended to according to this to this
Any pro forma restriction is done in invention, therefore, all have is made under identical spirit about
Any modification of invention or change, all must be included in the category that the invention is intended to protection.
Claims (5)
1. the manufacture method of a chip bearing board structure, it is characterised in that comprise:
One metallic base structure making step, comprises a plating steps and a pair pressure step, and this coating walks
Suddenly being to plate a barrier layer in a metallic substrate layer, this is at this by another metallic substrate layer to pressure step
Pressing on barrier layer, and form a multilayer structure；
One photoresist design layer forming step, this metallic substrate layer on upper strata produces a photoresist design layer；
One etching step, is etched with an etching solution, by this metallic substrate layer on upper strata not by this photoresistance
The part that patterned layer is covered is removed, and this metallic substrate layer on upper strata is formed as a projection cube structure, wherein
This etching solution does not reacts with this barrier layer；
One photoresist design layer removal step, removes this photoresist design layer；
One insulation material layer pressing step, is pressure bonded to an insulation material layer on this projection cube structure, and this is exhausted
Edge material layer fills up the space between this barrier layer and this projection cube structure；
One brushing step, planarizes the upper surface of this insulation material layer, simultaneously upper by this projection cube structure
Surface open out, and makes this projection cube structure form a coplanar flat with the upper surface of this insulation material layer；
One line layer making step, forms a line layer in this coplanar flat in the way of image transfer,
This insulation material layer of this line layer covering part and the upper surface of this projection cube structure, and with this projection cube structure
Connect；And
One welding resisting layer making step, is to form a welding resisting layer in this coplanar flat, and this welding resisting layer is exhausted by this
The part that edge material layer and this projection cube structure are not covered by this line layer covers, and is covered by the line layer of part
Lid,
This insulation material layer pressing step when this insulant of pressing, a further simultaneously pressing at least carbon
Fiber prepreg and be arranged at least one conductive layer on this at least one carbon fibre initial rinse fabric so that should
At least one carbon fibre initial rinse fabric, and this at least one conductive layer edge be embedded among insulation material layer, then exist
This brushing step make the upper surface of this at least one conductive layer and this projection cube structure expose so that this is altogether
Facial plane is the flat of surface co-planar on this insulation material layer, this at least one conductive layer and this projection cube structure
Face, and when making line layer making step, this projection cube structure of this line layer shape covering part, this at least
One conductive layer and this insulation material layer, and when this welding resisting layer making step, make this welding resisting layer cover absolutely
The part that edge material layer, projection cube structure and conductive layer are not covered by this line layer, and cover the line of part
Road floor.
2. the method for claim 1, it is characterised in that further after this etching step, enter
Row one second etching step, barrier layer is not tied by this projection by this second etching step with one second etching solution
The part that structure covers is removed, and wherein this second etching solution does not produces with this metallic substrate layer and this projection cube structure
Reaction, then when this insulation material layer pressing step is carried out, this insulation material layer fill up this barrier layer with
Space between this metallic substrate layer and this projection cube structure.
3. the method for claim 1, it is characterised in that further after this etching step, enter
Row one second etching step, barrier layer is not tied by this projection by this second etching step with one second etching solution
The part that structure covers is removed, and wherein this second etching solution does not produces with this metallic substrate layer and this projection cube structure
Reaction, then when this insulation material layer pressing step is carried out, this insulation material layer fill up this barrier layer with
Space between this metallic substrate layer and this projection cube structure.
4. the method for claim 1, it is characterised in that this metallic substrate layer, this projection cube structure,
The material of this line layer be copper, aluminum at least one, and the material of this barrier layer be stannum, nickel, titanium,
At least one of palladium, and Jie's metallic compound of the material formation with this metallic substrate layer, and should
The scope of barrier layer thickness is 3 μm～10 μm, and this insulation material layer is BT resin, glass fibre, ABF
At least one of glued membrane.
5. the method for claim 1, it is characterised in that the material of this at least one conductive layer be copper,
At least one of aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210233005.XA CN103531484B (en) | 2012-07-06 | 2012-07-06 | The manufacture method of chip bearing board structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210233005.XA CN103531484B (en) | 2012-07-06 | 2012-07-06 | The manufacture method of chip bearing board structure |
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| Publication Number | Publication Date |
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| CN103531484A CN103531484A (en) | 2014-01-22 |
| CN103531484B true CN103531484B (en) | 2016-12-21 |
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| CN201210233005.XA Active CN103531484B (en) | 2012-07-06 | 2012-07-06 | The manufacture method of chip bearing board structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5492235A (en) * | 1995-12-18 | 1996-02-20 | Intel Corporation | Process for single mask C4 solder bump fabrication |
| CN1445824A (en) * | 2003-04-17 | 2003-10-01 | 威盛电子股份有限公司 | Method for preparing lugs and glue stuff layer |
| TW200942762A (en) * | 2008-04-11 | 2009-10-16 | Unimicron Technology Corp | Circuit board and process for fabricating the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW512467B (en) * | 1999-10-12 | 2002-12-01 | North Kk | Wiring circuit substrate and manufacturing method therefor |
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2012
- 2012-07-06 CN CN201210233005.XA patent/CN103531484B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5492235A (en) * | 1995-12-18 | 1996-02-20 | Intel Corporation | Process for single mask C4 solder bump fabrication |
| CN1445824A (en) * | 2003-04-17 | 2003-10-01 | 威盛电子股份有限公司 | Method for preparing lugs and glue stuff layer |
| TW200942762A (en) * | 2008-04-11 | 2009-10-16 | Unimicron Technology Corp | Circuit board and process for fabricating the same |
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| Publication number | Publication date |
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| CN103531484A (en) | 2014-01-22 |
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