CN103472115A - Ion-sensitive field effect transistor and preparation method thereof - Google Patents
Ion-sensitive field effect transistor and preparation method thereof Download PDFInfo
- Publication number
- CN103472115A CN103472115A CN2013103596892A CN201310359689A CN103472115A CN 103472115 A CN103472115 A CN 103472115A CN 2013103596892 A CN2013103596892 A CN 2013103596892A CN 201310359689 A CN201310359689 A CN 201310359689A CN 103472115 A CN103472115 A CN 103472115A
- Authority
- CN
- China
- Prior art keywords
- ion
- semiconductor substrate
- field effect
- effect transistor
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a transistor, and discloses an ion-sensitive field effect transistor. The ion-sensitive field effect transistor comprises a semiconductor substrate 202, and a source 101 and a drain 102 which are located on the semiconductor substrate 202 and formed by doping; a groove structure etched to the interior of the semiconductor substrate 202 is arranged between the source 101 and the drain 102, an ion-sensitive membrane 103 is formed on the surface of the groove structure, and thus a gate insulating layer is formed. Because the groove structure is etched to the interior of the semiconductor substrate 202 with a certain depth, the structure can play a role of shielding and protecting measured hydrogen ions in a solution 201, so that interference of an electromagnetic field in the surrounding environment can be avoided when the concentration of the hydrogen ions is measured, and thus the accuracy and the repeatability of measurement results are effectively improved.
Description
Technical field
The present invention relates to field effect transistor, particularly a kind of ion-sensitive field effect transistor and preparation method thereof.
Background technology
In prior art, the structure of ion-sensitive field effect transistor ISFET device is very similar to the metal oxide semiconductor field effect tube MOSFET that removes metal gate, as depicted in figs. 1 and 2, its gate insulation layer is the planar section between source electrode 101 and drain electrode 102, one deck sensitive layer 103 covered on gate insulation layer directly contacts with detected solution 201, due to hydrionic existence in detected solution 201, induce this special Nernst response current potential of small energy to the hydrogen ion sensitivity on ion sensitive membrane 103 and detected solution 201 interfaces:
This Nernstian potential makes gate electrode insulation surface and source electrode form certain electric potential difference, after this electric potential difference increases to transistorized threshold voltage, raceway groove will be opened, at source electrode 101 with drain 102 and add a fixed voltage, will form electric current therebetween, the Nernst current potential that in solution, hydrogen ion induces more at most is larger, raceway groove is opened more abundant, and source-drain current is larger.Measurement by source-leakage current just can be detected pH or the activity in detected solution 201 solution, measures the pH value.
Be easy to be subject to the interference of peripheral electromagnetic field while measuring due to the pH to existing in solution 201, and in prior art, the gate insulation layer due to the ISFET device is a plane domain, can not play to the hydrogen ion in detected solution 201 shielding action to peripheral electromagnetic field, and, this special response current potential of energy between ion sensitive membrane 103-detected solution 201 interfaces is very small, slightly has that deviation will make that measurement result is unstable, poor repeatability, fiduciary level be low.
In prior art, also there is very large defect in the formation of source electrode and drain electrode, current technique is adulterated to the position of corresponding source electrode and drain electrode on Semiconductor substrate 202, the space of gate insulation layer is left in centre, such mode can cause source electrode and the diffusion that drains and adulterate to channel region, affects the actual effective dimensions of raceway groove.And the groove structure in the present invention separates source electrode and drain region automatically, can accurately control like this size of channel region.
Summary of the invention
The object of the present invention is to provide a kind of ion-sensitive field effect transistor and preparation method thereof, when this transistor of application carries out the detection of pH value, make hydrogen ion in detected solution exempt from the interference of electromagnetic field in surrounding environment, make measurement result more accurate, repeatability is higher.
For solving the problems of the technologies described above, the invention provides a kind of ion-sensitive field effect transistor, comprise Semiconductor substrate, extend to the groove of described Semiconductor substrate inside, and be positioned at source electrode and the drain electrode formed by doping on this Semiconductor substrate;
Described groove is between described source electrode and described drain electrode, and the degree of depth of described groove is greater than the junction depth of described source electrode and drain electrode;
Described groove surfaces has ion sensitive membrane.
The present invention also provides a kind of preparation method of ion-sensitive field effect transistor, comprises following steps:
Semi-conductive substrate is provided;
Adulterated on described Semiconductor substrate, formed doped region;
Etch a groove on described doped region and described Semiconductor substrate, the described doped region of described groove both sides forms source electrode and drain electrode; Wherein, the degree of depth of described groove is greater than the junction depth of described source electrode and drain electrode;
Generate ion sensitive membrane in described groove surfaces.
Compared with prior art, in the present invention, ISFET structurally improves, there is groove between source electrode and drain electrode, this groove is etched into semiconductor inside, source electrode is separated with drain electrode, groove surfaces has ion sensitive membrane, apply ISFET of the present invention and carry out the pH value while detecting, detected solution is injected in groove, because the etching depth of this groove is darker, can form a relatively space of sealing for detected solution, so just can play to the hydrogen ion in detected solution the effect of shielding protection, make the interference of electromagnetic field exempt from surrounding environment when measuring pH in, and then make the accuracy of measurement result and repeatability all obtain effective raising.
Preferably, in the present invention, whole semiconductor substrate surface first defines doped region by photoetching process, and then adulterated, then form groove structure on corresponding position, doped region is split up into to source electrode and drain electrode, this technique can guarantee in the doping in the zone of whole source electrode and drain electrode all more even, avoid source electrode and drain electrode because the doping inequality causes defect, affect device performance; And this doping process after the groove forming process in, between source electrode and drain electrode and groove walls, not there will be because the uneven defect formed of doping yet.
Secondly, the ion sensitive membrane in above-mentioned ion-sensitive field effect transistor is the individual layer insulating medium layer, and the ion-sensitive membrane material is SiO
2, Si
3n
4, Al
2o
3or Ta
2o
5, these ion-sensitive membrane materials are more responsive and suction-operated is more intense to hydrogen ion, and adsorption concentration is higher, and sensitivity is good, so just makes measurement result more timely and effective.
Again, the ion sensitive membrane in above-mentioned ion-sensitive field effect transistor can be also at least two-layer insulating medium layer, and wherein, the material that the layer contacted with Semiconductor substrate adopts is silicon dioxide SiO
2, the material that the layer of most surface adopts is silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5in any one.Because SiO
2better with the associativity of Semiconductor substrate, and surface adopts material more responsive to hydrogen ion and that suction-operated is more intense, therefore, can adopt rhythmo structure, make the ion sensitive membrane can be better with the associativity of Semiconductor substrate, can there is stronger suction-operated to hydrogen ion again.
In addition, ion-sensitive field effect transistor in the present invention also comprises the source exit, leaks exit and substrate exit, for laying respectively at the Metal-silicides Contact district at above-mentioned source electrode, drain electrode and the Semiconductor substrate back side, so that source electrode, drain electrode and Semiconductor substrate are connected with external circuits.
As a further improvement on the present invention, sink to the bottom before being adulterated and also will on this Semiconductor substrate, generate a layer insulating SiO at semiconductor
2or by SiO
2and Si
3n
4the laminated insulation layer formed, this insulation course on Semiconductor substrate between source drain and detected solution well the isolation, prevent that detected solution from infiltrating source electrode and drain region, produce leakage current between solution and source drain, further guarantee the stability of ion-sensitive field effect transistor duty.
As a nearlyer step of the present invention, improve, the selection of the Semiconductor substrate in the present invention is also particularly important, if Semiconductor substrate is the P type, source electrode and drain electrode are just the N-type doping; If Semiconductor substrate is N-type, described source electrode and described drain electrode are the doping of P type.Preferred substrate is the P type in the present invention, and the scheme that source electrode and drain electrode are the N-type doping is because source electrode and drain electrode are done in the N-type doping that the mobility of electronics, much larger than the mobility in hole, is therefore majority carrier with electronics, much better than by current capacity; In addition, from control angle, say, N-type ISFET can open with positive voltage, is easy to use.
Source electrode in the present invention is located by channel grooves structure self-aligning effect with drain electrode, adopt this mode to control the precision of position between source electrode and drain electrode and raceway groove very accurate, and as long as just can realize the definition of source electrode, drain electrode and channel region through the even glue of a step, exposure, development and etch step.
In addition, the groove that extends to Semiconductor substrate inside in intermediate ion sensitive field effect transistor of the present invention is that the mode combined with dry etching by dry etching or wet etching forms, the advantage of the transfer litho pattern that utilizes that the dry etching anisotropic is good, etch rate is high and can high-fidelity, etch above-mentioned groove accurately and rapidly; The mode that wet etching is combined with dry etching can first first be removed some residuals of semiconductor substrate surface with wet etching, then etches the groove of Semiconductor substrate inside with dry etching, and etching effect is more remarkable.
Finally, the ion sensitive membrane related in the present invention is to form by thermal oxide, chemical vapor deposition or ald mode, and comparatively speaking the method for these film forming is more simple.
The accompanying drawing explanation
Fig. 1 is ISFET solid pH sensor principle of work schematic diagram in prior art;
Fig. 2 A is according to the ion-sensitive field effect transistor schematic diagram in first embodiment of the invention;
Fig. 2 B is the schematic diagram of additional contrast electrode while testing according to the ion-sensitive field effect transistor in first embodiment of the invention;
Fig. 3 A is according to the ion-sensitive field effect transistor preparation method process flow diagram in second embodiment of the invention;
Fig. 3 B～3K is according to the ion-sensitive field effect transistor preparation method schematic diagram in second embodiment of the invention;
Fig. 3 L be according in the ion-sensitive field effect transistor preparation method in second embodiment of the invention when test additional contrast electrode schematic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.Yet, persons of ordinary skill in the art may appreciate that in each embodiment of the present invention, in order to make the reader understand the application better, many ins and outs have been proposed.But, even without these ins and outs and the many variations based on following each embodiment and modification, also can realize each claim of the application technical scheme required for protection.
The first embodiment of the present invention relates to a kind of ion-sensitive field effect transistor, and as shown in Figure 2 A, scheming left figure is vertical view, the diagrammatic cross-section that right figure is a-a ＇ face in corresponding left figure.This ion-sensitive field effect transistor comprises Semiconductor substrate 202 and is positioned on this Semiconductor substrate 202 and forms doped region 203 by doping, source electrode 101 and drain electrode 102 all are positioned at doped region 203, source electrode 101 and a groove structure that drains between 102 and have to extend to Semiconductor substrate 202 inside, groove surfaces generates ion sensitive membrane 103, this groove structure and this ion sensitive membrane 103 have formed the gate insulation layer on the raceway groove jointly, also will be respectively at source electrode 101 after the formation gate insulation layer, the Metal-silicides Contact district is produced at drain electrode 102 and Semiconductor substrate 202 back sides, so that by source electrode 101, drain electrode 102 is connected with external circuits with Semiconductor substrate 202.
In the present embodiment, ISFET device detected solution 201 when measuring injects in groove, can produce small Nernst response current potential on ion sensitive membrane 103 and detected solution 201 interfaces, this Nernst current potential makes gate electrode insulation surface and source electrode 101 form certain electric potential difference, after increasing to transistor threshold voltage, this electric potential difference will open at raceway groove, at source electrode 101 with drain 102 after adding a fixed voltage and will form electric current therebetween, the Nernst current potential that in detected solution 201, hydrogen ion induces more is larger, raceway groove is opened more abundant, source-drain current is larger, because above-mentioned Nernst response current potential is very small, in external environment, a slight influence factor just may cause this potential measurement inaccurate, and the groove described in the present embodiment is darker, can form a relatively space of sealing for detected solution, so just can play to the hydrogen ion in detected solution 201 effect of shielding protection, make when measuring hydrogen ion exempt from surrounding environment in the interference of electromagnetic field, and then make the accuracy of measurement result and repeatability all obtain effective raising.
Formation technique and the prior art of described doped region 203 are different in the present embodiment, at first the predeterminable area on Semiconductor substrate 202 surfaces adulterates, and then form groove structure on corresponding position, source electrode 101 and drain electrode 102 are separated, this technique can guarantee at whole source electrode and drain region doping all more even, avoid source electrode 101 and drain electrode 102 because the doping inequality causes defect, affect device performance; And this doping process after the groove forming process in, source electrode 101 and drain 102 and groove walls between not there will be the defect formed because of the inequality of adulterating yet.In addition, the method realization that Semiconductor substrate is adulterated and can be adopted the existing comparative maturities such as Implantation, do not repeat them here.
Ion sensitive membrane 103 in the present embodiment is the individual layer insulating medium layer, and the ion-sensitive membrane material is SiO
2, Si
3n
4, Al
2o
3or Ta
2o
5, these ion-sensitive membrane materials are more responsive and suction-operated is more intense to hydrogen ion, and adsorption concentration is higher, and sensitivity is good, so just makes measurement result more timely and effective.This ion sensitive membrane 103 can be also at least two-layer insulating medium layer, and wherein, the material that the layer contacted with Semiconductor substrate 202 adopts is silicon dioxide SiO
2, because SiO
2better with the associativity of Semiconductor substrate 202, the material that the layer of most surface adopts is silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5in any one.The present embodiment intermediate ion sensitive membrane 103 can be made film to above-mentioned material by the mode of thermal oxide, chemical vapor deposition or ald, these modes are all relatively simple comparatively speaking, film-forming apparatus is required also not high, can reduce the preparation cost of whole device.
In addition, the ISFET device in the present invention also comprises insulation course 204, and this insulation course 204 covers the zone of not adulterated on Semiconductor substrate 202.This insulation course 204 can be silicon dioxide SiO
2, silicon nitride Si
3n
4or the rhythmo structure of their compositions.If insulation course 204 is silicon dioxide SiO
2, can adopt the combination of high-temperature oxydation technology, ethyl orthosilicate (TEOS) low-pressure chemical vapor phase deposition (LPCVD) technology or two kinds of technology to form.LPCVD SiO
2with high-temperature thermal oxidation SiO
2compare, film quality is more loose, but can make up to a certain extent the high-temperature oxydation technology, forms thicker SiO
2stress and defect and the too high drawback of technological temperature during layer, brought.Therefore, adopt the combination of LPCVD technology and high-temperature oxydation technology to use, can guarantee SiO
2the compactness of film and with the adhesive capacity of Semiconductor substrate 202, can improve again electrical property and the yield rate of device.
The selection of Semiconductor substrate 202 in the present invention is also particularly important, and described Semiconductor substrate 202 can be P type or N-type, if Semiconductor substrate 202 is P types, what by doping, form is exactly source electrode 101 and the drain electrode 102 of N-type; If Semiconductor substrate 202 is N-types, what by doping, form is exactly source electrode 101 and the drain electrode 102 of P type.In the present embodiment, with be P-type semiconductor substrate 202, form source electrode 101 and the drain electrode 102 of N-type by doping, because the mobility of electronics is much larger than the mobility in hole, therefore source electrode 101 and drain electrode 102 are done in the N-type doping that is majority carrier with electronics, much better than by current capacity; In addition, from control angle, say, N-type ISFET can open with positive voltage, uses more convenient.
When being measured, the ISFET device can insert a contrast electrode 205 201 li of detected solutions in addition in present embodiment, this contrast electrode 205 is an Ag/AgCl contrast electrode of filling 3.5M KCl solution, this contrast electrode 205 has the effect of stable detected solution electromotive force, thereby accuracy and the reliability of measurement result have further been improved, as shown in Fig. 2 B.
Second embodiment of the invention relates to a kind of preparation method of ion-sensitive field effect transistor, as Fig. 3 A is the preparation method's of the ion-sensitive field effect transistor that provides of present embodiment process flow diagram, the diagrammatic cross-section (right side) of a-a ＇ face in vertical view (left side) corresponding to each step and corresponding vertical view in the preparation method of the ion-sensitive field effect transistor that Fig. 3 B to Fig. 3 K provides for present embodiment.Below in conjunction with Fig. 3 A to Fig. 3 K, the preparation method of the ion-sensitive field effect transistor that present embodiment is provided is specifically described.
Step S1, provide Semiconductor substrate 202, and form insulation course 204 on substrate, as shown in Fig. 3 A～3C.
Above-mentioned Semiconductor substrate 202 can be P type or N-type, if Semiconductor substrate 202 is P types, what by doping, form is exactly source electrode 101 and the drain electrode 102 of N-type; If Semiconductor substrate 202 is N-types, what by doping, form is exactly source electrode 101 and the drain electrode 102 of P type.In the present embodiment, with be P-type semiconductor substrate 202, form source electrode 101 and the drain electrode 102 of N-type by doping, because the mobility of electronics is much larger than the mobility in hole, therefore source electrode 101 and drain electrode 102 are done in the N-type doping that is majority carrier with electronics, much better than by current capacity; In addition, from control angle, say, N-type ISFET can open with positive voltage, uses more convenient.
Wherein, can form a layer insulating or multilayer dielectric layer on Semiconductor substrate; Wherein, the material of insulation course is silicon dioxide SiO
2, silicon nitride Si
3n
4or the rhythmo structure of their compositions.Such as insulation course 204 wherein can be SiO
2, can forming by the combination of high-temperature oxydation technology, ethyl orthosilicate (TEOS) low-pressure chemical vapor phase deposition (LPCVD) technology or two kinds of technology, application TEOSLPCVD technology realizes SiO
2in the deposit of semiconductor substrate surface, made up to a certain extent the high-temperature oxydation technology and formed thicker SiO
2layer overlong time, technological temperature is too high and produce stress and the drawbacks such as defect.Adopt the reasonable utilization of TEOS LPCVD technology and high-temperature oxydation technology, both guaranteed SiO
2the compactness of film and with the adhesive capacity of Semiconductor substrate 202, improved again electrical property and the yield rate of device.
Step S2 is adulterated on Semiconductor substrate 202, forms doped region 203.
Specifically, on Semiconductor substrate 202, adulterated, formed in the step of doped region 203, also comprised following sub-step:
Step S201 applies one deck photoresist 301, as shown in Figure 3 C on insulation course 204.This layer photoetching glue 301 can adopt the mode of rotary coating to be coated on this insulation course 204.
Step S202, prepare flagpole pattern as shown in Figure 3 D by exposure, developing process, exposes and need the SiO removed
2.
Step S203, the mode of being combined with dry etching with dry etching or wet etching etches away the SiO cruelly leaked in step S202
2, expose strip Semiconductor substrate 202, as shown in Fig. 3 E.
Step S204, effects on surface is adulterated, and forms the doped region 203 of strip, and this doped region 203 lays the foundation with drain electrode 102 for forming afterwards source electrode 101, as shown in Fig. 3 F.If the Semiconductor substrate provided in step S1 202 is P types, in this step, the rear doped region 203 of doping is N-type; If the Semiconductor substrate provided in step S1 202 is N-types, after the doping, doped region 203 is the P type.In the present embodiment, with be P-type semiconductor substrate 202, form source electrode 101 and the drain electrode 102 of N-type by doping, because the mobility of electronics is much larger than the mobility in hole, therefore source electrode 101 and drain electrode 102 are done in the N-type doping that is majority carrier with electronics, much better than by current capacity; In addition, from control angle, say, N-type ISFET can open with positive voltage, uses more convenient.
Step S3 etches a groove on doped region 203 and Semiconductor substrate 202, forms source electrode 101 and drain electrode 102.
Etch a groove specifically on doped region 203 and Semiconductor substrate 202, also comprise following sub-step in the step S3 of formation source electrode 101 and drain electrode 102:
Step S301, remove photoresist 301, manifests the insulation course 204 of being protected by photoresist 301, as shown in Fig. 3 G.
Step S302, as shown in Fig. 3 H, again through once even glue, aligning exposure, the also etching of developing (are repeating step 201～step 203, just change a mask plate), obtain the groove that 4 (show 4 in schematic diagram, in fact have a lot of) etch into Semiconductor substrate 202 inside, the etching depth of this groove is greater than source electrode 101 or 102 the junction depth of draining, so far, source electrode 101 and drain electrode 102 form.
When measuring; detected solution 201 injects groove; groove just can play to the hydrogen ion in detected solution 201 effect of shielding protection; make when measuring hydrogen ion exempt from surrounding environment in the interference of electromagnetic field; and then making the accuracy of measurement result and repeatability all obtain effective raising, this point is also the most important inventive point of the present invention.
This groove is just got ready for gate insulation layer formation afterwards.Wherein source electrode is located by channel grooves structure self-aligning effect with drain electrode, adopt this mode to control the precision of position between source electrode and drain electrode and raceway groove very accurate, and as long as just can realize the definition of source electrode, drain electrode and channel region through the even glue of a step, exposure, development and etch step.
Groove structure is that the mode of being combined with dry etching with dry etching or wet etching is etched to Semiconductor substrate 202 inside, the advantage of the transfer litho pattern that utilizes that the dry etching anisotropic is good, etch rate is high and can high-fidelity, etch above-mentioned groove accurately and rapidly; The mode that wet etching is combined with dry etching can first first be removed some residuals on Semiconductor substrate 202 surfaces with wet etching, then etches the groove of Semiconductor substrate 202 inside with dry etching, and etching effect is more remarkable.Secondly the relative position between the self alignment effect point-device control source electrode of energy adopted in the present embodiment and drain electrode and groove, and as long as just can realize the location of this position through the even glue of a step, exposure, development and etch step.
Step S4, generate ion sensitive membrane in groove surfaces.Generate ion sensitive membrane 103 at doped region 203 and groove part, after removing photoresist as shown in Fig. 3 I.
Ion sensitive membrane 103 wherein can be the individual layer insulating medium layer, and the ion-sensitive membrane material is SiO
2, Si
3n
4, Al
2o
3or Ta
2o
5, these ion-sensitive membrane materials are more responsive and suction-operated is more intense to hydrogen ion, and adsorption concentration is higher, and sensitivity is good, so just makes measurement result more timely and effective.This ion sensitive membrane can be also at least two-layer insulating medium layer, and wherein, the material that the layer contacted with Semiconductor substrate 202 adopts is silicon dioxide SiO
2, because SiO
2better with the associativity of Semiconductor substrate 202, the material that the layer of most surface adopts is silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5in any one.The present embodiment intermediate ion sensitive membrane 103 can be made film to above-mentioned material by modes such as thermal oxide, chemical vapor deposition or alds, these modes are all relatively simple comparatively speaking, film-forming apparatus is required also not high, can reduce the preparation cost of whole device.
After above-mentioned four main steps complete, again through standard photolithography process respectively source electrode 101, drain 102 and Semiconductor substrate produce Metal-silicides Contact district 302 202 times, finally, plate the layer of metal nickel, form Metal-silicides Contact after annealing, after being convenient to, whole device and external circuit is connected.
When being measured, the ISFET device can insert a contrast electrode 205 201 li of detected solutions in addition in the present embodiment, as shown in Fig. 3 L.This contrast electrode 205 is an Ag/AgCl contrast electrode 205 of filling 3.5M KCl solution, and this contrast electrode 205 has the effect of stable detected solution 201 electromotive forces, thereby has further improved accuracy and the reliability of measurement result.
Be not difficult to find, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment and preparation process are still effective in the present embodiment, in order to reduce repetition, repeat no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first embodiment.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiments of the invention, and in actual applications, can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (14)
1. an ion-sensitive field effect transistor, is characterized in that, comprises: Semiconductor substrate extends to the groove of described Semiconductor substrate inside, and is positioned at source electrode and the drain electrode formed by doping on described Semiconductor substrate;
Described groove is between described source electrode and described drain electrode, and the degree of depth of described groove is greater than the junction depth of described source electrode and drain electrode;
Described groove surfaces has ion sensitive membrane.
2. a kind of ion-sensitive field effect transistor according to claim 1, is characterized in that, described source electrode and drain electrode are by first adulterating in predeterminable area on Semiconductor substrate, then the mode of described doped region being separated by described groove structure forms.
3. a kind of ion-sensitive field effect transistor according to claim 1, is characterized in that, described ion sensitive membrane is the individual layer insulating medium layer, the material of described ion sensitive membrane be following any one:
Silicon dioxide SiO
2, silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5.
4. a kind of ion-sensitive field effect transistor according to claim 1, is characterized in that, described ion sensitive membrane is to have an at least two-layer insulating medium layer,
The material that the layer contacted with described Semiconductor substrate adopts is silicon dioxide SiO
2, the material that the layer of most surface adopts be following any one:
Silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5.
5. a kind of ion-sensitive field effect transistor according to claim 1, it is characterized in that, also comprise: source exit, leakage exit and substrate exit, for laying respectively at the Metal-silicides Contact district at described source electrode, drain electrode and the described Semiconductor substrate back side.
6. a kind of ion-sensitive field effect transistor according to claim 1, is characterized in that, described Semiconductor substrate is the P type, and described source electrode and described drain electrode are the N-type doping; Perhaps,
Described Semiconductor substrate is N-type, and described source electrode and described drain electrode are the doping of P type.
7. the preparation method of an ion-sensitive field effect transistor, is characterized in that, comprises following steps:
Semi-conductive substrate is provided;
Adulterated on described Semiconductor substrate, formed doped region;
Etch a groove at described doped region, described groove is separated described doped region, and the described doped region of its both sides forms source electrode and drain electrode; Wherein, the degree of depth of described groove is greater than the junction depth of described source electrode and drain electrode;
Generate ion sensitive membrane in described groove surfaces.
8. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, is characterized in that, in described groove surfaces, generates in the step of ion sensitive membrane, generates one deck insulating medium layer as described ion sensitive membrane;
Wherein, the material of described ion sensitive membrane be following any one:
Silicon dioxide SiO
2, silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5.
9. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, is characterized in that, in described groove surfaces, generates in the step of ion sensitive membrane, generates at least two-layer insulating medium layer as described ion sensitive membrane;
Wherein, the material that the layer contacted with described Semiconductor substrate adopts is silicon dioxide SiO
2, the material that the layer of most surface adopts be following any one:
Silicon nitride Si
3n
4, aluminium oxide Al
2o
3or tantalum pentoxide Ta
2o
5.
10. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterized in that, in described groove surfaces, generate in the step of ion sensitive membrane, the method by thermal oxide, chemical vapor deposition or ald obtains described ion sensitive membrane.
11. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, is characterized in that, after described groove surfaces generates the step of ion sensitive membrane, also comprises following steps:
Form the Metal-silicides Contact district at described source electrode, drain electrode and the described Semiconductor substrate back side, respectively as the exit of described source electrode, drain electrode and described Semiconductor substrate.
12. the preparation method of a kind of ion-sensitive field effect transistor according to claim 7, it is characterized in that, etch the step of a groove on described doped region and described Semiconductor substrate in, adopt the mode that dry etching or wet method are combined with dry etching to form groove.
13. a kind of ion-sensitive field effect transistor according to claim 7, is characterized in that, before described step of being adulterated, also comprises following steps:
Form insulation course on described Semiconductor substrate; Wherein, described insulation course is silicon dioxide SiO
2, silicon nitride Si
3n
4or the rhythmo structure of both compositions.
14. want 7 described a kind of ion-sensitive field effect transistors according to right, it is characterized in that, in the step of being adulterated on described Semiconductor substrate, described Semiconductor substrate is the P type, carries out the N-type doping; Perhaps,
Described Semiconductor substrate is N-type, carries out the doping of P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310359689.2A CN103472115B (en) | 2013-08-16 | 2013-08-16 | Ion-sensitive field effect transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310359689.2A CN103472115B (en) | 2013-08-16 | 2013-08-16 | Ion-sensitive field effect transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103472115A true CN103472115A (en) | 2013-12-25 |
| CN103472115B CN103472115B (en) | 2018-02-27 |
Family
ID=49797043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310359689.2A Active CN103472115B (en) | 2013-08-16 | 2013-08-16 | Ion-sensitive field effect transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103472115B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103940884A (en) * | 2014-03-18 | 2014-07-23 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
| CN115436436A (en) * | 2022-11-03 | 2022-12-06 | 南京元感微电子有限公司 | FET gas sensor and processing method thereof |
| CN115501920A (en) * | 2022-09-16 | 2022-12-23 | 中国人民解放军陆军特色医学中心 | Preparation method of nucleic acid amplification detection micro-fluidic chip with enhanced sensitivity of organic electrochemical transistor |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5911873A (en) * | 1997-05-02 | 1999-06-15 | Rosemount Analytical Inc. | Apparatus and method for operating an ISFET at multiple drain currents and gate-source voltages allowing for diagnostics and control of isopotential points |
| CN1577888A (en) * | 2003-07-24 | 2005-02-09 | 三星电子株式会社 | Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same |
| US20070095663A1 (en) * | 2005-11-01 | 2007-05-03 | National Yunlin University Of Science And Technology | Preparation of a PH sensor, the prepared PH sensor, system comprising the same and measurement using the system |
| CN101189507A (en) * | 2005-05-30 | 2008-05-28 | 梅特勒-托利多公开股份有限公司 | Electrochemical sensor |
| US20080283910A1 (en) * | 2007-05-15 | 2008-11-20 | Qimonda Ag | Integrated circuit and method of forming an integrated circuit |
| US20090184357A1 (en) * | 2008-01-18 | 2009-07-23 | Qimonda Ag | Soi based integrated circuit and method for manufacturing |
| CN101764155A (en) * | 2009-11-18 | 2010-06-30 | 上海宏力半导体制造有限公司 | Grooved field-effect tube and preparation method thereof |
| US20130204107A1 (en) * | 2012-01-23 | 2013-08-08 | The Ohio State University | Devices and methods for the rapid and accurate detection of analytes |
-
2013
- 2013-08-16 CN CN201310359689.2A patent/CN103472115B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5911873A (en) * | 1997-05-02 | 1999-06-15 | Rosemount Analytical Inc. | Apparatus and method for operating an ISFET at multiple drain currents and gate-source voltages allowing for diagnostics and control of isopotential points |
| CN1577888A (en) * | 2003-07-24 | 2005-02-09 | 三星电子株式会社 | Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same |
| CN101189507A (en) * | 2005-05-30 | 2008-05-28 | 梅特勒-托利多公开股份有限公司 | Electrochemical sensor |
| US20070095663A1 (en) * | 2005-11-01 | 2007-05-03 | National Yunlin University Of Science And Technology | Preparation of a PH sensor, the prepared PH sensor, system comprising the same and measurement using the system |
| US20080283910A1 (en) * | 2007-05-15 | 2008-11-20 | Qimonda Ag | Integrated circuit and method of forming an integrated circuit |
| US20090184357A1 (en) * | 2008-01-18 | 2009-07-23 | Qimonda Ag | Soi based integrated circuit and method for manufacturing |
| CN101764155A (en) * | 2009-11-18 | 2010-06-30 | 上海宏力半导体制造有限公司 | Grooved field-effect tube and preparation method thereof |
| US20130204107A1 (en) * | 2012-01-23 | 2013-08-08 | The Ohio State University | Devices and methods for the rapid and accurate detection of analytes |
Non-Patent Citations (1)
| Title |
|---|
| XIWEI HUANG 等: "《A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis》", 《IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103940884A (en) * | 2014-03-18 | 2014-07-23 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
| CN103940884B (en) * | 2014-03-18 | 2017-04-12 | 复旦大学 | Ion sensitive field effect transistor and preparation method thereof |
| CN115501920A (en) * | 2022-09-16 | 2022-12-23 | 中国人民解放军陆军特色医学中心 | Preparation method of nucleic acid amplification detection micro-fluidic chip with enhanced sensitivity of organic electrochemical transistor |
| CN115501920B (en) * | 2022-09-16 | 2024-04-05 | 中国人民解放军陆军特色医学中心 | Preparation method of nucleic acid amplification detection micro-fluidic chip of organic electrochemical crystal Guan Zengmin |
| CN115436436A (en) * | 2022-11-03 | 2022-12-06 | 南京元感微电子有限公司 | FET gas sensor and processing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103472115B (en) | 2018-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bousse et al. | Operation of chemically sensitive field-effect sensors as a function of the insulator-electrolyte interface | |
| JP2008215974A (en) | Field effect transistor type ion sensor | |
| TWI422818B (en) | Hydrogen ion sensitive field effect transistor and manufacturing method thereof | |
| KR101217576B1 (en) | The bio sensor and the driving method thereof | |
| US8878258B2 (en) | Detector of biological or chemical material and corresponding array of detectors | |
| US6617190B2 (en) | A-WO3-gate ISFET devices and method of making the same | |
| US7211459B2 (en) | Fabrication method of an ion sensitive field effect transistor | |
| CN108847424B (en) | Thin film transistor, sensor, biological detection device and method | |
| Nguyen et al. | Organic field-effect transistor with extended indium tin oxide gate structure for selective pH sensing | |
| CN103472115A (en) | Ion-sensitive field effect transistor and preparation method thereof | |
| CN103940884A (en) | Ion sensitive field effect transistor and preparation method thereof | |
| Khanna | Fabrication of ISFET microsensor by diffusion-based Al gate NMOS process and determination of its pH sensitivity from transfer characteristics | |
| CN105353000B (en) | Semiconductor devices and its detection method | |
| CN107564890B (en) | A kind of strain gauge structure and preparation method thereof | |
| CN105301079B (en) | Semiconductor devices and its detection method for the detection of determinand ionic activity | |
| CN104280443B (en) | A kind of making of highly sensitive OTFT pH sensors and pH detections | |
| Hizawa et al. | Characteristics of highly sensitive pH sensors with charge accumulation operation | |
| Yusof et al. | pH sensing characteristics of silicon nitride thin film and silicon nitride-based ISFET sensor | |
| CN108732225B (en) | Ion sensitive field effect transistor and forming method thereof | |
| JP2011085557A (en) | Semiconductor sensor and method for manufacturing the same | |
| KR102098288B1 (en) | Method for measuring doping concentration of semiconductor material , and recording medium for computer program using the same | |
| JP2011133234A (en) | Sensor, and measuring method using the same | |
| US20210270769A1 (en) | Chemical sensor and detection apparatus | |
| Wipf et al. | Potassium sensing with membrane-coated silicon nanowire field-effect transistors | |
| Sinha et al. | Simulation, fabrication and characterization of Dual-Gate MOSFET test structures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |