CN103390568B - A kind of method monitoring MOS device threshold voltage drift - Google Patents
A kind of method monitoring MOS device threshold voltage drift Download PDFInfo
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- CN103390568B CN103390568B CN201210139336.7A CN201210139336A CN103390568B CN 103390568 B CN103390568 B CN 103390568B CN 201210139336 A CN201210139336 A CN 201210139336A CN 103390568 B CN103390568 B CN 103390568B
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Abstract
The invention provides a kind of method monitoring MOS device threshold voltage drift, belong to the technical field of measurement and test of semiconductor device.In the method, after prepared by gate dielectric layer, the Q of this silicon chip of on-line monitoring
totand/or D
itvalue, and pass through Q
totand/or D
itthe threshold voltage shift of the MOS device prepared by this silicon chip of value prediction; Wherein, Q
totrepresent all electric charges of described gate dielectric layer inside, D
itrepresent the interface state density between described gate dielectric layer and silicon substrate.This method for supervising is ageing good, is conducive to the impact reduced because threshold voltage shift produces product yield.
Description
Technical field
The invention belongs to the technical field of measurement and test of semiconductor device, relating to one can realize MOS(Metal-Oxide-Semiconductor effectively in advance, metal-oxide semiconductor (MOS)) threshold voltage shift of device carries out the method monitored.
Background technology
Along with the development of semiconductor technology, in technology generation, constantly promotes, and processing step more (the flow time is longer), the characteristic size of MOS device constantly reduces, and the thickness of gate dielectric layer also constantly reduces.According to the threshold voltage (V of MOS device
tH) Computing Principle, along with the progress in technology generation, the various factors in manufacture process is also obvious all the more on the impact of threshold voltage, will be reflected in the drift of threshold voltage like this.Therefore, be improve product yield, monitoring threshold voltage shift seems ever more important.Generally, if find threshold voltage shift, then need to make adjustment to avoid threshold drift in technique etc.
The CV(capacitance-voltage of MOS device) curved measurement is the important means of threshold voltage characterizing MOS device.From CV curve, the flat band voltage (V of mos capacitance can be reflected
fB), V
fBcan be with for semiconductor surface in MOS structure and even up (in flat rubber belting state) required additional voltage, according to the physical principle of threshold voltage, V
fBone of part that can be understood as threshold voltage, therefore, during flatband voltage shift, generation is substantially also drifted about by the threshold voltage of MOS device.
For the drift of monitoring MOS device threshold voltage, usually introduce WAT(WaferAcceptTest, wafer acceptance test in the manufacture process of MOS device) test process, by measuring the CV(capacitance-voltage of MOS device) curve, if find its flat band voltage (V
fB) there is drift, can reflect that threshold voltage also exists drift.In current semiconductor manufactory, the complicated process of preparation of MOS device, processing step is many, WAT test has been prepared into from completing gate dielectric layer, time interval long (reaching 1 month in general manufactory) and substantially completed the preparation technology of MOS device, and within this time interval, the preparation of many (such as up to ten thousand) gate dielectric layers may have been completed on makers' production line, if it is serious to test out threshold voltage shift, in interval probably all there is threshold voltage shift phenomenon in manufactured MOS device during this period of time, such serious waste production capacity also reduces yield greatly.Therefore, in existing this method for supervising, delayed to the monitoring of threshold voltage shift, can not meet the requirement of semiconductor manufacturing.
In view of this, a kind of method proposing monitoring MOS device threshold voltage drift is newly necessary.
Summary of the invention
The object of the invention is to, ahead of time the drift of monitoring MOS device threshold voltage.
For realizing above object or other objects, the invention provides with a kind of method monitoring MOS device threshold voltage drift, wherein, after prepared by gate dielectric layer, the Q of this silicon chip of on-line monitoring
totand/or D
itvalue, and pass through Q
totand/or D
itthe threshold voltage shift of the MOS device prepared by this silicon chip of value prediction;
Wherein, Q
totrepresent all electric charges of described gate dielectric layer inside, D
itrepresent the interface state density between described gate dielectric layer and silicon substrate.
According to the method for supervising of one embodiment of the invention, wherein, the method comprises the following steps:
The silicon substrate of silicon chip completes gate dielectric layer preparation;
This silicon chip is placed on tester table, and to the surface offset electric charge of this silicon chip;
The surface of described silicon substrate is penetrated in illumination;
Measure the V of this silicon chip
s, draw Q
bias-V
srelation curve;
According to Q
bias-V
srelation curve calculates Q
bias-SPV relation curve;
According to Q
bias-SPV relation curve calculates Q
tot;
According to Q
totand Q
bias-V
srelation curve calculates D
it;
Judge Q respectively
totand/or D
itwhether depart from its corresponding predetermined range value;
If be judged as "Yes", then the threshold voltage of stating the prepared MOS device formed of this silicon chip will drift about;
Wherein, Q
biasrepresent the surface offset electric charge of silicon chip, V
srepresent the surface voltage of silicon chip, SPV states the surface photovoltage of silicon chip.
Preferably, at calculating Q
tottime, Q
tot=-Q
bias︱ SPV=0.
Preferably, in described silicon chip, arrange mute, the Q of mute described in on-line monitoring
totand/or D
itvalue is to reflect the Q of described silicon chip
totand/or D
itvalue.
Technique effect of the present invention is, this method for supervising can be able to complete after prepared by gate dielectric layer, achieves online effective monitoring, improves the ageing of monitoring, is conducive to the impact reduced because threshold voltage shift produces product yield.
Accompanying drawing explanation
From following detailed description by reference to the accompanying drawings, will make above and other object of the present invention and advantage more completely clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the schematic flow sheet of the method for the monitoring MOS device threshold voltage drift provided according to one embodiment of the invention.
Embodiment
Introduce below be of the present invention multiple may some in embodiment, aim to provide basic understanding of the present invention, be not intended to confirm key of the present invention or conclusive key element or limit claimed scope.Easy understand, according to technical scheme of the present invention, do not changing under connotation of the present invention, one of ordinary skill in the art can propose other implementations that can mutually replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or the restriction be considered as technical solution of the present invention or restriction.
Analyze discovery by applicant, affect the flat band voltage (V of MOS device
fB) factor mainly comprise: Q
totand D
it; Wherein Q
totrepresent all electric charges of gate dielectric layer inside, comprise the movable electric charge in fixed charge, gate dielectric layer, ionization trap etc.; D
itrepresent the interface state density between gate dielectric layer and channeled substrate.And found through experiments, when there is drift in threshold voltage, V
fBalso drift is produced, correspondingly, Q
totand/or D
italso there is exception.
The schematic flow sheet of the method for the monitoring MOS device threshold voltage drift provided according to one embodiment of the invention is provided.In the method embodiment, applicant according to above discovery, by on-line measurement or monitoring Q
totand D
it, know whether the threshold voltage of MOS device in the chip that preparation is formed by this silicon chip can drift about in advance, instead of wait silicon chip running through in all MOS preparation process, just carry out WAT and test and monitor its threshold voltage situation.Therefore, the monitoring of threshold voltage can relative to preparation technology's flow process of MOS device ahead of time.Particularly, method embodiment illustrated in fig. 1 comprises following concrete steps.
First, step S110, the silicon substrate of silicon chip completes the preparation of gate dielectric layer.In this step, the silicon chip preparing MOS device is thereon needed to be generally multi-disc, it adopts same process step and process conditions, be typically by batch to carry out, in this embodiment, monitor in advance for the threshold voltage of the MOS device formed on the wherein silicon chip of a batch, in the silicon chip of this batch, can arrange for test Q
totand/or D
itmute (DummyWafer), substantially reflected the Q of this batch of silicon chip by the result of this mute built-in testing
totand/or D
it; Certainly, this mute can also be used as other tests etc.
Further, step S120, is placed in mute on tester table, and to mute surface offset charge Q
bias.In this embodiment, the board of test adopts QUANTOX tester table, and by this board to silicon chip upper offset electric charge, such as, adopt the mode biascharge that scanning is biased, the scope of its scanning can be such as-5E7C/cm
2to 5E7C/cm
2.In this step, namely start to measure after gate dielectric layer preparation terminates, achieve on-line measurement.
Further, step S130, strong illumination surface of silicon.In this step, make use of the photo-generated carrier effect of silicon chip.When high light is radiated at surface of silicon instantaneously, nonequilibrium Carrier Profile can be produced in silicon substrate inside, and then can surface potential be changed.In this embodiment, the intensity of irradiating light intensity is roughly luminaire and is biased in the light intensity sent in the scope of 0.5V to 3V.
Further, step S140, after strong illumination surface of silicon, measures mute surface voltage V
s, draw Q
bias-V
srelation curve.In this step, strong illumination is not carried out in measuring process; Measured surface voltage V
safter, those skilled in the art can obtain Q
bias-V
srelation curve.
Further, step S150, according to Q
bias-V
srelation curve calculates Q
bias-SPV relation curve, wherein SPV is surface photovoltage.In this step, at Q
bias-V
swhen relation curve provides, those skilled in the art, can calculate Q
bias-SPV relation curve.
Further, step S160, according to Q
bias-SPV relation curve calculates Q
tot.At Q
biasin-SPV relation curve, when SPV=0, the Q of its correspondence
biaswith the Q in gate dielectric layer
totequal and opposite in direction, the Q that SPV=0 place is corresponding
biasbe Q
totsize (i.e. Q
tot=-Q
bias︱ SPV=0).
Further, step S170, according to Q
totand Q
bias-V
srelation curve calculates D
it.In this embodiment, at Q
biason axle, 0 to-Q
totq corresponding in scope
bias-V
sin relation curve, calculate the slope of the extension of its curved section to calculate Q
it.
Further, step S180, judges Q
totand D
itwhether depart from predetermined range value.In this step, Q
totand D
itall respectively to there being a predetermined range value, when threshold voltage is normal (when also flat band voltage is normal), Q
totand D
itshould change in predetermined range value respectively.This predetermined range value can according to threshold voltage size, redundancy range of drift etc. because usually determining.If Q
totdepart from its predetermined range value, and/or D
itdepart from its predetermined range value, then show that the threshold voltage of the MOS device formed based on this gate dielectric layer will drift about, in its CV curve test generally can tested at its WAT, obtain corresponding checking.
Further, step S190, if be judged as "Yes", the threshold voltage of the MOS device of this batch of prepared chip formed of silicon substrate will drift about.In this step, by measuring mute, the threshold voltage situation of the MOS device of the chip that this batch of silicon chip preparation is formed can be reflected.When threshold voltage is by drift, can stop the preparation of MOS device, adjustment preparation technology parameter etc. realizes the normal of threshold voltage.Like this, before discovery threshold voltage produces drift, prevent the processed manufacture of too much silicon chip, be conducive to improving yield, reduce costs.
Meanwhile, step S210, if be judged as that "No" monitoring feedback threshold voltage will be normal; Proceed other processing steps prepared by MOS device.
So far, the monitoring of the threshold voltage shift to MOS device is achieved.Can be found by above method for supervising process, Q
totand D
itmeasurement can canbe used on line, such as, can prepare in 2 hours at gate dielectric layer and just can measure Q
totand D
it, for the threshold voltage of MOS device formed monitored in advance (instead of etc. MOS device be fully formed after monitor again), improve the ageing of monitoring, be conducive to the impact reduced because threshold voltage shift produces product yield.
It should be noted that, in the embodiment above, Q
totrepresent all electric charges of described gate dielectric layer inside, D
itrepresent the interface state density between described gate dielectric layer and silicon substrate, Q
biasrepresent the surface offset electric charge of silicon chip, V
srepresent the surface voltage of silicon chip, SPV states the surface photovoltage of silicon chip.
It should be noted that, applicant finds, at Q
totand D
itin one substantially correspondence can there is threshold voltage shift situation when departing from the predetermined range value of its correspondence, therefore, in other embodiments, also can only control measurement Q
totand D
itin one realize monitoring the threshold voltage of MOS device.
Above example mainly describes the method for monitoring MOS device threshold voltage drift of the present invention.Although be only described some of them embodiments of the present invention, those of ordinary skill in the art should understand, and the present invention can implement with other forms many not departing from its purport and scope.Therefore, the example shown and execution mode are regarded as illustrative and not restrictive, when do not depart from as appended each claim define the present invention spirit and scope, the present invention may contain various amendments and replacement.
Claims (3)
1. monitor a method for MOS device threshold voltage drift, it is characterized in that, after prepared by gate dielectric layer, the Q of on-line monitoring silicon chip
totand/or D
itvalue, and pass through Q
totand/or D
itthe threshold voltage shift of the MOS device prepared by this silicon chip of value prediction;
Wherein, Q
totrepresent all electric charges of described gate dielectric layer inside, D
itrepresent the interface state density between described gate dielectric layer and silicon substrate, wherein, the method comprises the following steps:
The silicon substrate of silicon chip completes gate dielectric layer preparation;
This silicon chip is placed on tester table, and to the surface offset electric charge of this silicon chip;
The surface of described silicon substrate is penetrated in illumination;
Measure the V of this silicon chip
s, draw Q
bias-V
srelation curve;
According to Q
bias-V
srelation curve calculates Q
bias-SPV relation curve;
According to Q
bias-SPV relation curve calculates Q
tot;
According to Q
totand Q
bias-V
srelation curve calculates D
it;
Judge Q respectively
totand/or D
itwhether depart from its corresponding predetermined range value;
If be judged as "Yes", then the threshold voltage of stating the prepared MOS device formed of this silicon chip will drift about;
Wherein, Q
biasrepresent the surface offset electric charge of silicon chip, V
srepresent the surface voltage of silicon chip, SPV states the surface photovoltage of silicon chip.
2. the method for claim 1, is characterized in that, at calculating Q
tottime, Q
tot=-Q
bias︱ SPV=0.
3. the method for claim 1, is characterized in that, arranges mute in described silicon chip, the Q of mute described in on-line monitoring
totand/or D
itvalue is to reflect the Q of described silicon chip
totand/or D
itvalue.
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Citations (2)
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| US6011404A (en) * | 1997-07-03 | 2000-01-04 | Lucent Technologies Inc. | System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor |
| CN101154608A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid medium layer and estimating its electrical parameter |
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| JP2003347378A (en) * | 2002-05-23 | 2003-12-05 | Toyota Central Res & Dev Lab Inc | Threshold deriving method for abnormality decision of gate insulating film and inspecting method of semiconductor element using the threshold |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011404A (en) * | 1997-07-03 | 2000-01-04 | Lucent Technologies Inc. | System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor |
| CN101154608A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid medium layer and estimating its electrical parameter |
Non-Patent Citations (1)
| Title |
|---|
| 低温低剂量率下金属-氧化物-半导体器件的辐照效应;张延庆等;《物理学报》;20011220;第50卷(第12期);第2434-2438页 * |
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