CN103389914A - Satellite-borne triple modular redundancy system based on clock synchronization technology - Google Patents
Satellite-borne triple modular redundancy system based on clock synchronization technology Download PDFInfo
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Abstract
The invention discloses a satellite-borne triple modular redundancy system. The satellite-borne triple modular redundancy system comprises a triple modular isomorphism processor module, a clock synchronization module, a redundancy judging module and a model managing module; and a core technology is a clock synchronization technology. The clock synchronization module can be divided into a synchronous loading starting unit and a high-precision clock alignment module; the operation state of microprocessors is monitored through a multistage counting unit realized by an FPGA (Field Programmable Gate Array) to obtain a non-synchronous offset; and an input frequency and keeping time of the triple modular isomorphism processor module are adjusted so that the three microprocessors are at a synchronous operation state. The system is mainly applied to a pico-satellite satellite-borne computer system; the synchronous precision can reach a 10 nanosecond magnitude order; the universality is strong; and the reliability of the satellite-borne computer system can be effectively improved.
Description
Technical field
The present invention relates to a kind of triple-modular redundancy system, relate in particular to the spaceborne triple-modular redundancy system based on Clock Synchronization Technology.
Background technology
The skin satellite refers to the microsatellite of weight range at 1～10Kg, compare conventional satellite, the skin satellite adopts MNT(Micro-Nano Technology more widely,, Micro Electro Mechanical System) the micro-nano technology) and MEMS(Micro Electronic Mechanical System the new and high technology such as, functional density is high, lead time is short, cost is low, and volume is little, and is lightweight.
Spacecraft is among the radiation environment of charged particle all the time when space flight.Microprocessor may cause function to interrupt even losing because of the single-particle disturbance in this radiation environment, thereby leads to disastrous consequence.Cause that this serious problems are mainly total radiation dose effect and single particle effect, single particle effect is divided into again SEU(Signal Event Upset, single-particle inversion) and SEL(Signal Event Latch-up, single event latchup) 2 aspects.The single-particle inversion effect can cause a certain position in the storage unit of digital circuit to be overturn because being interfered, thereby cause the variation of memory contents, also can introduce an of short duration pulse in the output of combinational logic circuit, be the main cause that causes at present microprocessor operational failure.In skin satellite carried computer system, microprocessor is being born the important process such as the management of satellite Star Service, instruction transmitting-receiving, data acquisition, computing and processing, the Stability and dependability index of the stable and whole star of reliable directly impact of its performance, therefore carry out fault-tolerant design to spaceborne computer and be necessary.
The triplication redundancy technology is a kind of to the effective fault-tolerant technique of single-particle inversion, can greatly improve the reliability of circuit.Its basic thought is to generate 2 identical modules for module to be reinforced, then by majority voting, exports, even there is like this module system that breaks down still can work.The basis that triple-modular redundancy system is realized is to guarantee 3 module synchronous operations, so simultaneous techniques is to realize the key of triple-modular redundancy system.Simultaneous techniques is divided into again clock synchronous and 2 kinds of modes of tasks synchronization.
At present, domestic and international spaceborne triple-modular redundancy system adopts the tasks synchronization technology more, compares Clock Synchronization Technology, and its deficiency is: (1) synchronous degree of accuracy is relatively low.Synchronization levels is that the function level is synchronous, and that clock synchronous can reach instruction-level is synchronous; (2) versatility is poor.Tasks synchronization only can adapt to the triple-modular redundancy system under the appointed function demand; (3) higher to software requirement, take the software ample resources.
Summary of the invention
The invention provides the spaceborne triple-modular redundancy system based on Clock Synchronization Technology, adopt Clock Synchronization Technology, this system has improved synchronous degree of accuracy, and highly versatile can improve the reliability of board computer system effectively.
A kind of spaceborne triple-modular redundancy system based on Clock Synchronization Technology is characterized in that described spaceborne triple-modular redundancy system comprises three module isomorphism microprocessor modules, redundancy judging module, schema management module and clock synchronization module; Described three module isomorphism microprocessor modules comprise 3 DSP, and described clock synchronization module comprises one-level synchronization decisions unit, secondary synchronization decisions unit, clock alignment unit, synchronously loads start unit;
Described Clock Synchronization Technology comprises the steps:
Step S1, described 3 DSP of the synchronous startup of described synchronous loading start unit, 3 square-wave signals of described 3 DSP timing outputs are to described one-level synchronization decisions unit;
Step S2, the rising edge counting of described one-level synchronization decisions unit to described 3 square-wave signals, obtain one-level count value and the corresponding one-level synchronous mark signal of each square-wave signal, with one-level count value input described secondary synchronization decisions unit, and at the rising edge of each square-wave signal, the one-level synchronous mark signal of correspondence is inputted described secondary synchronization decisions unit;
Step S3, in described one-level synchronization decisions unit, take one of them one-level count value as benchmark, described 3 one-level count values are all identical synchronous, the output data of described 3 DSP are sent to described redundancy judging module, by described redundancy judging module, the signal condition of described output data is put to the vote, correct result after the output voting, described schema management module is that the different situation of signal condition of the data of output described in described redundancy judging module is counted, and obtains the different count value of signal condition; If at least one is different from the one-level count value as benchmark for other 2 one-level count values, and is asynchronous, by the asynchronous side-play amount of described secondary synchronization decisions unit judges;
Step S4, described secondary synchronization decisions unit is according to the described asynchronous side-play amount of one-level synchronous mark calculated signals of input, with described asynchronous side-play amount input described clock alignment unit, described clock alignment unit asynchronous DSP corresponding according to described asynchronous offset calibration;
Step S5, described secondary synchronization decisions unit is counted asynchronous number of times according to the one-level count value of input, obtains asynchronous count value, with the described schema management module of described asynchronous count value input;
Step S6,, at described schema management module setting threshold, when described asynchronous count value surpasses described threshold value, make corresponding DSP enter fault mode, and handling failure; The count value that described signal condition is different surpasses described threshold value, also makes DSP corresponding to described signal enter fault mode, and handling failure.
Modules in the spaceborne triple-modular redundancy system of the present invention is by FPGA(Field Programmable Gate Array, field programmable gate array) realize.
In described step S3, described redundancy judging module employing 3 is got 2 majority voting and is obtained correct result.Redundancy judging module employing 3 is got 2 majority voting modes and can be improved the reliability of system.
In described step S4, the retention time of asynchronous DSP incoming frequency and described incoming frequency is adjusted in described clock alignment unit according to described asynchronous side-play amount, to calibrate described asynchronous DSP.Wherein the clock calibration module inserts a plurality of phaselocked loop IP kernels for the incoming frequency of output multi-frequency as DSP by FPGA, and determines an optimal frequency retention time, with this, calibrates asynchronous DSP.
In described step S6, described schema management module is carried out handling failure by the DSP of the fault mode that resets.There are interface in schema management module and power-supply system and DSP, after DSP enters fault mode, can carry out power-off restarting or directly enable DSP reset signal pin by the DSP to fault mode, and this DSP that resets, make system recover normal operation.
In described step S6, described schema management module, by independently switching between three mould patterns, two mould patterns and single mode pattern, is carried out handling failure at the described spaceborne triple-modular redundancy system of fault mode decline mould operation.The schema management module is processed assurance isolation of system fault and long-play by falling mould.
Compared with prior art, the present invention has following useful technique effect:
The Clock Synchronization Technology that the spaceborne triple-modular redundancy system of the present invention adopts, synchronous than the function level of tasks synchronization technology, it is synchronous that Clock Synchronization Technology can be promoted to instruction-level with synchronization accuracy, greatly improves its synchronization accuracy.
The Clock Synchronization Technology that the spaceborne triple-modular redundancy system of the present invention adopts, than the tasks synchronization technology, its versatility is higher, has made up portable poor, the weakness that is only applicable to determine the functional requirement system of triple-modular redundancy system in the past.
The spaceborne triple-modular redundancy system of the present invention has the schema management module, and adopt adhesive logic FPGA to expand, check, manage, all software and hardware resources all meet war products one-level derate standard, have increased reliability and the processing power of itself, and the dirigibility extensibility.
Rely on programming logic gate array FPGA, the system fast operation, but efficient solution is softened part, improves software work efficiency.
Be equipped on microsatellite, Primary Component all adopts low-power chip, has overcome the larger weakness of triple-modular redundancy system power consumption in the past.
Description of drawings
Fig. 1 is the schematic diagram of the spaceborne triple-modular redundancy system of the present invention;
Fig. 2 is the schematic diagram of clock synchronization module of the present invention;
Fig. 3 is that the present invention synchronously loads the start-up operation process flow diagram;
Fig. 4 is the operational flowchart of high precision clock alignment module of the present invention;
Fig. 5 is the operational flowchart of schema management module of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail.
Fig. 1 is the schematic diagram of the spaceborne triple-modular redundancy system of the present invention, comprising: three module isomorphism microprocessor modules, clock synchronization module, redundancy judging module, schema management module, interfacing expansion module.Three module isomorphism microprocessor modules are connected with clock synchronization module, schema management module; Clock synchronization module is connected with redundancy judging module, schema management module; The redundancy judging module is connected with interfacing expansion module and schema management module.
The modules of spaceborne triple-modular redundancy system is realized by FPGA.
Three module isomorphism microprocessor modules are comprised of 3 isomorphism low-power consumption DSP, it is the SDRAM of 256Mb that its outside exented memory is selected 2 capacity, input clock both can be provided by the 24MHz crystal oscillator, also can input the homology V-CLK by FPGA, all designs comprise that its supply module all keeps highly consistent on hardware.Three module isomorphism microprocessor modules send instruction, operation result to FPGA by the EMIFA interface, receive simultaneously the data that FPGA gathers from each subsystem; Design interrupt priority level administration module, respond each road external interrupt by the GPIO interface; After choosing the DSP loading mode, by general SPI interface, be used for loading the dsp software program; In addition, GPIO interface timing output synchronous square-wave signal is used for the high precision alignment of clock synchronization module.Three module isomorphism microprocessor modules are as the master control device of triple-modular redundancy system, and this module is mainly used in realizing the functions such as the management of skin satellite Star Service, instruction transmitting-receiving, data acquisition, computing, processing, and coordinate clock synchronization module to realize the instruction-level clock synchronous.
Clock synchronization module is the improvement part of the spaceborne triple-modular redundancy system of the present invention, and its synchronization accuracy directly affects the accuracy of redundancy judging module.As shown in Figure 2, clock synchronization module can be divided into synchronous loading start unit and high precision clock alignment module two parts, and wherein high precision clock alignment module is comprised of one-level synchronization decisions unit, secondary synchronization decisions unit and clock alignment unit.
The operating process of synchronous loading start unit as shown in Figure 3.At first, use to load and use DSP, in same program programming to 3 an isomorphism Flash, after choosing the DSP loading mode, power-off restarting.The implementation method of synchronous loading start unit is as follows:
(1) 3 DSP loads successively;
(2) output loads and successfully indicates to FPGA;
(3) enter the Idle pattern and wait for external interrupt wakeup;
(4) 3 DSP receive the external interrupt from FPGA simultaneously;
(5) externally interrupt processing in function to export to wake up successfully indicating to FPGA;
(6) enter normal mode of operation.
High precision clock alignment module operation flow process as shown in Figure 4.At first, one-level synchronization decisions unit realized in FPGA by 3 one-level synchronous counters, and 3 one-level synchronous counters receive synchronous square-wave signals from 3 DSP respectively.At the rising edge of each synchronous square wave, synchronous counter adds 1, exports simultaneously an one-level count flag signal to next stage synchronization decisions unit.
Then,, take synchronous counter corresponding to DSP1 as benchmark,, if the count value of 3 one-level synchronous counters is all identical, directly enters the redundancy judging module and carry out 3 and get 2 majority votes outputs; If the count value of the synchronous counter that the count value of other any 1 synchronous counter and DSP1 are corresponding is not identical, judge that DSP corresponding to this synchronous counter is asynchronous, enter secondary synchronization decisions unit.
Secondary synchronization decisions unit is realized in FPGA by 2 secondary synchronous counters.Take the one-level synchronous mark signal of DSP1 as benchmark, and another two one-level synchronous mark signals between the time interval in, the system clock rising edge of FPGA is sampled, export to the clock alignment unit by calculating asynchronous side-play amount.Simultaneously, secondary synchronization decisions unit is added up nonsynchronous number of times, exports asynchronous count value to the schema management module, if surpass a set threshold value, the schema management module is carried out fault recovery, fallen the processing such as mould corresponding DSP; If asynchronous number of times does not surpass threshold value, enter one-level synchronization decisions unit, continue to judge whether 3 DSP are in synchronous regime.
Finally, at first the clock alignment unit can insert a plurality of phaselocked loop IP kernels by FPGA and be used for the output multi-frequency, need determine in addition an optimal frequency retention time.According to the asynchronous side-play amount that obtains, the incoming frequency of corresponding DSP is adjusted in the clock alignment unit, thereby reaches the purpose of 3 DSP synchronous operations.
The redundancy judging module realizes with 3 shift registers in FPGA.After the clock synchronization module calibration, 3 DSP synchronous operations, its output data pass to interfacing expansion module after 3 get 2.
The schema management module has been mainly used in the conversion when Star Service computer operation pattern, and it needs 2 monitor counters of design in FPGA, is used for the out of step conditions of DSP2 and DSP3 is counted; In addition, also need 3 counters of another design, be used for recording the output signal situation different from all the other of DSP.
At first under normal circumstances, the Star Service counter is in the triplication redundancy clock synchronization module, if the asynchronous Count of Status value of certain DSP has surpassed set threshold value, the Star Service computing machine enters fault mode; If 2 DSP are different for the output of certain DSP and all the other, and its different number of times also surpass set threshold value, and the Star Service computing machine enters fault mode equally.
After the Star Service computing machine enters fault mode, can send the corresponding DSP of reseting signal reset by FPGA, also can be cut off by power management module the power supply of corresponding DSP, thereby fall mould to 2 mould backup mode or single mode pattern.
The interfacing expansion module of Star Service computing machine is by general SPI, I
2C, UART interface are connected with subsystems such as skin Satellite TT subsystem, appearance control subsystem, load subsystem, rail control subsystem, thermal control subsystems, the sequence of operations such as data acquisition, instruction transmission.
This spaceborne triple-modular redundancy system is mainly used in skin satellite carried computer system, and synchronization accuracy can be up to 10 nanosecond orders, and highly versatile can improve the reliability of board computer system effectively.
Claims (5)
1. the spaceborne triple-modular redundancy system based on Clock Synchronization Technology, is characterized in that, described spaceborne triple-modular redundancy system comprises three module isomorphism microprocessor modules, redundancy judging module, schema management module and clock synchronization module; Described three module isomorphism microprocessor modules comprise 3 DSP, and described clock synchronization module comprises one-level synchronization decisions unit, secondary synchronization decisions unit, clock alignment unit, synchronously loads start unit;
Described Clock Synchronization Technology comprises the steps:
Step S1, described 3 DSP of the synchronous startup of described synchronous loading start unit, 3 square-wave signals of described 3 DSP timing outputs are to described one-level synchronization decisions unit;
Step S2, the rising edge counting of described one-level synchronization decisions unit to described 3 square-wave signals, obtain one-level count value and the corresponding one-level synchronous mark signal of each square-wave signal, with one-level count value input described secondary synchronization decisions unit, and at the rising edge of each square-wave signal, the one-level synchronous mark signal of correspondence is inputted described secondary synchronization decisions unit;
Step S3, in described one-level synchronization decisions unit, take one of them one-level count value as benchmark, described 3 one-level count values are all identical synchronous, the output data of described 3 DSP are sent to described redundancy judging module, by described redundancy judging module, the signal condition of described output data is put to the vote, correct result after the output voting, described schema management module is that the different situation of signal condition of the data of output described in described redundancy judging module is counted, and obtains the different count value of signal condition; If at least one is different from the one-level count value as benchmark for other 2 one-level count values, and is asynchronous, by the asynchronous side-play amount of described secondary synchronization decisions unit judges;
Step S4, described secondary synchronization decisions unit is according to the described asynchronous side-play amount of one-level synchronous mark calculated signals of input, with described asynchronous side-play amount input described clock alignment unit, described clock alignment unit asynchronous DSP corresponding according to described asynchronous offset calibration;
Step S5, described secondary synchronization decisions unit is counted asynchronous number of times according to the one-level count value of input, obtains asynchronous count value, with the described schema management module of described asynchronous count value input;
Step S6,, at described schema management module setting threshold, when described asynchronous count value surpasses described threshold value, make corresponding DSP enter fault mode, and handling failure; The count value that described signal condition is different surpasses described threshold value, also makes DSP corresponding to described signal enter fault mode, and handling failure.
2., as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S3, described redundancy judging module employing 3 is got 2 majority voting and is obtained correct result.
3. as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S4, the incoming frequency of asynchronous DSP and the retention time of described incoming frequency are adjusted according to described asynchronous side-play amount in described clock alignment unit, to calibrate described asynchronous DSP.
4., as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S6, described schema management module is carried out handling failure by the DSP of the fault mode that resets.
5. as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S6, described schema management module, by independently switching between three mould patterns, two mould patterns and single mode pattern, is carried out handling failure at the described spaceborne triple-modular redundancy system of fault mode decline mould operation.
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| CN106533601A (en) * | 2016-10-27 | 2017-03-22 | 中国电子科技集团公司第三十二研究所 | Method for clock synchronization in modular redundancy system |
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| CN104062923B (en) * | 2014-07-01 | 2016-11-02 | 中国科学院长春光学精密机械与物理研究所 | Space flight multichannel TDICCD camera synchronous method |
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| CN111176890A (en) * | 2019-12-16 | 2020-05-19 | 上海航天控制技术研究所 | Data storage and exception recovery method for satellite-borne software |
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| CN111431651A (en) * | 2020-03-04 | 2020-07-17 | 上海航天控制技术研究所 | Multicomputer synchronous operation and time alignment method suitable for Mars detection |
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| CN111538369B (en) * | 2020-04-17 | 2021-09-24 | 北京中科宇航技术有限公司 | Triple-modular redundancy computer clock synchronization method and system |
| CN111538369A (en) * | 2020-04-17 | 2020-08-14 | 北京中科宇航技术有限公司 | Triple-modular redundancy computer clock synchronization method and system |
| CN114301566A (en) * | 2021-03-25 | 2022-04-08 | 井芯微电子技术(天津)有限公司 | Clock synchronization method of redundancy system, redundancy system and network system |
| CN114301566B (en) * | 2021-03-25 | 2023-11-21 | 井芯微电子技术(天津)有限公司 | Clock synchronization method of redundant system, redundant system and network system |
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