CN103346131A - Fine-pitch POP type sealing structure and sealing method - Google Patents
Fine-pitch POP type sealing structure and sealing method Download PDFInfo
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- CN103346131A CN103346131A CN2013102584309A CN201310258430A CN103346131A CN 103346131 A CN103346131 A CN 103346131A CN 2013102584309 A CN2013102584309 A CN 2013102584309A CN 201310258430 A CN201310258430 A CN 201310258430A CN 103346131 A CN103346131 A CN 103346131A
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- packaging body
- infrabasal plate
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- upper substrate
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Abstract
The invention discloses a fine-pitch POP type sealing structure and sealing method. Grooves are formed in an upper substrate and a lower substrate, a chip of a lower substrate is sealed in the corresponding area of the groove, the separation distance between the upper substrate and the lower substrate are greatly shortened, therefore, the size of a welding ball which needs to be larger than the sealing thickness of the chip originally is greatly reduced, and the separation distance of welding balls is greatly reduced. Compared with the prior art, according to the technical scheme, the fine-pitch POP type sealing structure is simple in structure and easy to manufacture, and the quality of a product is improved due to the fact that destructive punching is avoided.
Description
Technical field
The present invention relates to the integrated circuit encapsulation field, particularly, is to form thin space encapsulating structure and method for packing in a kind of stacked package technology (POP).
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit is constantly dwindled, and interconnection density improves constantly.The user improves constantly the requirement of high-performance low power consumption simultaneously.In this case, the mode that improves performance by the live width of further dwindling interconnection line is subjected to the restriction of physical characteristics of materials and apparatus and process, and the resistance capacitance of two-dimentional interconnection line (RC) postpones to become gradually the bottleneck that restriction semiconductor core piece performance improves.
Piling up of chip is one of main path that improves highly denseization of Electronic Packaging, and as the highly dense integrated main mode of present encapsulation, POP (package on package, stacked package) is more and more paid attention to.A typical two-layer POP design as shown in Figure 1, the reflux course of following packaging body 13 by soldered ball 12 be welded to packaging body 11 below, more multi-layered POP designs can repeat as above process.Chip and last packaging body on following packaging body produce interference, soldered ball 12 diameters of following packaging body 13 peripheries generally are designed to the height greater than chip, but so design has just increased the size of soldered ball 12 and its spacing, and it is opposing that this and encapsulation technology highly dense integrated requires.
Therefore having put down in writing use TMV (Through Mold Via, embedding through hole) technology in the patent documentation of U.S. Patent number: US7671457 realizes thin space POP packaging technology.As shown in Figure 2, this encapsulating structure comprises packaging body 11 ', following packaging body 12 ', and at the plastic packaging glue 13 ' between the packaging body up and down.The TMV technology is by carrying out laser drilling at plastic packaging glue 13 ', produce running through the pore 30 ' of plastic packaging glue 13 ', carries out metal filledly then in pore 30 ', realizes the electrical connection of packaging body up and down.Yet the weak point of TMV technology is that do destructiveness to the intact product of plastic packaging with laser punches, and correlation step is more, comprises plastic packaging, punching, filling scolder, applying etc., and implementation procedure is complicated.
Therefore, be necessary to propose a kind of new thin space POP packaging technology, to solve implementation procedure past complicated problems in the prior art.
Summary of the invention
In view of this, the objective of the invention is to propose a kind of thin space POP formula encapsulating structure and method for packing, characteristics simple in structure, that be easy to make that this encapsulating structure and method for packing have.
A kind of thin space POP formula encapsulating structure according to purpose proposition of the present invention, comprise the packaging body of two interconnection up and down, on, between the following packaging body electric intercommunication is arranged, the described substrate of going up packaging body is upper substrate, the substrate of following packaging body is infrabasal plate, offer groove at least one in described upper substrate and the infrabasal plate, the chip encapsulation region of the corresponding infrabasal plate of this groove, one or more chips are mounted in the chip encapsulation region of this infrabasal plate in the upside-down mounting mode, and form electric intercommunication with infrabasal plate, on the regional correspondence beyond the groove, the interconnection district of following packaging body, this interconnection district is provided with some soldered balls, form interconnection by described soldered ball between upper substrate and the infrabasal plate, this interconnection forms at least one and is electrically connected, and also is provided with filler in the gap of upper substrate and infrabasal plate.
Preferably, described groove is opened in the upper surface of infrabasal plate, and described one or more chips are mounted in this groove in the upside-down mounting mode.
Preferably, described groove is opened in the upper substrate bottom surface, and described one or more chips are encapsulated in the below of the corresponding described groove of infrabasal plate upper surface.
Preferably, described upper substrate bottom surface and infrabasal plate upper surface are offered groove simultaneously, and one or more chips of described infrabasal plate are encapsulated in the space of these two grooves.
Preferably, described upper substrate is provided with one or more chips, when a plurality of chip, described a plurality of chips with side by side or the mode of lamination be encapsulated in the upper surface of described upper substrate.
Preferably, described top of going up packaging body also is provided with one or more packaging bodies.
Preferably, the below of described down packaging body and another or the interconnection of a plurality of packaging body perhaps interconnect with a PCB, and form an electrical connection at least.
Preferably, described filler is the epoxy scaling powder.
The invention allows for a kind of thin space POP formula method for packing simultaneously, comprise the manufacture craft of packaging body, the manufacture craft of following packaging body and the interconnection process of upper and lower encapsulation,
Be included in the step of offering groove on infrabasal plate or the upper substrate in the manufacture craft of the manufacture craft of described following packaging body or last packaging body, described groove correspondence is at the chip installation area of infrabasal plate, also be included in the step of implanting the thin space soldered ball on the upper substrate, the zone of described thin space soldered ball correspondence outside described groove in the manufacture craft of described upward packaging body.
Preferably, also be included in down packaging body bottom surface interconnect another or a plurality of packaging body, the step of the pcb board that perhaps interconnects is perhaps in the step of the upper-surface interconnection of last packaging body another or a plurality of packaging bodies.
Thin space POP formula encapsulating structure of the present invention, by offering groove at upper and lower base plate, the chip of infrabasal plate is encapsulated in the zone of groove correspondence, make that the spacing between the upper and lower base plate is shortened greatly, thus, can make that script need be reduced greater than the size of solder ball of chip package thickness, thereby significantly reduce the spacing between this soldered ball.Compared with prior art, technical scheme of the present invention is simple in structure, is easy to make, and owing to avoided destructive punching, makes the quality of product get a promotion.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is existing two-layer POP encapsulating structure schematic diagram.
Fig. 2 is to use the POP encapsulating structure schematic diagram of TMV technology.
Fig. 3 is the thin space POP formula encapsulating structure schematic diagram of first embodiment of the invention.
Fig. 4 is the thin space POP formula encapsulating structure schematic diagram of second embodiment of the invention.
Fig. 5 is the thin space POP formula encapsulating structure schematic diagram of third embodiment of the invention.
Fig. 6 A-6C is the thin space POP formula method for packing schematic flow sheet under the first embodiment of the invention.
Embodiment
Just as described in the background art, in the existing P OP formula encapsulation technology, therefore common process can't realize the encapsulation interconnection of thin space because pedestal need guarantee to be higher than chip thickness.And in TMV technology, by laser drilling, though can produce thinner conductive through hole at packaging plastic, but because laser drilling itself is a kind of destructive technology, add this Technology Need and use correlation step such as plastic packaging, punching, filling scolder, applying, make that the POP encapsulation technology under the whole TMV technology is too loaded down with trivial details, efficient and the cost of influence encapsulation.
Therefore, the present invention proposes a kind of encapsulating structure and the corresponding method for packing that can realize thin space POP formula encapsulation technology.This encapsulating structure is realized thin space between the pedestal by the size that reduces pedestal itself, and its technical problem that will overcome is how the size of pedestal to be dwindled.In the prior art, pedestal is subject to chip and is encapsulated in intrinsic height on the substrate, for instance, at present common chip thickness is greater than about 150um-200um, to lose money instead of making money encapsulation, chip height after the encapsulation is greatly about 200um-250um, and in order to guarantee the interconnection validity of packaging body up and down, often the sphere diameter with pedestal is set in about 300um.And when usually carrying out the interconnection of encapsulation point up and down with pedestal, the spacing between each salient point should be about 2 times of the own size of salient point, can prevent from occurring when reflow soldering the short circuit problem of adjacent salient point like this.So, the distance between the pad is near 500um-600um, even some is near 1mm, and such spacing obviously can't be competent at for the highly integrated encapsulation technology of present high density.In order to solve this technical problem, the technological means that the present invention adopts is: offer groove in one of them of upper and lower base plate, allow the chip on the infrabasal plate be encapsulated in this groove, zone outside the groove then arranges pedestal, because the existence of groove, make the plane at the relative pedestal of packaging height place of chip reduce greatly, can reduce up and down by two packaging bodies like this in the spacing of interconnect area, thereby reduce the size of pedestal, reach the effect that reduces spot pitch.
To be described in detail technical scheme of the present invention by embodiment below.
See also Fig. 3, Fig. 3 is the schematic diagram of the thin space formula POP formula encapsulating structure under the first embodiment of the invention.As shown in the figure, this encapsulating structure 100 comprises the packaging body 110,120 of two interconnection up and down, and electric intercommunication is arranged between the packaging body up and down.The substrate of last packaging body 110 is upper substrate 111, the substrate of packaging body 120 is infrabasal plate 121 down.Wherein offer groove on the upper surface of infrabasal plate 121, the chip encapsulation region of the corresponding infrabasal plate 121 of this groove, one or more chips 122 are mounted in the groove of infrabasal plate 121 in the upside-down mounting mode, and form electric intercommunication with infrabasal plate 121.Zone beyond groove area forms interconnection by soldered ball 114 or alternate manner between upper substrate 111 and the infrabasal plate 121, and this interconnection forms at least one effective electrical connection.Be provided with filler 123 in the gap of upper substrate 111 and infrabasal plate 121 simultaneously, this filler 123 is epoxy scaling powder or other filler.
Above-mentioned last packaging body 110 might arrange one or more chips 112 on upper substrate 111, these chips 112 can be arranged on the upper surface of upper substrate 111 in mode side by side, also can be arranged on the upper surface of upper substrate 111 in the mode of piling up.Has electrical interconnection between these chips 112 and the upper substrate 111, the form of electrical interconnection can be passed through the form of lead-in wire as shown in FIG. and carry out, namely chip 112 and upper substrate 111 are provided with pad (pad), by wire bonds (wire bonding) pad of chip 112 and the pad of upper substrate 111 are connected then, realize electrical interconnection.Also can be undertaken by the form of ball grid array, namely in chip 112 bottom surfaces and upper substrate 111 upper surface correspondence positions pad is set separately, by soldered ball these pads be connected, realize electrical interconnection.Certainly, as the form of other known chip electrical interconnection of this area, also can be used as optional execution mode and be applied in herein.On upper substrate 111, be provided with the conductive through hole (not shown) that runs through whole base plate, the position of these conductive through holes can be set directly at upper substrate 111 and the pad below that chip 112 interconnects, and also can be connected to by the metal interconnecting layer on the substrate on these pads.The effect of these conductive through holes is that the chip with the upper surface of upper substrate is electrically connected at least one soldered ball 114 of bottom surface, thereby realizes effective electrical interconnection of packaging body up and down.In the outside of chip 112, cover one deck plastic packaging glue 113 and encapsulate fixing.
The top that should go up encapsulation 110 can also allow by certain approach interconnect another or a plurality of packaging body again, and forms at least one electrical connection.
Above-mentioned following packaging body 120, at the groove that infrabasal plate 121 is offered, its width is at least greater than the width of a chip, operates easily when making flip-chip, the width of this groove has under the situation of enough areas as the bonding pad of soldered ball satisfying infrabasal plate 121, and that can do is big as far as possible.The degree of depth of groove has determined the packaging height of chip 122, under the intensity situation that guarantees infrabasal plate 121, the degree of depth of this groove can be dug deeply as far as possible, can make the spacing between the upper and lower base plate be subjected to the influence of chip 122 packaging height more and more littler like this, it is littler just to mean that also the soldered ball diameter that connects upper and lower base plate can be done.Preferably, in the present invention, consider the complexity of infrabasal plate 121 groovings, with this groove the degree of depth be set at 100-200um, like this, chip 122 is encapsulated in exposing highly greatly about about 50 to 150um in this groove, and the sphere diameter of soldered ball 114 can be made into greatly about 100um-200um, spacing between soldered ball can be produced on 200um-400um, reaches the purpose of thin space POP encapsulation.
Further, filler 123 is soft semi-fluid colloid in the normal state, and when soldered ball 114 welds when living in down packaging body by reflux technique, 123 in this filler is subjected to hot curing, forms the relatively encapsulated layer of hard.
Following packaging body 120 is the same with last packaging body 110, thereunder allows one or more packaging bodies that interconnect again, perhaps directly will descend packaging body 120 to be welded on the pcb board, forms at least one electrical connection.As described in Figure, this time packaging body directly can be interconnected with a pcb board by soldered ball 124, and form an electrical connection at least.
See also Fig. 4, Fig. 4 is the schematic diagram of the thin space POP encapsulating structure under the second embodiment of the invention.In this embodiment, offer a groove in the bottom surface of upper substrate 111, this groove correspondence is above infrabasal plate chip encapsulation region, and the upper surface of one or more chip 122 packed infrabasal plates 121 is to below that should groove, and all the other are then identical with execution mode one.
See also Fig. 5, Fig. 5 is the schematic diagram of the thin space POP encapsulating structure under the third embodiment of the invention.In this embodiment, upper substrate 111 bottom surfaces and infrabasal plate 121 end faces have all been offered groove, make these two groove correspondences in the position of infrabasal plate chip encapsulation region equally, one or more chips 122 of infrabasal plate 121 are encapsulated in these two groove spaces.In this embodiment because upper and lower base plate all offered groove, therefore can so that upper and lower base plate keep more raw substrate in the position of offering groove, make upper and lower base plate intensity can both be better than first execution mode and second execution mode.
Below, be described in detail with regard to thin space POP method for packing of the present invention.
See also Fig. 6 A-6C, Fig. 6 A-6C is the thin space POP method for packing flow chart under the first embodiment of the invention.Fig. 6 A is the making of packaging body down, and Fig. 6 B is the making of going up packaging body, and Fig. 6 C will connect the schematic diagram that a packaging body interconnects up and down.
Wherein descend the making of packaging body to comprise step:
1.1) offer groove at the infrabasal plate upper surface;
1.2) with the upside-down mounting mode with one or more chip attachment in the groove of infrabasal plate, chip bottom is filled the end and is filled glue;
1.3) applying filler at the infrabasal plate upper surface, this filler is such as being epoxy scaling powder or other gentle matter colloid;
The making of last packaging body comprises step:
2.1) encapsulate one or more chips at the upper substrate upper surface, comprise steps such as paster, bonding wire, plastic packaging.
2.2) implant a plurality of thin space soldered balls at the lower surface of upper substrate, the position correspondence of these soldered balls is on the zone outside the infrabasal plate groove.
The packaging body contraposition is fitted up and down at last, makes soldered ball with the upper and lower base plate solder interconnections by Reflow Soldering, forms a packaging body.
In some applications, also be included in and continue the one or more packaging bodies of interconnection on the packaging body, infrabasal plate then can interconnect directly on the pcb board, perhaps also can continue one or more other packaging bodies that interconnect.
During encapsulating structure in the corresponding above-mentioned execution mode two, then on making, during packaging body, need offer groove in the position of the bottom surface of last packaging body correspondence infrabasal plate chip packaging area, at this moment, just save the step of offering groove in the manufacturing process of following packaging body.All the other steps are identical with execution mode one, repeat no more herein.
During encapsulating structure in the corresponding above-mentioned execution mode three, then at last packaging body with encapsulate system down and do in the process, all need to offer groove.
In sum, the present invention proposes a kind of thin space POP encapsulating structure and method for packing, by offering groove at upper and lower base plate, the chip of infrabasal plate is encapsulated in the zone of groove correspondence, make that the spacing between the upper and lower base plate is shortened greatly, thus, can make that script need be reduced greater than the size of solder ball of chip package thickness, thereby significantly reduce the spacing between this soldered ball.Compared with prior art, technical scheme of the present invention is simple in structure, is easy to make, and owing to avoided destructive punching, makes the quality of product get a promotion.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. thin space POP formula encapsulating structure, comprise the packaging body of two interconnection up and down, on, between the following packaging body electric intercommunication is arranged, the described substrate of going up packaging body is upper substrate, the substrate of following packaging body is infrabasal plate, it is characterized in that: offer groove at least one in described upper substrate and the infrabasal plate, the chip encapsulation region of the corresponding infrabasal plate of this groove, one or more chips are mounted in the chip encapsulation region of this infrabasal plate in the upside-down mounting mode, and form electric intercommunication with infrabasal plate, on the regional correspondence beyond the groove, the interconnection district of following packaging body, this interconnection district is provided with some soldered balls, form interconnection by described soldered ball between upper substrate and the infrabasal plate, this interconnection forms at least one and is electrically connected, and also is provided with filler in the gap of upper substrate and infrabasal plate.
2. thin space POP formula encapsulating structure as claimed in claim 1, it is characterized in that: described groove is opened in the upper surface of infrabasal plate, and described one or more chips are mounted in this groove in the upside-down mounting mode.
3. thin space POP formula encapsulating structure as claimed in claim 1, it is characterized in that: described groove is opened in the upper substrate bottom surface, and described one or more chips are encapsulated in the below of the corresponding described groove of infrabasal plate upper surface.
4. thin space POP formula encapsulating structure as claimed in claim 1, it is characterized in that: described upper substrate bottom surface and infrabasal plate upper surface are offered groove simultaneously, and one or more chips of described infrabasal plate are encapsulated in the space of these two grooves.
5. as any described thin space POP formula encapsulating structure of claim 1-4, it is characterized in that: described upper substrate is provided with one or more chips, when a plurality of chip, described a plurality of chips with side by side or the mode of lamination be encapsulated in the upper surface of described upper substrate.
6. as any described thin space POP formula encapsulating structure of claim 1-4, it is characterized in that: described top of going up packaging body also is provided with one or more packaging bodies.
7. as any described thin space POP formula encapsulating structure of claim 1-4, it is characterized in that: the below of described down packaging body and another or the interconnection of a plurality of packaging body perhaps interconnect with a PCB, and form an electrical connection at least.
8. as any described thin space POP formula encapsulating structure of claim 1-4, it is characterized in that: described filler is the epoxy scaling powder.
9. a thin space POP formula method for packing comprises the manufacture craft of packaging body, the manufacture craft of following packaging body and the interconnection process of upper and lower encapsulation, it is characterized in that:
Be included in the step of offering groove on infrabasal plate or the upper substrate in the manufacture craft of the manufacture craft of described following packaging body or last packaging body, described groove correspondence is at the chip installation area of infrabasal plate, also be included in the step of implanting the thin space soldered ball on the upper substrate, the zone of described thin space soldered ball correspondence outside described groove in the manufacture craft of described upward packaging body.
10. thin space POP formula method for packing as claimed in claim 9, it is characterized in that: also be included in down packaging body bottom surface interconnect another or a plurality of packaging body, perhaps the interconnect step of a pcb board is perhaps in the step of the upper-surface interconnection of last packaging body another or a plurality of packaging bodies.
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| CN2013102584309A CN103346131A (en) | 2013-06-25 | 2013-06-25 | Fine-pitch POP type sealing structure and sealing method |
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| CN2013102584309A CN103346131A (en) | 2013-06-25 | 2013-06-25 | Fine-pitch POP type sealing structure and sealing method |
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