CN103338174A - Generation device of data clock of responder - Google Patents
Generation device of data clock of responder Download PDFInfo
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- CN103338174A CN103338174A CN201310257643XA CN201310257643A CN103338174A CN 103338174 A CN103338174 A CN 103338174A CN 201310257643X A CN201310257643X A CN 201310257643XA CN 201310257643 A CN201310257643 A CN 201310257643A CN 103338174 A CN103338174 A CN 103338174A
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- frequency division
- division counter
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Abstract
The invention discloses a generation device of a data clock of a responder. The generation device comprises an FPGA (field programmable gate array), wherein the FPGA is loaded with a judgment module, a frequency division counting module and a clock output module. According to the generation device, a binary FSK (frequency shift keying) signal is taken as a counting clock of the frequency division counting module, the counting range of the frequency division counting module is dynamically adjusted in combination with message data of the responder, and the stable data clock of 564 KHz can be extracted from the FSK signal to read the message data of the responder in a memory. Therefore, the power consumption of the whole responder can be reduced while the hardware cost is lowered.
Description
Technical field
The invention belongs to railway system control technology field, be specifically related to a kind of generating means of transponder data clock.
Background technology
China train control system (Chinese Train Control System, CTCS) standard is with reference to European Train Control System (European Train Control System, ETCS) formulate, in this standard, the railway transponder makes the automaticity of train control system further improve as the key component of train operation control system.The effect of railway transponder in the train supervision device has: can realize the absolute hi-Fix (precision can reach+1 meter) of train, need not manual intervention, it is minimum that the security incident that human error is caused is reduced to; Can be to train transmitting line longitudinal data, bridge tunnel positional information, circuit speed-limiting messages, even temporary speed limitation information; Also the information of the other electronic unit of rail can be passed to train etc. fast.
The operation principle of transponder is: when train arrives the ground transponder efficient working range, be that the vehicle-mounted power antenna of 27.095MHz activates transponder by the frequency that is installed on the train bottom, transponder begins to provide running information to train.These information are referred to as the transponder message, by FSK(Frequency-shift keying, frequency shift keying) modulation after send; This shows the correct traffic safety that is reliably directly determining train of transponder message, and can the correctness of transponder data clock frequency have determined directly the transponder message correctly to be sent.
This railway transponder technology is monopolized by state external signal company (such as Siemens, Alstom etc.) for a long time, thereby causes transponder expensive.Along with the develop rapidly of railway construction in China, be badly in need of the railway transponder with Intellectual Property in China.Required mobile unit of circuit of general construction and transponder will spend tens million of RMB, and the transponder of independent research can better be contributed for the development of China railways cause when saving a large amount of foreign exchanges for China.
In transponder national standard (CTCS), stipulated that clearly two frequencies of the fsk signal that transponder adopts are: 4.512MHz and 3.948MHz, and the data transfer rate of message is 564kbps.Because transponder is very limited by the energy that electromagnetic coupled obtains, the power consumption of whole transponder is just very strict.Generation about data clock at present mainly contains two kinds of methods: first kind is the clock that produces 564KHz by high-frequency crystal oscillator frequency division, but the more energy of crystal oscillator consumption rate, and this also becomes the shortcoming of this technology maximum.
Publication number is that the Chinese patent of CN101364816 discloses another kind of transponder technology, and its signal by the 27.095MHz on the power antenna carries out the data clock that 48 frequency divisions obtain 564KHz; This technology does not need extra crystal oscillator, has saved power consumption greatly, but will carry out 48 frequency divisions after all, and hardware spending and power consumption are still bigger.
Summary of the invention
At the above-mentioned technical problem of existing in prior technology, the invention provides a kind of generating means of transponder data clock, can when reducing hardware spending, also can reduce the power consumption of whole transponder.
A kind of generating means of transponder data clock comprises the FPGA(field programmable gate array), described FPGA is loaded with judging module, frequency division counter module and clock output module; Wherein:
Described judging module is used for receiving the message data of transponder, generates the count range of frequency division counter module according to described message data;
Described frequency division counter module is used for fsk signal counting in described count range as counting clock;
Described clock output module is used for the highest order of frequency division counter module output count results is also exported as the transponder data clock.
Described judging module is as follows according to the process of the count range of message data generation frequency division counter module:
When the frequency division counter module with fsk signal rising edge or trailing edge under the prerequisite as counting clock, if the message data that judging module receives is 1, then the count range of judging module output is 0～6; If the message data that judging module receives is 0, then the count range of judging module output is 0～7;
When the frequency division counter module with fsk signal rising edge and trailing edge jointly under the prerequisite as counting clock, if the message data that judging module receives is 1, then the count range of judging module output is 0～13; If the message data that judging module receives is 0, then the count range of judging module output is 0～15.
Described judging module receives the count results of frequency division counter module output, if count results reaches the maximum of count range, then will after the described count results zero clearing frequency division counter module be counted again.
Described frequency division counter module adopts 3 digit counters or 4 digit counters; If as counting clock, then the frequency division counter module adopts 3 digit counters with fsk signal rising edge or trailing edge; If jointly as counting clock, then the frequency division counter module adopts 4 digit counters with fsk signal rising edge and trailing edge.
The present invention analyzes fsk signal frequency (4.512MHz or 3.948MHz) and the data rate (564kbps that stipulates in the transponder relevant criterion, corresponding read data clock is 564KHz) find that the fsk signal frequency is 7 times (3.948MHz/564KHz) or 8 times (4.512MHz/564KHz) of data rate approximately.With the counting clock of fsk signal as the frequency division counter module, realize dynamic frequency division by the count range that produces frequency counter in conjunction with the transponder message data dynamically, can from fsk signal, extract the data clock of stable 564KHz, read transponder message data in the memory with this.
The present invention is with the fsk signal of the lower frequency counting clock as frequency counter, can be met the 564KHz data clock that the transponder relevant criterion requires so the present invention at most only needs to carry out 16 frequency divisions (4 frequency counters of needs).Carry out the method that 48 frequency divisions (needing 6 frequency counters) obtain the data clock of 564KHz with respect to the signal by the 27.095MHz on the power antenna, data clock generating means of the present invention also can reduce the power consumption of whole transponder when reducing hardware spending.
Description of drawings
Fig. 1 is the structural representation of generating means of the present invention.
Fig. 2 is when being frequency division counter building block technique clock with binary FSK signal rising edge, the simulation result under the Modelsim of simulation software.
Fig. 3 is when being frequency division counter building block technique clock with binary FSK signal trailing edge, the simulation result under the Modelsim of simulation software.
When Fig. 4 is frequency division counter building block technique clock for the while with binary FSK signal rising edge and trailing edge, the simulation result under the Modelsim of simulation software.
Embodiment
In order more specifically to describe the present invention, below in conjunction with the drawings and the specific embodiments technical scheme of the present invention and relative theory thereof are elaborated.
As shown in Figure 1, a kind of generating means of transponder data clock comprises FPGA, and FPGA is loaded with judging module, frequency division counter module and clock output module; Judging module, frequency division counter module and clock output module are all by realizing by the program code programming under the FPGA platform; Wherein:
Judging module is used for reading the message data that receives transponder from external memory storage, generates the count range of frequency division counter module according to message data; The concrete operations rules are as follows:
When the frequency division counter module with fsk signal rising edge or trailing edge as counting clock, if the message data that judging module receives is 1, then the count range of judging module output is 0～6; If the message data that judging module receives is 0, then the count range of judging module output is 0～7;
When the frequency division counter module with fsk signal rising edge and trailing edge jointly as counting clock, if the message data that judging module receives is 1, then the count range of judging module output is 0～13; If the message data that judging module receives is 0, then the count range of judging module output is 0～15.
The fsk signal that the frequency division counter module is used for generating with outside FSK oscillator is counted in the count range that judging module generates as counting clock; In the present embodiment, if with fsk signal rising edge or trailing edge as counting clock, then the frequency division counter module adopts 3 digit counters; If jointly as counting clock, then the frequency division counter module adopts 4 digit counters with fsk signal rising edge and trailing edge.
When the count results of frequency division counter module output reaches the maximum of count range, judging module then will count the frequency division counter module after this count results zero clearing again.
The clock output module is used for highest order with frequency division counter module output count results as the transponder data clock and exports to peripheral storage.
In the present embodiment, the frequency division counter module with binary FSK signal rising edge as counting clock; This frequency division counter module is 3 digit counters so, judging module root transponder message data produces the count range of frequency division counter module, if the transponder message data is " 1 ", the frequency division counter module count down to 6 from 0, if the transponder message data is " 0 ", the frequency division counter module count down to 7 from 0; Last with the tertiary result of frequency division counter module as the data clock that extracts.As shown in Figure 2, at each binary FSK signal rising edge, the frequency division counter module adds 1 as can be seen.The data clock frequency that finally extracts is 564KHz, satisfies the requirement of transponder.
The frequency division counter module also can binary FSK signal trailing edge as counting clock, this frequency division counter module also is 3 digit counters, judging module root transponder message data is adjudicated the count range of frequency division counter module, if the transponder message data is " 1 ", the frequency division counter module count down to 6 from 0, if the transponder message data is " 0 ", the frequency division counter module count down to 7 from 0; Last with the tertiary result of frequency division counter module as the data clock that extracts.As shown in Figure 3, at each binary FSK signal trailing edge, the frequency division counter module adds 1 as can be seen.The data clock frequency that finally extracts is 564KHz, satisfies the requirement of transponder.
If the frequency division counter module simultaneously with binary FSK signal rising edge and trailing edge as counting clock, this frequency division counter module is 4 digit counters so, judging module root transponder message data is adjudicated the count range of frequency division counter module, if the transponder message data is " 1 ", the frequency division counter module count down to 13 from 0, if the transponder message data is " 0 ", the frequency division counter module count down to 15 from 0; At last with the result of the 4th of frequency division counter module as the data clock that extracts.As shown in Figure 4, at each binary FSK signal rising edge and trailing edge, the frequency division counter module adds 1 as can be seen.The data clock frequency that finally extracts is 564KHz, also satisfies the requirement of transponder.
Present embodiment is by analyzing fsk signal frequency (4.512MHz or 3.948MHz) and the data rate (564kbps that stipulates in the transponder relevant criterion, corresponding read data clock is 564KHz) find that the fsk signal frequency is 7 times (3.948MHz/564KHz) or 8 times (4.512MHz/564KHz) of data rate approximately.So utilize fsk signal as the counting clock of frequency division counter module, realize dynamic frequency division by the count range that produces frequency counter in conjunction with the transponder message data dynamically, can from fsk signal, extract the data clock of stable 564KHz, read transponder message data in the memory with this.
Present embodiment can be met the 564KHz data clock that the transponder relevant criterion requires with the fsk signal of the lower frequency counting clock as the frequency division counter module so at most only need to carry out 16 frequency divisions (4 frequency counters of needs).Carry out the method that 48 frequency divisions (needing 6 frequency counters) obtain the data clock of 564KHz with respect to the signal by the 27.095MHz on the power antenna, the data clock generating means of present embodiment also can reduce the power consumption of whole transponder when reducing hardware spending.
Claims (6)
1. the generating means of a transponder data clock comprises FPGA; It is characterized in that: described FPGA is loaded with judging module, frequency division counter module and clock output module; Wherein:
Described judging module is used for receiving the message data of transponder, generates the count range of frequency division counter module according to described message data;
Described frequency division counter module is used for fsk signal counting in described count range as counting clock;
Described clock output module is used for the highest order of frequency division counter module output count results is also exported as the transponder data clock.
2. generating means according to claim 1, it is characterized in that: when the frequency division counter module with fsk signal rising edge or trailing edge under the prerequisite as counting clock, if the message data that judging module receives is 1, then the count range of judging module output is 0～6; If the message data that judging module receives is 0, then the count range of judging module output is 0～7.
3. generating means according to claim 1, it is characterized in that: when the frequency division counter module with fsk signal rising edge and trailing edge jointly under the prerequisite as counting clock, if the message data that judging module receives is 1, then the count range of judging module output is 0～13; If the message data that judging module receives is 0, then the count range of judging module output is 0～15.
4. generating means according to claim 1, it is characterized in that: described judging module receives the count results of frequency division counter module output, if count results reaches the maximum of count range, then will after the described count results zero clearing frequency division counter module be counted again.
5. generating means according to claim 1, it is characterized in that: described frequency division counter module adopts 3 digit counters or 4 digit counters.
6. generating means according to claim 5 is characterized in that: if with fsk signal rising edge or trailing edge as counting clock, then the frequency division counter module adopts 3 digit counters; If jointly as counting clock, then the frequency division counter module adopts 4 digit counters with fsk signal rising edge and trailing edge.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107112999A (en) * | 2014-12-31 | 2017-08-29 | 德克萨斯仪器股份有限公司 | Frequency synthesizer output cycle rate counter including ring encoder |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483193A (en) * | 1995-03-24 | 1996-01-09 | Ford Motor Company | Circuit for demodulating FSK signals |
| CN1313974A (en) * | 1998-06-22 | 2001-09-19 | 乔治·伦纳德·鲍威尔 | Anti-collision tag apparatus and system |
| CN101432758A (en) * | 2006-03-03 | 2009-05-13 | 威夫特伦德科技有限公司 | Apparatus and methods for electromagnetic identification |
-
2013
- 2013-06-25 CN CN201310257643.XA patent/CN103338174B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483193A (en) * | 1995-03-24 | 1996-01-09 | Ford Motor Company | Circuit for demodulating FSK signals |
| CN1313974A (en) * | 1998-06-22 | 2001-09-19 | 乔治·伦纳德·鲍威尔 | Anti-collision tag apparatus and system |
| CN101432758A (en) * | 2006-03-03 | 2009-05-13 | 威夫特伦德科技有限公司 | Apparatus and methods for electromagnetic identification |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107112999A (en) * | 2014-12-31 | 2017-08-29 | 德克萨斯仪器股份有限公司 | Frequency synthesizer output cycle rate counter including ring encoder |
| CN107112999B (en) * | 2014-12-31 | 2020-09-04 | 德克萨斯仪器股份有限公司 | Frequency synthesizer output period counter including a ring encoder |
| US11162986B2 (en) | 2014-12-31 | 2021-11-02 | Texas Instruments Incorporated | Frequency synthesizer output cycle counter including ring encoder |
| US11486916B2 (en) | 2014-12-31 | 2022-11-01 | Texas Instmments Incorporated | Frequency synthesizer output cycle counter including ring encoder |
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