CN103248230A - Switching regulator - Google Patents
Switching regulator Download PDFInfo
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- CN103248230A CN103248230A CN2012105929373A CN201210592937A CN103248230A CN 103248230 A CN103248230 A CN 103248230A CN 2012105929373 A CN2012105929373 A CN 2012105929373A CN 201210592937 A CN201210592937 A CN 201210592937A CN 103248230 A CN103248230 A CN 103248230A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
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- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A switching regulator controls an output transistor supplying current to an inductor and generates a second supply voltage from a first supply voltage. The switching regulator has: an error amplifier amplifying a difference between the second supply voltage and a reference voltage; a current sense amplifier converting an inductor current into voltage; a current comparator comparing an output voltages of the error amplifier and the current sense amplifier, so as to output a trigger signal when the second supply voltage decreases; a pulse generation circuit generating a control pulse to drive the first output transistor in response to the trigger signal; and a sleep control circuit, during a sleep period by a sleep signal supplied from a load side, suspending operation of the current sense amplifier or the pulse generation circuit, and tentatively resuming the suspended operation in response to the trigger signal, and thereafter suspending the operation again.
Description
Technical field
Embodiment relates to a kind of switching regulator
Background technology
Switching regulator generates second supply power voltage that will be provided for load circuit from first supply power voltage of input, and provides the voltage that generates to it.Switching regulator is intended to, and the heavy duty condition of high-current consumption and consuming under both situations of light-load conditions of little electric current in load circuit maintains second supply power voltage voltage of appointment.
On the other hand, according to the demand of the low-power consumption in the switching regulator that is installed on the mobile device for example etc., preferably suppress the power consumption in the internal circuit of switching regulator, in order to improve power conversion efficiency.
In the power loss of switching regulator, comprise multiple loss.For example, these losses comprise the gate charge loss of inductor current loss and inductor magnetic hysteresis loss and switching losses, conduction loss and output driving transistors.In order to improve power conversion efficiency, need as much as possible these losses to be reduced to minimum.
Switching regulator is disclosed in following patent documentation.According to these patent documentations, carry out following control to reduce power consumption: when the load in the load circuit is light, switch to by the alternate aerodrome effect transistor (FET) with little grid width and drive, and according to the loading level in the load circuit, for example when diminishing, load reduces the number of output driving transistors, so that the suppressor grid loss of charge.
These patent documentations are No. the 5731731st, United States Patent (USP), No. the 5969514th, United States Patent (USP).
Like this, in traditional switching regulator, by monitoring output current etc., when detecting light-load conditions, switch the output driving transistors or reduce its number.Yet, the overwhelming majority of the control circuit of incorporating into must remain on mode of operation in case for the flip-flop of the loading condition of load circuit ready.Therefore, in traditional switching regulator, the raising of efficient is not enough.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of switching regulator with power efficiency of raising.
First aspect according to embodiment, a kind of switching regulator, its control provides first output transistor of electric current and generates second supply power voltage from first supply power voltage to inductor, this switching regulator has: error amplifier is configured to amplify poor between second supply power voltage and first reference voltage; The current sense amplifier, the inductor current that is configured to flow through inductor converts voltage to; Current comparator is configured to the output voltage of error amplifier and the output voltage of current sense amplifier are compared, in order to export triggering signal when second supply power voltage reduces; Pulse generation circuit is configured to generate control impuls to drive first output transistor in response to triggering signal; And dormancy control circuit, the sleep signal that provides by from the load-side that is provided second supply power voltage is provided, operation at dormancy period pause current sense amplifier or pulse generation circuit, and in response to triggering signal, the operation that is suspended of temporary transient intermittent current sensing amplifier or pulse generation circuit, and pausing operation again subsequently, wherein in the dormancy period, pulse generation circuit generates control impuls after through the stipulated time after triggering signal occurs.
According to first aspect, improved the power efficiency of switching regulator.
Description of drawings
Fig. 1 is the diagram of the configuration of diagram switching regulator.
Fig. 2 is the oscillogram of the operation of the switching regulator shown in the pictorial image 1.
Fig. 3 is the oscillogram of the operation of the switching regulator shown in the pictorial image 1.
Fig. 4 is the allocation plan according to the switching regulator of first embodiment.
Fig. 5 is the allocation plan of dormancy control circuit 30.
Fig. 6 is the allocation plan of timing circuit 32.
Fig. 7 is the sequential chart of the operation of diagram switching regulator.
Fig. 8 is the allocation plan according to the switching regulator of second embodiment.
Fig. 9 is the sequential chart of the operation of the switching regulator shown in the pictorial image 8.
Figure 10 is the allocation plan according to the switching regulator of the 3rd embodiment.
Figure 11 illustrates the circuit diagram of current comparator 14-1,14-2 respectively.
Figure 12 is the sequential chart of the operation of the switching regulator shown in diagram Figure 10.
Figure 13 is the allocation plan according to the switching regulator of the 4th embodiment.
Figure 14 is the allocation plan according to the switching regulator of the 5th embodiment.
Embodiment
Fig. 1 is the diagram of the configuration of diagram switching regulator.Switching regulator is the circuit that generates the second supply power voltage VOUT that will offer load circuit 2 from the first supply power voltage VIN that imports it.In this configuration, switching regulator comprise be arranged on the first supply power voltage VIN and the VSS(reference voltage) between the first output transistor QH and the second output transistor QL.This switching regulator further comprises: be arranged on the connected node VL of above-mentioned output transistor and inductor (coil) LOUT between the lead-out terminal (node of the second supply power voltage VOUT); Be arranged on capacitor (capacitor, the condenser) COUT at lead-out terminal place; And the control circuit 1 of controlling to drive output transistor QH, QL.
Therefore, according to present embodiment, switching regulator only is illustrated among Fig. 1 the control unit 1 by dotted line in some cases, perhaps in other cases, expression comprises control unit 1, the first and second output transistor QH, QL are for it generate to drive the drive circuit 20,22 and the configuration of inductor LOUT of signal DRVH and DRVL.Under the former situation, control unit 1 is designated as switching regulator 1.
In response to the triggering signal SET from current comparator 14 outputs, Drive and Control Circuit 18 is based on the pulse from 16 outputs of pulse generative circuit, and output driving pulse DRVH, DRVL are to control output transistor QH, QL by drive circuit 20,22.In brief, pulse generative circuit 16 and Drive and Control Circuit 18 have constituted the pulse generation circuit that is used for generating the control impuls that drives output transistor.
Two output transistor QH, QL repeat conducting and not conducting in response to above-mentioned driving pulse DRVH, DRVL, and use the smoothing function of the lc circuit that is constituted by inductor LOUT and capacitor COUT, the output current IO UT of substantial constant is provided to load circuit 2.In addition, the second supply power voltage VOUT that offers load circuit 2 is maintained at the required expectation voltage level of load circuit 2.
Fig. 2 is the oscillogram of the operation of the switching regulator shown in the pictorial image 1.Fig. 2 illustrates when load circuit 2 and is in light-load conditions and because the high internal resistance of load circuit makes the consumed current IOUT of institute hour operation waveform.At first, the second supply power voltage VOUT is arrived error amplifier 10 by negative feedback, if and the second supply power voltage VOUT reduces with respect to reference voltage VREF, then output voltage EOUT increases, and it is opposite, if when the second supply power voltage VOUT increased near reference voltage VREF, output voltage EOUT reduced.Do not providing under the state of electric current from the first output transistor QH, inductor current IL is zero, and the output voltage CS of current sense amplifier 12 is the voltage corresponding with zero current.Under above-mentioned state, if because the current drain in the load circuit 2 causes the electric charge among the output capacitor COUT to reduce, thereby the second supply power voltage VOUT reduces, and then the output voltage EOUT of error amplifier 10 increases.
When output voltage EOUT increase reaches output voltage CS, current comparator 14 output triggering signal SET.In response to triggering signal SET, pulse generative circuit 16 generates has the control impuls of predetermined pulse width (for example, isopulse width).Subsequently, the first driving pulse DRVH(H level pulse that Drive and Control Circuit 18 output pulse widths are corresponding with its control impuls), in order to make the first transistor QH conducting.By the conducting of the first transistor QH, the voltage of connected node VL is increased to the first supply power voltage VIN, and the inductor current IL of inductor LOUT also increases.
The Drive and Control Circuit 18 outputs second driving pulse DRVL(H level pulse) replaces the first driving pulse DRVH, in order to make the first output transistor not conducting of QH and the second output transistor QL conducting.By this, provide electric current to suspend by the first output transistor QH to inductor LOUT from the first supply power voltage VIN, yet, because the second output transistor QL conducting, so the forward current on the direction of arrow shown in Fig. 1 continues to flow through inductor LOUT because of the electromagnetic energy of wherein storage.Yet inductor current IL reduces gradually.
Zero-crossing comparator 24 is exported zero passage detection signal ZC when detecting inductor current IL vanishing.In response to this, Drive and Control Circuit 18 second driving pulse DRVL are set to the L level.By this, prevent that inductor current IL from flowing to rightabout, and the electric charge among the output capacitor COUT is discarded into ground VSS by output transistor QL.
In Fig. 2, during the time period from triggering signal SET to zero passage detection signal ZC (driving period DRIVE), the electric current of carrying out at the second supply power voltage VOUT provides operation.Provide by this electric current, output voltage VO UT increases and the output voltage EOUT of error amplifier 10 reduces, and has therefore produced the empty lots IDLE that electric current is not provided therebetween.
Like this, under light-load conditions, repeat to drive period DRIVE and empty lots IDLE, and relatively little electric current I OUT is provided for load circuit 2, and the second supply power voltage VOUT is maintained at the voltage level of expectation.
Fig. 3 is the oscillogram of the operation of the switching regulator shown in the pictorial image 1.Be different from Fig. 2, Fig. 3 illustrates the operation waveform when load circuit 2 is in than the heavy duty condition, and this moment is because the low internal resistance of load circuit has produced the state that consumes big output current IO UT.In Fig. 3, for current sense amplifier CS, show the solid line of indication heavy duty condition and the dotted line of indication light-load conditions.
Under the heavy duty condition, in load circuit 2, there is big current drain, and the decline immediately after carrying out current drives of the voltage of the second supply power voltage VOUT, in order to produce the high output voltage EOUT of error amplifier 10 immediately.Therefore, the electric current among the driving period DRIVE shown in Fig. 2 provides for operation under the situation of empty lots IDLE and repeats.Because the big current drain of the load circuit 2 under the heavy duty condition, the inductor current IL1 under the light-load conditions (dotted line), the inductor current IL2 under the heavy duty condition is maintained at higher level.
In the switching regulator shown in Fig. 1, owing to comprise the LC resonant circuit of inductor LOUT and capacitor COUT, transfer function comprises duopole, makes phase place shift to an earlier date 360 °.The phase place supplementary circuitry that is used for the phase place that the compensation duopole produces is complicated and is difficult to realize.Therefore, make inductor current IL to the input side feedback of control unit 1 by current sense amplifier 12 is set, the resonance point that makes the LC resonant circuit is sightless.As a result, transfer function only comprises by the first order pole of the CR circuit of the internal resistance configuration of capacitor COUT and load circuit 2, makes and can simplify the phase place supplementary circuitry.
The aforementioned switches pressurizer has the problem of power efficiency difference under light-load conditions.More specifically, be unexpected load variations, when particularly the unexpected increase of load is prepared, even when load circuit 2 is in light-load conditions, switching regulator still is configured to provide the standard bias current to error amplifier 10, current sense amplifier 12 and current comparator 14, in order to realize the quick response at the flip-flop of load.Similarly, the standard bias current is provided for a part of circuit in the pulse generative circuit 16.Therefore, under light-load conditions, because bias current is continued to offer the foregoing circuit of preparing for the flip-flop of load, therefore the bias current similar to the situation of heavy duty condition is consumed, and reduces although drive the frequency of period DRIVE.By this, undesirably reduced overall power efficient.
[first embodiment]
Fig. 4 is the allocation plan according to the switching regulator of first embodiment.When the control unit (both are designated as load system together) from the load circuit 2 that is provided the second supply power voltage VOUT or control load circuit 2 receive sleep signal SLP#(wherein # represent to work as the signal of paying close attention to when being in the L level, produced active state) time, wherein this sleep signal has been guaranteed little load current and the flip-flop of load current can not have been taken place, and switching regulator stops or suspending the operation of current sense amplifier 12 and the pulse generative circuit 16 of production burst CP is suspended (perhaps making the bias current minimum).Here, error amplifier 10 and current comparator 14 are maintained at mode of operation, and in addition, when detecting the decline of the second supply power voltage VOUT that offers load circuit 2, the current sense amplifier 12 that operation has been suspended and pulse generative circuit 16 begin to continue operation, provide electric current in order to drive output transistor QH, QL and begin to the second supply power voltage VOUT side.When finishing in the driving period, the operation of current sense amplifier 12 and pulse generative circuit 16 suspends again.Carry out this operation suspension by for example blocking bias current.
In order to make current sense amplifier 12 and pulse generative circuit 16 begin to continue operation, need official hour.Therefore, in case the operation suspension that makes as indicated above, the unexpected load variations of response fast.Yet, when receiving from the load system side joint when guaranteeing not take place sleep signal SLP# that unexpected load changes, therefore this quick response at load variations may be unnecessary, and current sense amplifier 12 as indicated above and the operation suspension of pulse generative circuit 16 can not have problems.
Except the configuration shown in Fig. 1, the switching regulator shown in Fig. 4 further comprises: dormancy control circuit 30, be used in response to the sleep signal SLP# that provides from load system, and generate dormancy enable signal SLP_EN#_A, SLP_EN#_B; And timing circuit 32, be used for making triggering signal SET to postpone official hour, to provide delayed triggering signal SET' to pulse generative circuit 16.Under standard operation state, based on dormancy enable signal SLP_EN#_A, timing circuit 32 offers pulse generative circuit 16 with triggering signal SET under the situation that triggering signal SET is postponed.When becoming dormancy during the period by receiving sleep signal SLP#, timing circuit 32 postpones triggering signal SET.
When receiving sleep signal LSP#, in response to zero passage detection signal ZC, dormancy control circuit 30 makes dormancy enable signal SLP_EN#A and SLP_EN#B active (L level).The result, by means of the SLP_EN#_A that is in the L level, dormancy control circuit 30 allows timing circuit 32 to carry out the delay operation, and by means of the SLP_EN#_B that is in the L level, dormancy control circuit 30 allows current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 to suspend their operation (perhaps suppressing bias current).More specifically, the bias current of dormancy control circuit 30 cut-off current sensing amplifiers 12, pulse generative circuit 16 and zero-crossing comparator 24 is to forbid their operation.
Under above-mentioned state, when error amplifier 10 and current comparator 14 generate triggering signal SET along with the decline of output voltage VO UT, dormancy control circuit 30 makes dormancy enable signal SLP_EN#_B be in non-active state (H level), so that the current sense amplifier 12 that start-up function has been suspended, pulse generative circuit 16 and zero-crossing comparator 24.Owing to will consume the stipulated time with the starting foregoing circuit, timing circuit 32 postpones the triggering signal SET corresponding to the above-mentioned time, to the delayed triggering signal SET' of pulse generative circuit 16 outputs.Before delayed triggering signal SET' was provided, the starting that pulse generative circuit 16, current sense amplifier 12 and zero-crossing comparator 24 have been finished them to be becoming mode of operation, and carried out the operation that electric current is provided from inductor LOUT accordingly.
Fig. 5 is the allocation plan of dormancy control circuit 30.Dormancy control circuit 30 comprise trigger 301,303 and or (OR) door 302.
Fig. 6 is the allocation plan of timing circuit 32.When dormancy enable signal SLP_EN#_A enlivens (L level), timing circuit 32 is exported delayed triggering signal SET' by triggering signal SET is postponed, and when dormancy enable signal SLP_EN#_A inactive (H level), timing circuit 32 does not make triggering signal SET postpone.
Fig. 7 is the sequential chart of the operation of diagram switching regulator.With reference to Fig. 7, explain the operation of switching regulator together with the operation of dormancy control circuit.
At first, when sleep signal SLP# inactive (H level), because SET=L and ZC=L, trigger 301 is reset, make its anti-phase output XQ be set to the H level, and trigger 303 is cleared, and makes its anti-phase output XQ be set to the H level, makes dormancy enable signal SLP_EN#_A, SLP_EN#_B both all inactive (H level).At time t1, when sleep signal SLP# became active (L level), the Reset Status of trigger 301 was cancelled, and the cleared condition of trigger 303 also is cancelled.Yet the state of two dormancy enable signals is constant.
Therefore, even sleep signal SLP# becomes active (L level), the bias current of current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 can not blocked immediately, makes standard operation continue.
In Fig. 7, after time t1 in response to triggering signal SET, export triggering signal SET' without delay, and pulse generative circuit 16 production burst CP, and Drive and Control Circuit generates driving pulse DRVH, DRVL successively, in order to make output transistor QH, QL conducting successively, thereby and carry out electric current by inductor LOUT operation is provided.In addition, zero-crossing comparator 24 detects inductor current IL and becomes inverse direction from direction, and output zero passage detection signal ZC.Like this, carried out the driving operation DRIVE that explains among Fig. 1,2.
Next, at time t2, when inductor current IL vanishing and zero passage detection signal ZC became H level (ZC=H), the dormancy period corresponding with sleep signal SLP# began.More specifically, the trigger 301 in the dormancy control circuit 30 is set up, and makes its output become Q=H and XQ=L respectively.Synchronous with above-mentioned Q=H, trigger 303 is obtained H level data D, makes its output become XQ=L.By this, dormancy enable signal SLP_EN#_A, SLP_EN#_B both all come to life (L level).This has blocked the bias current in current sense amplifier 12, pulse generative circuit 16 and the zero-crossing comparator 24, in order to make their operation suspension, and therefore, timing circuit 32 becomes the delay mode of operation.By this, the power consumption that the bias current in current sense amplifier 12, pulse generative circuit 16 and the zero-crossing comparator 24 causes is eliminated, and empty lots IDLE begins.During the operation suspension of current sense amplifier 12, its output voltage CS is zero.
During empty lots IDLE, at time t3, when the current potential of the second supply power voltage VOUT descends owing to the current drain in the load circuit 2, the output voltage EOUT of error amplifier 10 increases, and when it surpasses the output voltage CS of current sense amplifier 12, current comparator 14 output triggering signal SET.In response to this triggering signal SET(=H level), the trigger 301 in the dormancy control circuit 30 is reset, and makes output become XQ=H and Q=L respectively, and dormancy enable signal SLP_EN#_B becomes inactive (H level).Here, another dormancy enable signal SLP_EN#_A keeps active (L level).
In response to the disabled state (H level) of dormancy enable signal SLP_EN#_B at time t3, the bias current of current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 continues, and makes their start-up function that operates in continue afterwards.Here, in above-mentioned start-up function, will consume official hour.On the other hand, timing circuit 32 postpones triggering signal SET, and at time t4, delayed triggering signal SET' is outputed to pulse generative circuit 16.At this moment, the start-up function of pulse generative circuit 16 grades is finished.As a result, time t4 and become afterwards and drive period DRIVE to make output transistor QH, QL conducting successively, making provides electric current to the second supply power voltage VOUT.As a result, the current potential of the second supply power voltage VOUT increases, and the output voltage EOUT of error amplifier 10 reduces.
At time t5, when zero passage detection signal ZC became H level (ZC=H), t2 was similar to the time, and the trigger 301 in the dormancy control circuit 30 is set up, and made output become XQ=L so that dormancy enable signal SLP_EN#_B active (L level).In response to this, the bias current of current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 is blocked and their operation suspension again, and therefore empty lots IDLE begins.
By the way, be at sleep signal SLP# during the dormancy period of active state (L level), drive period DRIVE and empty lots IDLE and alternately repeat.Especially, because the bias current of current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 is blocked, therefore can suppress power loss in empty lots IDLE.
Subsequently, at time t6, when sleep signal SLP# became inactive (H level), each trigger in the dormancy control circuit 30 was reset or zero clearing, so that dormancy enable signal SLP_EN#_A, SLP_EN#_B both inactive (H level) make on-off controller begin standard operation.Under this standard operation state, because current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 are in mode of operation, so on-off controller responsive load variation fast, make it possible to tackle unexpected load and change.
In Fig. 4, the LSI chip 1 of switching regulator is not incorporated drive circuit 20,22 into, output transistor QH, QL and inductor LOUT.Yet, can become and incorporate that it is all or part of into.
[second embodiment]
Fig. 8 is the allocation plan according to the switching regulator of second embodiment.Fig. 9 is the sequential chart of the operation of the switching regulator shown in the pictorial image 8.In Fig. 8; be with the difference in the configuration of first embodiment shown in Fig. 4; setting have trigger 161 and timer circuit 162 turn-on time timer circuit as pulse generative circuit 16; and in addition, current foldback circuit 26 and overvoltage and under-voltage protecting circuit 28 are set.Other configurations are identical with the configuration shown in Fig. 4.Here, the LSI chip 1 in the switching regulator is omitted in Fig. 8.
In pulse generative circuit 16, in response to triggering signal SET or SET' trigger 161 is set, be set to the H level in order to export Q.From the rising edge of output Q through the constant time after, timer circuit 162 outputs are set to the H level, and in response to this, trigger 161 is reset, and make output Q be set to the L level.Therefore, the pulse duration W of the pulse CP among the output Q of trigger 161 becomes constant.The Drive and Control Circuit 18 drive pulse signal DRVH that the production burst width is identical with pulse CP subsequently is in order to make the first output transistor QH conducting equal the time period of pulse duration W.In addition, after drive pulse signal DRVH is set to the L level, Drive and Control Circuit 18 another drive pulse signal of output DRVL(H level) so that the second output transistor QL conducting.Subsequently, when flowing through the inductor current IL vanishing of inductor LOUT from ground VCC by the second output transistor QL on direction, Drive and Control Circuit 18 is set to the L level in response to the H level drive pulse signal DRVL from the zero passage detection signal ZC of zero-crossing comparator 24 outputs.
Like this, in the switching regulator according to second embodiment, be appreciated that the pulse duration of the driving pulse DRVH of the first output transistor QH has steady state value W, and according to the loading condition of load circuit, provide betwixt and carry out PFM in driving period of electric current and control to change frequency.
When the output voltage CS of current sense amplifier 12 surpassed permission, current foldback circuit 26 allowed Drive and Control Circuit 18 drive pulse signal DRVH, DRVL to be set to the L level, in order to suspend the driving operation of output transistor QH, QL.By this, prevented that too much electric current from flowing in inductor LOUT.This exemplary cases of crossing multiple current is the second supply power voltage VOUT and ground short circuit in load circuit 2.In this case, current foldback circuit 26 has been avoided the too much electric current among load circuit 2 and the inductor LOUT.
Excessively be increased to more than the higher limit or excessively be reduced to lower limit when following detecting voltage level by the second supply power voltage COUT of feedback control loop FB feedback; overvoltage and under-voltage protecting circuit 28 allow Drive and Control Circuit 18 drive pulse signal DRVH, DRVL to be set to the L level, in order to suspend the driving operation of output transistor QH, QL.By this, the second supply power voltage VOUT is maintained in the voltage range between higher limit and the lower limit.
According to present embodiment, when dormancy enable signal SLP_EN#_A became active (L level), current foldback circuit 26 and overvoltage and under-voltage protecting circuit 28 were by operating to prevent current drain in dormancy period pause.Because these circuit 26, the 28th, the protective circuit that only needs in accident is saturated therefore especially, when from the sleep signal SLP# active (L level) of load system side, is little in necessity of dormancy period manipulate.Therefore, to suppress the current drain during the dormancy period, can contribution be arranged by pausing operation to improving power efficiency.As an alternative, can also be only in the operation of empty lots pause circuit 26,28, wherein dormancy enable signal SLP_EN#_B is (the L level) that enlivens during the dormancy period.
Sequential chart shown in Fig. 9 illustrates the operation during dormancy period when sleep signal SLP# active (L level).Similar to the description of front, when the second supply power voltage VOUT that passes through to descend during the dormancy period generates triggering signal SET, dormancy enable signal SLP_EN#_B by unshowned inactive (H level), the bias current of current sense amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 continues to carry out start-up function, and therefore the operation of these circuit continues.In addition, in response to the delayed triggering signal SET' in regulation input after time of delay, pulse generative circuit 16 output devices have the pulse CP of constant pulse duration W.The driving control unit 18 drive pulse signal DRVH that output pulse width is identical with pulse CP subsequently is so that the first output transistor QH conducting.Subsequently, after making the first not conducting of output transistor QH, Drive and Control Circuit 18 output drive pulse signal DRVL are so that the second output transistor QL conducting, and in addition, in response to zero passage detection signal ZC, drive pulse signal DRVL is set to the L level subsequently, in order to make the second not conducting of output transistor QL.
D time of delay shown in Fig. 9 is set to larger than the required time of starting current sensing amplifier 12, pulse generative circuit 16 and zero-crossing comparator 24 and comprises this time.In addition, pulse duration W is the pulse duration of pulse CP and driving pulse DRVH, and it is constant.
[the 3rd embodiment]
Figure 10 is the allocation plan according to the switching regulator of the 3rd embodiment.In Figure 10, the LSI chip 1 of switching regulator is omitted.In Figure 10, the difference with Fig. 4 in configuration is that current comparator comprises two current comparator 14-1,14-2.The first current comparator 14-1 can respond the circuit that input changes fast, and the second current comparator 14-2 is that response speed is than the slow circuit of the first current comparator 14-1.
Figure 11 illustrates the circuit diagram of current comparator 14-1,14-2 respectively.These two circuit have identical configuration, and each circuit comprises: PMOS transistor P1, P2, and it compares output voltage EOUT and CS; PMOS transistor P3, P4, it is as the load of PMOS transistor P1, P2 and connect; And output PMOS transistor P5, its grid is connected to the drain terminal of PMOS transistor P2.In addition, each current comparator comprises: bias current sources IREF; PMOS transistor P6, P7, P8, it is configured for sending the current mirroring circuit of the bias current of self-bias current source IREF; And secondary inverter INV1, INV2, it is arranged on outlet side.
The electric current of the bias current sources IREF1 of the first current comparator 14-1 of fast-response has for example produced the electric current than big ten times of the bias current sources IREF2 of the second current comparator 14-2 of slow-response.Although the first current comparator 14-1 because bigger bias current has produced bigger current drain, can export triggering signal SET in response to the variation of input EOUT and CS fast.Moreover each the PMOS transistor that constitutes the first current comparator 14-1 can have than the little transistor size of each PMOS transistor that constitutes the second current comparator 14-2, so that can be with higher speed operation.
Return with reference to Figure 10, the output of the first and second current comparator 14-1,14-2 by or door 34 be output to timing circuit 32, as triggering signal SET.In the dormancy period, when dormancy enable signal SLP_EN#_A became active (L level), the bias current sources IREF with first current comparator 14-1 of fast-response and big current drain was blocked, and made its operation suspension.As a result, during the dormancy period, only the second current comparator 14-2 of slow-response is by relatively carrying out detection with the output EOUT of error amplifier 10 and the output CS of current sense amplifier 12.
Figure 12 is the sequential chart of the operation of the switching regulator shown in diagram Figure 10.Be with the difference of Fig. 7, time t3 in Fig. 7, when error amplifier output EOUT surpasses current sense amplifier output CS, current comparator responds fast to export triggering signal SET basically simultaneously, and in Figure 12, because the current comparator 14-2 of slow-response operates in dormancy period SLEEP, so time t3-1 departs from time t3-2.In other words, error amplifier output EOUT surpasses current sense amplifier output CS at time t3-1, yet the current comparator 14-2 of slow-response is at time t3-2 output triggering signal SET.Generate triggering signal SET operation afterwards with identical shown in Fig. 7.Therefore, the time period from time t3-2 to time t4 is corresponding to the starting institute of the circuit that has been suspended of the operation time with consumption.
According to above-mentioned the 3rd embodiment and since have fast-response and big current drain the first current comparator 14-1 operate in dormancy period pause, therefore improved the power efficiency under the underload.In addition, can also only suspend its operation at the second current comparator 14-2 of dormancy period SLEEP manipulate slow-response and in other periods, make the first current comparator 14-1 of fast-response operate.
[the 4th embodiment]
Figure 13 is the allocation plan according to the switching regulator of the 4th embodiment.In the configuration of this switching regulator, be with the difference of the configuration shown in Fig. 4, except output transistor QH, QL with wide grid width and high driving ability, as output transistor, output transistor QHd, QLd with narrower grid width and low driving force are provided, and have been used for to output transistor QHd, the QLd output driving pulse DRVHD with narrow grid width, buffer 20d, the 22d of DRVLD.Other configurations are identical with Fig. 4.
During the dormancy period, dormancy enable signal SLP_EN#_A is (the L level) that enlivens, thereby drive circuit 20,22 suspends their operation.Therefore, do not export driving pulse DRVH, DRVL, and therefore do not carry out the driving operation of output transistor QH, QL.Replace as it, output transistor QHd, the QLd with narrow grid width carries out and drives operation.
In order to drive output transistor QH, the QL with wide grid width, driving pulse DRVH, DRVL must be provided for its gate electrode so that gate electrode voltage height.This needs a large amount of gate charges, follows big power consumption, and this is designated as the gate charge loss.Therefore, according to the 4th embodiment, owing to during the dormancy period, guarantee not have the flip-flop of load-side, therefore output transistor QHd, the QLd with narrow grid width carried out and drive control, and to the driving operation suspension of output transistor QH, QL with wide grid width, and therefore, during the dormancy period, suppressed power consumption.
[the 5th embodiment]
Figure 14 is the allocation plan according to the switching regulator of the 5th embodiment.In the configuration of this switching regulator, be that with the difference of Fig. 4 the pulse generative circuit is not provided, and by oscillator 36 is provided, the output of this oscillator is imported into Drive and Control Circuit 18.In Fig. 8, switching regulator uses pulse frequency modulated (PFM) to provide electric current to the second supply power voltage VOUT by having the drive pulse signal DRVH of fixed pulse width.On the other hand, in the example shown in Figure 14, Drive and Control Circuit 18 generates the drive pulse signal DRVH with the pulse duration that obtains by pulse width modulation (PWM).Drive and Control Circuit 18 is incorporated the pwm circuit of the running clock that uses oscillator 36 into.
Like this, in the switching regulator of carrying out PWM control, the bias current of current sense amplifier 12 and zero-crossing comparator 24 also blocked by the dormancy enable signal SLP_EN#_B that enlivens (L level) during the dormancy period, made their operation suspension.In addition, will also suspend for the operation of the amplifier (not shown) of the Drive and Control Circuit 18 of PWM control.Therefore, can under underload, improve power efficiency.
In the switching regulator shown in Figure 14, do not provide pulse generative circuit 16, yet Drive and Control Circuit 18 have the function of pulse generation circuit and drive pulse signal DRVH, DRVL corresponding to control impuls.
Described as mentioned, guarantee not take place the sleep signal that unexpected load changes in response to providing from the load system side, according to the switching regulator of each embodiment beyond the time that load circuit side needs electric current provides the time chien shih main control circuit operation suspension, and only keep mode of operation in the minimum circuit (error amplifier 10 and current comparator 14).When detecting load circuit and need electric current to provide, switching regulator provides electric current by the circuit that starting suspends.Therefore, can improve power efficiency under the light-load conditions.
Claims (13)
1. switching regulator, its control provides first output transistor of electric current and generates second supply power voltage from first supply power voltage to inductor, and described switching regulator has:
Error amplifier is configured to amplify poor between described second supply power voltage and first reference voltage;
The current sense amplifier, the inductor current that is configured to flow through described inductor converts voltage to;
Current comparator is configured to the output voltage of described error amplifier and the output voltage of described current sense amplifier are compared, in order to export triggering signal when described second supply power voltage reduces;
Pulse generation circuit is configured to generate control impuls to drive described first output transistor in response to described triggering signal; And
The dormancy control circuit, the sleep signal that provides by from the load-side that is provided described second supply power voltage is provided, operation at the described current sense amplifier of dormancy period pause or described pulse generation circuit, and in response to described triggering signal, the temporary transient operation that is suspended that continues described current sense amplifier or described pulse generation circuit, and pausing operation again subsequently
Wherein in the described dormancy period, described pulse generation circuit generates described control impuls after through the stipulated time after described triggering signal occurs.
2. switching regulator according to claim 1,
Wherein, described pulse generation circuit comprises the pulse generative circuit, and described pulse generative circuit is configured in response to described triggering signal, generates to have the ono shot pulse of the isopulse width of control impuls as described.
3. switching regulator according to claim 2,
Wherein, described pulse generative circuit comprises: trigger, and it is configured in response to described triggering signal, the forward edge that becomes first state and export described control impuls; And timer circuit, it is configured to make described forward along delay, the reverse edge that wherein said trigger becomes second state and exports described control impuls by delayed forward edge, and
Wherein, during the described dormancy period, when described pulse generation circuit suspended and continue operation, described timer circuit suspended and continues operation respectively.
4. switching regulator according to claim 1,
Wherein, described current sense amplifier becomes mode of operation when bias current is provided, and becomes halted state when described bias current is blocked or suppresses.
5. switching regulator according to claim 1,
Wherein, described pulse generation circuit comprises:
Drive and Control Circuit, be configured to control the described the first transistor and the transistor seconds that are arranged between described first supply power voltage and second reference voltage, make by making the described first output transistor conducting, inductor current flows through described inductor in direction, and subsequently by making the described first not conducting of output transistor and making the described second output transistor conducting simultaneously, described inductor current continues to flow through described inductor in described direction, and wherein said inductor is arranged on interconnecting between node and the lead-out terminal of described the first transistor and described transistor seconds; And further comprise:
Zero-crossing comparator is configured to detect described inductor current and switches to inverse direction from described direction, and
Wherein, in response to the detection output of described zero-crossing comparator, described Drive and Control Circuit switches to not conducting with described second output transistor from conducting, and
Wherein, in response to the detection of described zero-crossing comparator output, the operation that described dormancy control circuit makes described current sense amplifier or described pulse generation circuit from temporarily again the continuation state suspend.
6. switching regulator according to claim 1,
Wherein, described dormancy control circuit is controlled, make described current comparator operate with first response speed in the time beyond the described dormancy period, and during the described dormancy period, operate with second response speed that is lower than described first response speed.
7. switching regulator according to claim 1 further comprises:
The first little output transistor, be configured to comprise size than described first output transistor little and transistor that be arranged in parallel with described first output transistor; And
Drive and Control Circuit, drive described first output transistor in described control impuls the time response that is configured to beyond the described dormancy period, and drive described first output transistor and drive the described first little output transistor in response to described control impuls in described dormancy period pause.
8. switching regulator according to claim 1 further comprises:
Current foldback circuit is configured to when the output voltage of described current sense amplifier surpasses the first protection voltage, is no more than the electric current corresponding with the described first protection voltage by making the described first not conducting of output transistor control described inductor current,
Wherein said current foldback circuit is in the pause operation of described dormancy period.
9. switching regulator according to claim 1 further comprises:
Overvoltage and under-voltage protecting circuit; be configured to when described second supply power voltage departs from operating voltage range between the voltage of the second protection voltage and the 3rd protection that is higher than the described second protection voltage; do not depart from described operating voltage range by making the described first not conducting of output transistor control described second supply power voltage
Wherein said overvoltage and under-voltage protecting circuit are in the pause operation of described dormancy period.
10. switching regulator according to claim 1 further comprises:
Timing circuit is configured to make during the described dormancy period described triggering signal to postpone the described stipulated time and delayed triggering signal is offered described pulse generation circuit, and the time beyond the described dormancy period does not make described triggering signal postpone.
11. switching regulator, its control is arranged between first supply power voltage and the reference voltage and inductor is arranged on first output transistor and second output transistor that interconnects the node place, to generate second supply power voltage from described first supply power voltage, described switching regulator comprises:
Error amplifier is configured to amplify poor between described second supply power voltage and first reference voltage;
The current sense amplifier, the inductor current that is configured to flow through described inductor converts voltage to;
Current comparator is configured to the output voltage of described error amplifier and the output voltage of described current sense amplifier are compared, in order to export triggering signal when described second supply power voltage reduces;
Driving control unit is configured to generate first driving pulse driving described first output transistor in response to described triggering signal, and generates second driving pulse to drive described second output transistor after driving described first output transistor; And
The dormancy control circuit, the sleep signal that provides by from the load-side that is provided described second supply power voltage is provided, operation in the described current sense amplifier of dormancy period pause or described driving control unit, and the appearance in response to described triggering signal, the temporary transient operation that is suspended that continues described current sense amplifier or described driving control unit, and pausing operation again subsequently
Wherein in the described dormancy period, described driving control unit generates described first driving pulse after through the stipulated time after described triggering signal occurs.
12. switching regulator according to claim 11,
Wherein, described driving control unit comprises:
Pulse generation circuit, generate control impuls in described triggering signal the time response that is configured to beyond the described dormancy period, and generate described control impuls after through the stipulated time in the described dormancy period after described triggering signal occurs; And
Drive and Control Circuit is configured to generate described first driving pulse and described second driving pulse according to described control impuls, and
Wherein, during the described dormancy period, the described pulse generation circuit in the described driving control unit suspends and continues operation.
13. switching regulator according to claim 11,
Wherein, described driving control unit is during the described dormancy period, generate described first driving pulse, the pulse duration of described first driving pulse is modulated after through the stipulated time after described triggering signal occurs, and the time beyond the described dormancy period, under the situation of described stipulated time, in response to described triggering signal, modulated first driving pulse of production burst width.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012025669A JP5942455B2 (en) | 2012-02-09 | 2012-02-09 | Switching regulator |
| JP2012-025669 | 2012-02-09 |
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| Publication Number | Publication Date |
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| CN103248230A true CN103248230A (en) | 2013-08-14 |
| CN103248230B CN103248230B (en) | 2016-12-28 |
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| CN201210592937.3A Active CN103248230B (en) | 2012-02-09 | 2012-12-31 | Switching regulator |
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|---|---|
| US (1) | US20130207625A1 (en) |
| JP (1) | JP5942455B2 (en) |
| CN (1) | CN103248230B (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP5942455B2 (en) | 2016-06-29 |
| JP2013162733A (en) | 2013-08-19 |
| CN103248230B (en) | 2016-12-28 |
| US20130207625A1 (en) | 2013-08-15 |
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