CN103176945B - FPGA is from reconfiguration device and method - Google Patents
FPGA is from reconfiguration device and method Download PDFInfo
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- CN103176945B CN103176945B CN201110439628.8A CN201110439628A CN103176945B CN 103176945 B CN103176945 B CN 103176945B CN 201110439628 A CN201110439628 A CN 201110439628A CN 103176945 B CN103176945 B CN 103176945B
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Abstract
The application relates to a kind of FPGA device from reconfiguration device and method, this device comprises the self-configuring circuit be arranged in FPGA device and the signal conditioning circuit being arranged on outside, self-configuring circuit comprises the first to the 3rd counter and testing circuit, first to the 3rd counter is for receiving same clock pulse signal to carry out timing, and when timing reaches preset value output low level signal, testing circuit detects the first to the 3rd counter, and whether one of them exports different from other two counters, and when difference being detected output low level signal, when detecting that exporting homogeneous phase exports the level signal identical with the first to the 3rd counter simultaneously, the output terminal connection signal modulate circuit of testing circuit, the low level signal that testing circuit exports transfers to and reshuffles pin by signal conditioning circuit, and control to reshuffle the pin maintenance low level time more than Preset Time.The present invention has that required external devices is few, structure is simple, take the few advantage of PCB resource.
Description
Technical field
The application relates to space apparatus engineering field, particularly relate to a kind of FPGA from reconfiguration device and method.
Background technology
Along with the development of spationautics and the demand of every field, increasing satellite and spacecraft come into operation.The function of spacecraft becomes increasingly complex in-orbit, this realizes more function with regard to needing complicated logic, extensive field programmable gate array (Field-ProgrammableGateArray, FPGA device) be more satisfactory device, particularly SRAM (StaticRandomAccessMemory, static RAM) type FPGA device has that scale is large, function is strong, can the advantage such as overprogram.At present, SRAM type FPGA device is widely used at commercial field.Owing to there being various particle in space environment, such as proton, electronics, α particle, heavy ion, gamma-rays etc., multiple single particle effect (SingleEventEffect will be there is in these particle bombardments to SRAM type FPGA device, SEE), such as single-particle inversion (SingleEventUpset, SEU), single event function interrupt (SingleEventFunctionalInterrupt, SEFI), total dose effect, locking single particle (SingleEventFunctionalLatchup, SEL), single event burnout (SingleEventBurnout, SEB), displacement damage, single-particle instantaneous disturbance (SingleEventTransient, SET) etc.These single particle effects directly affect the reliability of the function and space electronic device of FPGA device.Therefore, the application of SRAM type FPGA device in space flight is needed to carry out extra Design of Reinforcement, to strengthen the ability of its anti-single particle effect, guarantees reliability service.
Often from device level and design level, SRAM type FPGA device is reinforced to resist single particle effect.Device level carries out resistance to Radiation Hardened to device itself, mainly resists total dose effect and locking single particle etc., and the chip of resistance to Radiation Hardened that each large chip manufacturer can release some aerospace levels is available.Design level is then reinforced further by various design means, mainly resists single-particle inversion (SEU) and single event function interrupt (SEFI) etc.Carry out anti-single particle effect reinforcing from design angle to SRAM type FPGA device, two kinds of popular at present ways are:
1: triplication redundancy+timing is reshuffled: triplication redundancy backs up the user logic in FPGA device, and when ensureing that some backups make mistakes by majority voting device, still have correct output.Timing is reshuffled, by periodically reshuffling the incorrect integration eliminated single particle effect and cause completely to FPGA device.
2: triplication redundancy+timing heavily refreshes: triplication redundancy backs up the user logic in FPGA device, and when ensureing that some backups make mistakes by majority voting device, still have correct output.Timing heavily refreshes, by periodically completely heavily refreshing the incorrect integration corrected single particle effect and cause to the config memory of FPGA device inside.
Wherein, triplication redundancy+timing reshuffles project plan comparison simply, is suitable for the undemanding occasion of all kinds of requirement of real-time, has practical application at present in all kinds of spacecraft.The heavy refresh scheme of triplication redundancy+timing then designs more complicated, is suitable for strict to requirement of real-time and can not the occasion run of interrupt routine.
Reshuffle in scheme in triplication redundancy+timing, the way of current main flow adopts outside device to control timing to reshuffle, and triplication redundancy is then added in the program design of FPGA device by user.External devices can be single-chip microcomputer, watchdog circuit and Actel aerospace level anti-fuse FPGA device etc.This design proposal is except the FPGA device normally run, also need extra external devices, the PCB surface occupying hardware circuit like this amass, increase the complicacy of design and circuit board wiring difficulty, gain in weight and power consumption, thus cause the reliability of hardware design to reduce.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
A fundamental purpose of the present invention be to provide a kind of without the need to increasing outside reconfiguration circuitry, required external devices is few, structure simple, take the few FPGA device of PCB resource from reconfiguration device and method.
For achieving the above object, the invention provides a kind of FPGA device from reconfiguration device, comprise the self-configuring circuit be arranged in FPGA device and the signal conditioning circuit being arranged on FPGA device exterior, self-configuring circuit comprises the first to the 3rd counter and is connected to the testing circuit of the first to the 3rd counter, first to the 3rd counter is for receiving same clock pulse signal to carry out timing, and when timing reaches preset value output low level signal, otherwise output high level signal, for detecting the first to the 3rd counter, whether one of them exports different level signals from other two counters to testing circuit, and when difference being detected output low level signal, the level signal identical with the first to the 3rd counter is exported when detecting that the first to the 3rd counter exports identical level signal, the output terminal connection signal modulate circuit of testing circuit, what signal conditioning circuit was used for the low level signal that testing circuit exports to transfer to FPGA device reshuffles pin, and control to reshuffle the pin maintenance low level time more than Preset Time.
For realizing object of the present invention, present invention also offers a kind of FPGA device from method for reconfiguration, comprising:
Receive same pulse signal by three counters be arranged in FPGA device and carry out timing, and when timing reaches preset value output low level, otherwise export high level;
The level signal of three counters outputs is detected by the testing circuit be arranged in FPGA device, if the level signal difference that three counters export, testing circuit output low level signal, if the level signal of three counter outputs is identical, testing circuit exports the level signal identical with the first to the 3rd counter;
The low level signal exported by testing circuit reshuffles pin from the external transmission of FPGA device to FPGA, and controls to reshuffle pin and keep the low level time more than Preset Time.
FPGA device of the present invention does not need to increase extra single-chip microcomputer, FPGA device or watchdog circuit from reconfiguration device and method, only self-configuring circuit is set in FPGA device, at FPGA device exterior, simple signal conditioning circuit is set, structure is simple, easily connects up, only takies very little FPGA device inside resource, the PCB resource taken is less, not only achieve timing to reshuffle, also there is the function detecting mistake, can enforce when mistake being detected and reshuffle.
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the block scheme of field programmable gate array of the present invention from a kind of embodiment of reconfiguration device.
Fig. 2 is the circuit diagram of field programmable gate array of the present invention from a kind of embodiment of reconfiguration device.
Fig. 3 is the process flow diagram of field programmable gate array of the present invention from a kind of embodiment of method for reconfiguration.
Fig. 4 is the process flow diagram of step S2 in Fig. 3.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of embodiment and feature can combine with the element shown in one or more other accompanying drawing or embodiment and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.
For SRAM type FPGA device, generally all provide one and reshuffle pin, by applying the low level pulse of a predetermined width at this pin, FPGA device just can be made to enter the stage of reshuffling.The invention provides a kind of FPGA device from reconfiguration device.In the apparatus of the present, the low level pulse of this predetermined width self is provided by FPGA device to be configured, particularly, in FPGA device to be configured, self-configuring circuit is set, this self-configuring circuit output end is as an I/O pin of FPGA device to be configured, reshuffle pin by the signal conditioning circuit of outside with this to be connected, this self-configuring circuit can force when reshuffling signal or mistake detected output to reshuffle signal by timing output, what this reshuffled that signal exports FPGA device to after signal conditioning circuit conditioning reshuffles pin, FPGA device is made to enter the stage of reshuffling, signal conditioning circuit is used for control and reshuffles the pin maintenance low level time more than Preset Time.
The invention provides a kind of FPGA device from reconfiguration device, comprise the self-configuring circuit be arranged in FPGA device and the signal conditioning circuit being arranged on FPGA device exterior, self-configuring circuit comprises the first to the 3rd counter and is connected to the testing circuit of the first to the 3rd counter, first to the 3rd counter is for receiving same clock pulse signal to carry out timing, and when timing reaches preset value output low level signal, otherwise output high level signal, for detecting the first to the 3rd counter, whether one of them exports different level signals from other two counters to testing circuit, and when difference being detected output low level signal, the level signal identical with the first to the 3rd counter is exported when detecting that the first to the 3rd counter exports identical level signal, the output terminal connection signal modulate circuit of testing circuit, signal conditioning circuit is used for the low level signal that testing circuit exports to transfer to reshuffle pin, and control to reshuffle the pin maintenance low level time more than Preset Time.
Alternatively, testing circuit comprises the first to the 3rd voting machine, first to the 3rd arithmetical unit, first to the 3rd tri-state gate circuit, first to the 3rd voting machine respectively has the first to the 3rd input end and the first output terminal and the second output terminal, the output terminal of the first counter is connected to the first input end of the first voting machine, second input end of the second voting machine and the second input end of the 3rd voting machine, the output terminal of the second counter connects the first input end of the second voting machine, second input end of the first voting machine and the 3rd input end of the 3rd voting machine, the output terminal of the 3rd counter connects the first input end of the 3rd voting machine, 3rd input end of the first voting machine and the 3rd input end of the second voting machine, first arithmetic device be used for the output terminal of the first counter and the first output terminal of the first voting machine carry out with computing after export the input end of the first tri-state gate circuit to, second output terminal of the first voting machine is as the control end of the first tri-state gate circuit, second arithmetic device be used for the output terminal of the second counter and the first output terminal of the second voting machine carry out with computing after export the input end of the second tri-state gate circuit to, second output terminal of the second voting machine is as the control end of the second tri-state gate circuit, 3rd arithmetical unit be used for the output terminal of the 3rd counter and the first output terminal of the 3rd voting machine carry out with computing after export the input end of the 3rd tri-state gate circuit to, second output terminal of the 3rd voting machine is as the control end of the 3rd tri-state gate circuit, as the output terminal of testing circuit after the output terminal of the first to the 3rd tri-state gate circuit is connected, first, second or the 3rd first output terminal of voting machine in second of correspondence, high level signal is exported when the level signal of the 3rd input end is identical, in second of correspondence, output low level signal when the level signal of the 3rd input end is different, first, second or the 3rd second output terminal of voting machine in the level signal and corresponding second of the first input end of correspondence, high level signal is exported when the level signal of the 3rd input end is all not identical, in the level signal and second of the first input end of correspondence, output low level signal when one of them level signal of 3rd input end is identical.
With reference to figure 1, for FPGA device of the present invention is from the block scheme of reconfiguration device.In embodiments of the invention, be specifically described for the FPGA device 100 of XilinxVirtex series, make the FPGA device 100 of XilinxVirtex series enter the stage of reshuffling, need its pin PROGRAM to keep the low level of more than 300ns (nanosecond).In this FPGA device 100 inside, self-configuring circuit 10 is set, the output terminal I/O of self-configuring circuit 10 connects the pin PROGRAM of FPGA device 100 by the signal conditioning circuit 20 being arranged on FPGA device 100 outside, during normal work, the output terminal I/O of self-configuring circuit 10 exports high level.Self-configuring circuit 10 for receive clock signal to carry out timing, its output terminal I/O can when timing reaches preset value output low level signal, i.e. configuration signal; When self-configuring circuit 10 detects mistake, it forces output low level; The low level signal that self-configuring circuit 10 exports transfers to pin PROGRAM through modulate circuit 20, and modulate circuit 20 ensures that this low level signal maintains more than 300ns and enters reset phase to make FPGA device 100.
With reference to figure 2, for FPGA device of the present invention is from the circuit diagram of reconfiguration device.In order to meet the demand of AEROSPACE APPLICATION, need to carry out anti-single particle overturn Design of Reinforcement to FPGA device, self-configuring circuit of the present invention adopts the triplication redundancy design improved, and possesses simultaneously and reinforces function and error detection function.As shown in Figure 2, self-configuring circuit 10 comprises counter Counter1-Counter3, voting machine M1-M3, arithmetical unit U1-U3, tri-state gate circuit T1-T3, and voting machine M1-M3 respectively has input end P, I1, I2 and output terminal X and Y.Voting machine M1-M3, arithmetical unit U1-U3, tri-state gate circuit T1-T3 form testing circuit.The input end of counter Counter1-Counter3 is used for receive clock pulse signal, and the output terminal of counter Counter1 is connected to the input end P of voting machine M1, also connects the input end I1 of voting machine M2 and M3.The output terminal of counter Counter2 connects the input end P of voting machine M2, also connects the input end I1 of voting machine M1 and the input end I2 of voting machine M3.The output terminal of counter Counter3 connects the input end P of voting machine M3 and the input end I2 of voting machine M1, M2.Arithmetical unit U1 be used for the output terminal of counter Counter1 and the output terminal X of voting machine M1 carry out with computing after export the input end of tri-state gate circuit T1 to, the output terminal Y of voting machine M1 is as the control end of tri-state gate circuit T1.Arithmetical unit U2 be used for the output terminal of counter Counter2 and the output terminal X of voting machine M2 carry out with computing after export the input end of tri-state gate circuit T2 to, the output terminal Y of voting machine M2 is as the control end of tri-state gate circuit T2.Arithmetical unit U3 be used for the output terminal of counter Counter3 and the output terminal X of voting machine M3 carry out with computing after export the input end of tri-state gate circuit T3 to, the output terminal Y of voting machine M3 is as the control end of tri-state gate circuit T3.As the output terminal I/O of self-configuring circuit 10 after the output terminal of tri-state gate circuit T1-T3 is connected.
Signal conditioning circuit 20 comprises electric capacity C1 and pull-up resistor R1, one end of electric capacity C1 connects the output terminal I/O of configuration circuit 10, the other end that the other end connects one end of pull-up resistor R1 and the pin PROGRAM of FPGA device 100, pull-up resistor R1 connects power supply.
The time clock that counter Counter1-Counter3 is used for receiving counts, the output low level when counting reaches preset value, otherwise exports high level.
Seeing table, is input end P, I1, I2 of each voting machine M1-M3 and the truth table of output terminal X, Y.Input end I1, I2 of each voting machine M1-M3 are for detecting mistake, when the level signal of input end I1 with I2 of each voting machine M1-M3 is identical, corresponding output terminal X exports high level " 1 ", when the level signal of input end I1 with I2 of each voting machine M1-M3 is different, corresponding output terminal X output low level " 0 ".If the input end P of each voting machine M1-M3 is all different from corresponding input end I1 and I2, corresponding output terminal Y exports high level " 1 ", if one of them is identical for the input end P of each voting machine M1-M3 and corresponding input end I1 with I2, corresponding output terminal Y output low level " 0 ".
| P | I1 | I2 | X | Y |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 1 |
Under normal circumstances, the clock pulse signal that counter Counter1-Counter3 receives is identical, therefore export also identical, the output terminal X of three voting machine M1-M3 all exports high level, the equal output low level of output terminal Y of three voting machine M1-M3, when counting does not reach preset value, the output terminal of tri-state gate circuit T1-T3 all exports high level, when reaching preset value, the equal output low level of output terminal of tri-state gate circuit T1-T3.
Suppose due to space single particle effect, cause the storage unit generation single-particle inversion of FPGA device 100 inside, cause one of them counter, as counter Counter1 makes mistakes, all the other two counters are normal, now, for voting machine M1, the level signal of its input end I1, I2 is identical, and the level signal of its input end P is different from the level signal of input end I1, I2, and therefore output terminal X exports high level, output terminal Y exports high level, tri-state gate circuit T1 closes, and the output terminal of tri-state gate circuit T1 becomes high-impedance state, forbids exporting.
For voting machine M2, the level signal of its input end I1, I2 is different, and the level signal of input end P is identical with input end one of I1, I2, therefore output terminal X output low level, output terminal Y output low level, arithmetical unit U2 output low level, tri-state gate circuit T2 output low level.
For voting machine M3, its input end I1, I2 are different, and the level signal of input end P is identical with input end one of I1, I2, therefore output terminal X output low level, output terminal Y output low level, arithmetical unit U3 output low level, tri-state gate circuit T3 output low level.
In signal conditioning circuit 20, electric capacity C1 and pull-up resistor R1 forms charge-discharge circuit, during normal work, electric capacity C1 two ends are high level, when receiving the low level signal that tri-state gate circuit T2 and T3 exports, electric capacity C1 starts electric discharge to draw as low level by pin PROGRAM, the parameter value suitably choosing electric capacity C1 and pull-up resistor R1 just can make the low level retention time of pin PROGRAM at more than 300ns, for the FPGA device of other series, selection by electric capacity C1 and pull-up resistor R1 parameter value obtains different discharge times, to adapt to the demand of different low level retention times.After electric discharge terminates, electric capacity C1 plays the effect of isolation, ensures that pin PROGRAM reverts to high level by pull-up pull-up resistor R1, with ensure replacement complete after FPGA device 100 recover normal work.
Alternatively, signal conditioning circuit also comprises hand switch K1, and hand switch K1 one end connects pin PROGRAM, other end ground connection, and hand switch is used for hand-reset to start reshuffling of FPGA device 100.
Alternatively, signal conditioning circuit 20 also comprises pull down resistor R2, and one end of pull down resistor R2 connects the output terminal of tri-state gate circuit T1-T3, other end ground connection.In AEROSPACE APPLICATION, except easily there is single particle effect and except making a mistake in the config memory of FPGA device inside, also single particle effect can be there is and make mistakes in some important registers of FPGA device inside, to some critical functions of FPGA device be caused to lose efficacy like this, namely single event function interrupt, single event function interrupt can be divided into following two kinds of situations;
1, electrification reset logic (POR) register and some overall signals etc. make a mistake, and the input causing FPGA device all, output pin are lost efficacy, and become high-impedance state.
2, SelectMAP configuration register, JTAG configuration register and FAR frame address register make a mistake, and will the configuration interface of FPGA device be caused to lose efficacy, all the other output/output interfaces be normal.
For the first situation, although the program of FPGA device inside can also normally be run, I/O pin becomes high-impedance state and lost efficacy, and FPGA device also will be caused normally to work.Pull down resistor R2 is set in signal conditioning circuit 20, lost efficacy once all I/O of FPGA device become high-impedance state, electric capacity C1 will be discharged by this pull down resistor R2, causing pin PROGRAM to become low level, the low level of pin PROGRAM can be made to maintain more than 300ns by suitably selecting the resistance of the capacitance of electric capacity C1 and pull down resistor R2.Like this, just achieve when there is single event function interrupt and automatically enter reconfiguration status, make FPGA device 100 recover normal work.
For the second situation, be only configuration circuit interface fails, the program of all the other I/O pins and FPGA device inside still can normally work, so not influential system function.Etc. to be counted reach preset value perform timing reshuffle after, these mistakes will be corrected, thus make FPGA device 100 recover normal operating conditions.
Therefore, pull down resistor R2 is set, automatically reshuffling when can realize single event function interrupt in signal conditioning circuit 20, recovers normal work to make FPGA device.
With reference to figure 3, FPGA device of the present invention is applied FPGA device of the present invention from method for reconfiguration and is carried out reshuffling of FPGA device from reconfiguration device, comprises the following steps:
Step S1: receive same pulse signal by three counters (i.e. counter Counter1-Counter3) be arranged in FPGA device and carry out timing, and when timing reaches preset value output low level, otherwise export high level;
Step S2: the level signal being detected three counters outputs by the testing circuit be arranged in FPGA device, if the level signal difference that three counters export, testing circuit output low level signal, if the level signal of three counter outputs is identical, testing circuit exports the level signal identical with three counters;
Step S3: the low level signal exported by testing circuit reshuffles pin, i.e. pin PROGRAM from the external transmission of FPGA device to institute FPGA device, and control to reshuffle pin and keep the low level time more than Preset Time.
With reference to figure 4, alternatively, step S2 comprises the following steps:
Step S21: judge that whether the wherein output of two in three counters is identical respectively; In this step, respectively the output of three counters is judged between two, such as, judge the output of counter Counter1 with Counter2 whether identical (whether being namely all high level " 1 " or low level " 0 "), judge that whether the output of counter Counter2 with Counter3 is identical, also judge that whether the output of counter Counter1 with Counter3 is identical;
Step S22: export identical situation for any two counters, carries out AND operation by the output of another counter and high level " 1 "; Different situations is exported for any two counters, another counter and low level " 0 " are carried out AND operation; Such as, when the output of counter Counter1 with Counter2 is identical, AND operation is carried out in the output of counter Counter3 and high level " 1 ", otherwise AND operation is carried out in the output of counter Counter3 and low level " 0 "; When the output of counter Counter2 with Counter3 is identical, AND operation is carried out in the output of counter Counter1 and high level " 1 ", otherwise AND operation is carried out in the output of counter Counter1 and low level " 0 "; When the output of counter Counter1 with Counter3 is identical, AND operation is carried out in the output of counter Counter2 and high level " 1 ", otherwise AND operation is carried out in the output of counter Counter2 and low level " 0 ";
Step S23: judge that whether three counters are identical with the output of two other counter respectively; In this step, judge that whether the output of counter Counter1 is identical with counter Counter1 with Counter2, judge that whether the output of counter Counter2 is identical with counter Counter1 with Counter3, also judge that whether the output of counter Counter3 is identical with counter Counter1 with Counter2;
Step S24: if one of them counter and two other counter export all different, forbids the result after exporting this counter and high level " 1 " or low level " 0 " carries out AND operation; Such as, if the output of counter Counter1 is all different from counter Counter1 and Counter2, forbid output counter Counter1 and high level " 1 " or low level " 0 " carry out AND operation after result; If the output of counter Counter2 is all different from counter Counter1 and Counter3, forbid output counter Counter2 and high level " 1 " or low level " 0 " carry out AND operation after result; If the output of counter Counter3 is all different from counter Counter1 and Counter2, forbid output counter Counter3 and high level " 1 " or low level " 0 " carry out AND operation after result;
Step S25: if the output of one of them counter exports identical with one of two other counter, export this counter and high level " 1 " or low level " 0 " carry out AND operation after result.Such as, if the output of counter Counter1 is identical with the output of counter Counter1 or Counter2, output counter Counter1 and high level " 1 " or low level " 0 " carry out the result after AND operation; If the output of counter Counter2 is identical with counter Counter1 or Counter2, output counter Counter2 and high level " 1 " or low level " 0 " carry out the result after AND operation; If the output of counter Counter3 is identical with counter Counter1 or Counter2, output counter Counter3 and high level " 1 " or low level " 0 " carry out the result after AND operation.
The single-chip microcomputer not needing increase extra from reconfiguration device and method of the present invention, FPGA device or watchdog circuit, only self-configuring circuit is set in FPGA device, at FPGA device exterior, simple signal conditioning circuit is set, structure is simple, easy wiring, only take very little FPGA device inside resource, take less PCB resource, three counters and testing circuit is utilized to achieve the reinforcing mode of triplication redundancy, not only achieve timing to reshuffle, also there is the function detecting mistake, can enforce when mistake being detected and reshuffle, also can realize automatically reshuffling when there is single event function interrupt.
In the system of the present invention, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Simultaneously, above in the description of the specific embodiment of the invention, the feature described for a kind of embodiment and/or illustrate can use in one or more other embodiment in same or similar mode, combined with the feature in other embodiment, or substitute the feature in other embodiment.
In the apparatus of the present: invention, obviously, each parts reconfigure after can decomposing, combine and/or decomposing.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Above in the description of the specific embodiment of the invention, the feature described for a kind of embodiment and/or illustrate can use in one or more other embodiment in same or similar mode, combined with the feature in other embodiment, or substitute the feature in other embodiment.
Should emphasize, term " comprises/comprises " existence referring to feature, key element, step or assembly when using herein, but does not get rid of the existence or additional of one or more further feature, key element, step or assembly.
Although described the present invention and advantage thereof in detail, be to be understood that and can have carried out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and conversion.And the scope of the application is not limited only to the specific embodiment of process, equipment, means, method and step described by instructions.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (7)
1. a FPGA is from reconfiguration device, comprise the self-configuring circuit be arranged in FPGA and the signal conditioning circuit being arranged on described field programmable gate array outside, described self-configuring circuit comprises the first to the 3rd counter and is connected to the testing circuit of the described first to the 3rd counter, described first to the 3rd counter is for receiving same clock pulse signal to carry out timing, and when timing reaches preset value output low level signal, otherwise output high level signal, described testing circuit is for detecting one of them whether different from some output in other two counters level signal of the described first to the 3rd counter, and when difference being detected output low level signal, the level signal identical with the described first to the 3rd counter is exported when detecting that the described first to the 3rd counter exports identical level signal, the output terminal of described testing circuit connects described signal conditioning circuit, what described signal conditioning circuit was used for the low level signal that described testing circuit exports to transfer to described FPGA reshuffles pin, and reshuffle the pin maintenance low level time described in controlling more than Preset Time.
2. FPGA as claimed in claim 1 is from reconfiguration device, it is characterized in that, described testing circuit comprises the first to the 3rd voting machine, first to the 3rd arithmetical unit, first to the 3rd tri-state gate circuit, described first to the 3rd voting machine respectively has the first to the 3rd input end and the first output terminal and the second output terminal, the output terminal of described first counter is connected to the first input end of described first voting machine, second input end of described second voting machine and the second input end of the 3rd voting machine, the output terminal of described second counter connects the first input end of described second voting machine, second input end of the first voting machine and the 3rd input end of the 3rd voting machine, the output terminal of described 3rd counter connects the first input end of described 3rd voting machine, 3rd input end of the first voting machine and the 3rd input end of the second voting machine, described first arithmetic device be used for the output terminal of described first counter and the first output terminal of described first voting machine carry out with computing after export the input end of described first tri-state gate circuit to, second output terminal of described first voting machine is as the control end of described first tri-state gate circuit, described second arithmetic device be used for the output terminal of described second counter and the first output terminal of the second voting machine carry out with computing after export the input end of described second tri-state gate circuit to, second output terminal of described second voting machine is as the control end of described second tri-state gate circuit, described 3rd arithmetical unit be used for the output terminal of described 3rd counter and the first output terminal of described 3rd voting machine carry out with computing after export the input end of described 3rd tri-state gate circuit to, second output terminal of described 3rd voting machine is as the control end of described 3rd tri-state gate circuit, as the output terminal of described testing circuit after the output terminal of the described first to the 3rd tri-state gate circuit is connected, described first, second or the 3rd first output terminal of voting machine in second of correspondence, high level signal is exported when the level signal of the 3rd input end is identical, in second of correspondence, output low level signal when the level signal of the 3rd input end is different, described first, second or the 3rd second output terminal of voting machine in the level signal and corresponding second of the first input end of correspondence, high level signal is exported when the level signal of the 3rd input end is all not identical, in the level signal and second of the first input end of correspondence, output low level signal when one of them level signal of 3rd input end is identical.
3. FPGA as claimed in claim 1 is from reconfiguration device, it is characterized in that, described signal conditioning circuit comprises electric capacity and pull-up resistor, one end of described electric capacity connects the output terminal of described testing circuit, what the other end connected one end of described pull-up resistor and described FPGA reshuffles pin, and the other end of described pull-up resistor connects power supply.
4. FPGA as claimed in claim 3 is from reconfiguration device, and it is characterized in that, described signal conditioning circuit also comprises hand switch, reshuffles pin, other end ground connection described in one end connection of described hand switch.
5. FPGA as claimed in claim 3 is from reconfiguration device, and it is characterized in that, described signal conditioning circuit also comprises pull down resistor, and one end of described pull down resistor connects the output terminal of described testing circuit, other end ground connection.
6. FPGA is from a method for reconfiguration, comprising:
Receive same pulse signal by three counters be arranged in FPGA and carry out timing, and when timing reaches preset value output low level, otherwise export high level;
The level signal of described three counters output is detected by the testing circuit be arranged in described FPGA, if the level signal that described three counters export is different, described testing circuit output low level signal, if the level signal that described three counters export is identical, described testing circuit exports the level signal identical with the described first to the 3rd counter;
The low level signal exported by described testing circuit reshuffles pin from the external transmission of described FPGA to described FPGA, and reshuffles pin described in controlling and keep the low level time more than Preset Time.
7. FPGA as claimed in claim 6 is from method for reconfiguration, it is characterized in that, the step that testing circuit detects the level signal that described three counters export comprises:
Judge that whether the wherein output of two in described three counters is identical respectively;
Identical situation is exported for any two counters, AND operation is carried out in the output of another counter and high level " 1 "; Different situations is exported for any two counters, another counter and low level " 0 " are carried out AND operation;
Judge that whether described three counters are identical with the output of two other counter respectively;
If one of them counter export all different from two other counter, forbid the result after exporting this counter and high level " 1 " or low level " 0 " carries out AND operation;
If the output of one of them counter exports identical with one of two other counter, export this counter and high level " 1 " or low level " 0 " carry out AND operation after result.
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| EP3322095A1 (en) * | 2016-11-11 | 2018-05-16 | Tesat Spacecom GmbH & Co. KG | Tristate and cross current free output buffer |
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| CN104750481B (en) * | 2015-03-10 | 2018-04-17 | 深圳大学 | A kind of FPGA output pins multiplex circuit, method and apparatus |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| CN108536637B (en) * | 2018-04-24 | 2021-07-02 | 杭州芯声智能科技有限公司 | Communication system and method for transmitter conditioning chip |
| CN111104240A (en) * | 2019-11-28 | 2020-05-05 | 中国航空工业集团公司西安航空计算技术研究所 | FPGA fault self-recovery circuit and method |
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| US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
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| KR20070019173A (en) * | 2005-08-11 | 2007-02-15 | 삼성전자주식회사 | Integrated circuit devicee and method for monitoring a bus |
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| EP3322095A1 (en) * | 2016-11-11 | 2018-05-16 | Tesat Spacecom GmbH & Co. KG | Tristate and cross current free output buffer |
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