CN103066997B - Digital delay implementation method that a kind of binary channels based on FPGA is seamless - Google Patents
Digital delay implementation method that a kind of binary channels based on FPGA is seamless Download PDFInfo
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Abstract
The invention provides the seamless digital delay implementation method of a kind of binary channels based on FPGA, change switching time of delay take system processing time to overcome existing delay line, reduce the deficiency of system works efficiency, fully take into account the work characteristics of FIFO, adopt the data fifo memory block of two same structures, arrange by different requirement time of delay and select passage corresponding to different pieces of information memory block to export data, when a passage is when resetting, another passage is also uninterruptedly exporting data, when passage resets and writes full, the state of systematic evaluation two passages, read the data of the most newly-installed data storage area, make to meet Current demands from the input data of this data storage area respective channel and the time delay exported between data and avoid data storage area to switch the idle condition that pending datas such as causing system appearance exports, realize the different seamless switching postponing to export, real ghost environments can be simulated better.
Description
Technical field
The invention belongs to signal processing technology, be specifically related to digital delay techniques.
Background technology
Delay is a basic operation of signal transacting, and along with the development of digital technology, digital delay line obtains applying more and more widely in the field such as radar, communication.Adopt fpga chip, realizing digital delay line by hardware programming is current designer trends.Adopt fpga chip to realize digital delay, its duration postponed is realized by the length of data storage area in default queue FIFO (First Input First Output).As shown in Figure 1, when needs time delay N number of clock cycle, then the length of setting data memory block is N.In data storage area, write pointers point memory cell and read pointer point to memory cell and are spaced length N.Each clock cycle, fpga chip is to write pointers point memory cell write data; After data storage area is fully written, each clock cycle fpga chip points to memory cell by read pointer and reads data.Namely be read out to data from data storage area from data write data storage area and be just spaced N number of clock cycle, thus realize input data and export time delay N number of clock cycle between data.
In general radar signal simulation, according to the characteristics of motion of target, echo-signal time delay has the change increasing or reduce, and need carry out the delay process of different duration to signal.When exporting delay duration and need revising, data storage area in FIFO should be emptied, after resetting data storage area size according to new duration, wait pending data to fill the data exporting new time delay again.System processing time needed for data storage area switches (will empty FIFO and reload the system processing time that data need to expend according to new duration) causes the idle condition of the pending data outputs such as system appearance.Because real ghost environments does not exist such idle condition, therefore change the switching that FPGA realizes different digital time delay size neatly, avoid occurring that idle condition becomes more and more important to realize " seamless ".
Summary of the invention
Technical problem to be solved by this invention is, provides a kind of seamless digital delay line implementation method based on FPGA.
The present invention for solving the problems of the technologies described above adopted technical scheme is, digital delay implementation method that a kind of binary channels based on FPGA is seamless, comprises the following steps:
The size of initial setting up two panels data fifo memory block; Select a slice in two panels data storage area to be output state, another sheet is only write state; The data need carrying out time delay uninterruptedly sequentially send into two panels data storage area simultaneously;
After data storage area is fully written, start to read and the read pointer exporting the data storage area being in output state points to the data of memory cell, another sheet is in only write state data storage area and writes data from overflow completely;
When exporting the delay of data relative to input data and needing to adjust, while continuation is read the data storage area of output state, the data storage area being in only write state to be emptied and the length resetting this data storage area is target delay length; The data storage area being in only write state after resetting is write completely again, switches the state of two panels data storage area according to sequential.
The present invention changes switching take system processing time to overcome existing delay line time of delay, reduce the deficiency of system works efficiency, fully take into account the work characteristics of FIFO, adopt the data fifo memory block of two same structures, arrange by different requirement time of delay and select passage corresponding to different pieces of information memory block to export data, when a passage is when resetting, another passage is also uninterruptedly exporting data, when passage resets and writes full, the state of systematic evaluation two passages, read the data of the most newly-installed data storage area, make to meet Current demands from the input data of this data storage area respective channel and the time delay exported between data and avoid data storage area to switch the idle condition that pending datas such as causing system appearance exports.
Further, in order to make the real-time of time delay of the present invention the strongest, export data and need to carry out opportunity of adjusting for the system processing time needed for switching according to target travel rule and data storage area relative to the delay of input data, before target time delay change, in advance the data storage area being in only write state emptied and reset the length of this data storage area, when this data storage area starts to export data after state has been switched, export data and meet target time delay after change corresponding to current time relative to input data.That is, before target time delay change, the system processing time needed for switching according to data storage area starts to carry out data storage area hand-off process in advance, and after pending data memory block has switched, the time delay of output data meets the target delay requirement after change.
The invention has the beneficial effects as follows, realize the different seamless switching postponing to export by being arranged alternately of the identical data fifo memory block of two structures from alternately exporting, real ghost environments can be simulated better.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that existing fpga chip realizes digital delay;
Fig. 2 is the schematic diagram that embodiment F PGA chip realizes digital delay.
Embodiment
As shown in Figure 2, realizing digital delay line needs to use: 1, the FIFO of two install beforehand data storage area sizes, for preserving input data; Data for being postponed by band are distributed to the deconcentrator of these two data storage areas; Multiway analog switch MUX, for selecting the data of different pieces of information memory block respective channel as output data.FIFO adopts the IP kernel of FPGA to realize.Data fifo district size adopts USEDW signal setting.Data fifo district empties and adopts CLR signal controlling.
Digital delay implementation method that binary channels based on FPGA is seamless, more and more nearer with the motion of target in the ghost environments simulated, echo-signal time delay is reduced to example gradually, and step is as follows:
Step one, arrange the initial size of two panels data fifo memory block, it is that to arrange length be N-1 for N, FIFO2 that FIFO1 arranges length.The access mode of FIFO: when writing continuously, data sequentially input the memory cell of write pointers point; During reading, the memory cell pointed to from read pointer reads data, after the length of setting data memory block, exports data delay time corresponding with memory block length.
Step 2, input data sequentially send into FIFO1 and FIFO2, until data field is fully written simultaneously.
Step 3, data are write completely, select the memory cell pointed to from FIFO1 or FIFO2 read pointer to read data by MUX according to current target delay value.
When selection a certain FIFO carries out reading data, then MUX will open the output channel of this FIFO, and namely this FIFO is in the state that data export; Another sheet data fifo can not export, and is in only write state, and data are write and overflowed completely afterwards.When selecting by FIFO1 reading, export data relative to input data delay N number of clock cycle; When selecting by FIFO2 reading, export data relative to data delay N-1 the clock cycle of input.
Step 4, carry out data output as current selection FIFO2.While to FIFO2 reading, according to target travel rule, the required delay of time delay adjustment is next time adjusted to N-2 clock cycle by N-1 clock cycle, now by control signal CLR, FIFO1 is emptied, USEDW is set, makes FIFO1 data storage area length be N-2, again write completely until FIFO1, switch to according to sequential and exported by FIFO1, export data relative to data delay N-2 the clock cycle of input.
Step 5, when export data relative to input data delay need be adjusted to N-3 clock cycle by N-2 time, can while to FIFO1 reading, by control signal CLR, FIFO2 is emptied, USEDW is set, FIFO2 data storage area length is made to be N-3, again write completely until FIFO2, switch to according to sequential and exported by FIFO2, export data relative to data delay N-3 the clock cycle of input.
By being arranged alternately, switching FIFO1 and FIFO2, the change of signal time delay by N-3 clock cycle to 1 clock cycle can be realized.
Reach need adjust time delay, stop switching FIFO operating state.
Through above-mentioned steps process, can obtain the output signal meeting delay requirement, the delay due to two different time of delays exports and is realized by two panels FIFO respectively, and is selected by diverter switch, seamless delay can be realized, avoid the idle condition that the pending datas such as system appearance export.
Optionally, in step one, when the initial size of data memory area is arranged, the length of two panels FIFO also can be set to identical or different length.As being set to different length, the difference of the length of two panels FIFO can be the step-length postponing adjustment, the delay adjustment step-length arranged in embodiment is 1 clock cycle, is certainly also not limited only to this, can according to the actual requirements using 2 or 3 even longer clock cycle as delay adjustment step-length.
Optionally, in step 3, embodiment MUX carries out the first reading to the two panels FIFO after initialization and selects to be after FIFO writes completely.Equally, also can give tacit consent to certain a slice FIFO when two panels FIFO initial setting up be the initial object read, and gives tacit consent to it for output state, reads when this FIFO writes completely and opened the output channel of this FIFO by MUX this FIFO read pointer sensing memory cell.
Be not limited to as the module exporting data the module that existing multiway analog switch MUX can also be other identical selection function for selecting the data of different pieces of information memory block respective channel.Even, this selection module can receive the data from two FIFO respective channel simultaneously, then exports the data of a passage (output state) according to target delay selection, abandons the data of another passage (only write state).
Embodiment
Adopt radar signal simulator as platform, according to simulated target and the relative position of radar and the motion mode of target, enter radar beam main lobe from target and leave radar beam main lobe to target, receive altogether M echo impulse.The echo-signal of its first pulse repetition period and the delay between transmitting were 500 clock cycle, the echo-signal of second pulse repetition period and the delay between transmitting were 499 clock cycle, by that analogy, M echo-signal and the delay between transmitting are 500-M+1 clock cycle, therefore need the FIFO size arranged to be 500 ~ 500-M+1.
Step one, arrange the size of two panels data fifo memory block, it is that to arrange length be 499 to 500, FIFO2 that FIFO1 arranges length.
Step 2, data sequentially send into FIFO1 and FIFO2 simultaneously, until data field is fully written.
Step 3, data write full after, according to simulated target and the relative position of radar and the motion mode of target, being selected first from FIFO1, to read data by selector switch, exporting data relative to inputting 500 clock cycle of data delay; When target delay needs to be adjusted to 499, selected to read data from FIFO2 by selector switch, export data relative to input 499 clock cycle of data delay.
Step 4, according to embodiment assumed condition, while to FIFO2 reading, required time delay should be adjusted to 498 next time, then by control signal CLR, FIFO1 is emptied, USEDW is set, makes FIFO1 data storage area reduce by 2 long measures, again write completely until FIFO1, switch to according to sequential and exported by FIFO1, export data relative to input 498 clock cycle of data delay.
Step 5, while to FIFO1 reading, required time delay should be adjusted to 497 next time, then by control signal CLR, FIFO2 is emptied, USEDW is set, FIFO2 data storage area is made to reduce by two unit, again write completely until FIFO2, switch to according to sequential and exported by FIFO2, export data relative to input 497 clock cycle of data delay.
Step 6, the step 4 that hockets and step 5, can realize the change of signal time delay by 498 clock cycle to 500 ~ 500-M+1 the clock cycle.
Those of ordinary skill in the art will appreciate that, embodiment described here is to help reader understanding's implementation method of the present invention, should be understood to that protection scope of the present invention is not limited to so special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combination of not departing from essence of the present invention according to these technology enlightenment disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
Claims (8)
1., based on the seamless digital delay implementation method of binary channels of FPGA, it is characterized in that, comprise the following steps:
The size of initial setting up two panels data fifo memory block; Select a slice in two panels data fifo memory block to be output state, another sheet is only write state; The data need carrying out time delay uninterruptedly sequentially send into two panels data fifo memory block simultaneously;
After data fifo memory block is fully written, start to read and export the data of the data fifo memory block being in output state, another sheet is in only write state data fifo memory block and writes data from overflow completely;
When exporting the delay of data relative to input data and needing to adjust, while the data fifo memory block of output state is read, the data fifo memory block being in only write state is emptied and resets the length of this data fifo memory block; After resetting the length of data fifo memory block, the data fifo memory block being in only write state starts data cached, again writes completely, switches the state of two panels data fifo memory block according to sequential;
Export data and need to carry out opportunity of adjusting for the system processing time needed for switching according to target travel rule and data fifo memory block relative to the delay of input data, before target time delay change, in advance the data fifo memory block being in only write state emptied and reset the length of this data fifo memory block, when this data fifo memory block starts to export data after state has been switched, export data and meet target time delay after change corresponding to current time relative to input data.
2. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, it is characterized in that, when arranging the initial size of data fifo memory block, the length of two panels data fifo memory block is set to equal length.
3. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, it is characterized in that, when the initial size of data fifo memory block is arranged, the length of two panels data fifo memory block is set to different length, and the difference of the length of two panels FIFO is the step-length postponing adjustment.
4. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, is characterized in that, to the two panels data fifo memory block after Initialize installation carry out first time condition selecting be data fifo memory block first time write full after.
5. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, is characterized in that, to the two panels data fifo memory block after Initialize installation carry out first time condition selecting be data write is carried out to data fifo memory block before.
6. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, is characterized in that, described two panels data fifo memory block adopts the IP kernel of FPGA to realize.
7. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, is characterized in that, adopts USEDW signal to arrange two panels data fifo memory block size.
8. the seamless digital delay implementation method of a kind of binary channels based on FPGA as claimed in claim 1, is characterized in that, adopts CLR signal controlling data fifo memory block to empty.
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| CN104731550B (en) * | 2015-03-12 | 2017-10-17 | 电子科技大学 | A kind of Clock Doubled bi-directional digital related method thereof based on single FIFO |
| CN105790822B (en) * | 2016-03-04 | 2019-03-05 | 北京航空航天大学 | The configurable chain circuit transmission time delay production method of the bit error rate, apparatus and system |
| CN108414988B (en) * | 2018-03-09 | 2020-06-05 | 北京润科通用技术有限公司 | Digital delay method and device based on FPGA |
| CN114330229B (en) * | 2022-03-11 | 2022-06-03 | 苏州浪潮智能科技有限公司 | Method, device, equipment and medium for delay modeling of memory |
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