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Publication numberCN103066997 A
Publication typeApplication
Application numberCN 201210497093
Publication date24 Apr 2013
Filing date29 Nov 2012
Priority date29 Nov 2012
Also published asCN103066997B
Publication number201210497093.4, CN 103066997 A, CN 103066997A, CN 201210497093, CN-A-103066997, CN103066997 A, CN103066997A, CN201210497093, CN201210497093.4
Inventors崔明雷, 钱璐, 邹林, 于雪莲, 周云, 汪学刚
Applicant电子科技大学
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Two-channel seamless digit delay implementation method based on field programmable gate array (FPGA)
CN 103066997 A
Abstract
The invention provides a two-channel seamless digit delay implementation method based on a field programmable gate array (FPGA). The defects that an existing delay line delays time for replacing and switching and occupies system processing time, and system work efficiency is lowered are overcome. The work characteristics of first input first output (FIFO) are fully considered, two FIFO data storage areas which are identical in structure are adopted, and channels corresponding to different data storage areas are arranged and selected according to the different delay time requirements to output data. When one channel is rearranged, another channel outputs the data continuously. When the channels are rearranged and written full, the states of the two channels are switched by a system, the data of a data storage area which is arranged up to the minute are read, so that the time delay between input data and output data of the corresponding channel of the data storage area meets the current requirements, and an idle state for waiting the data to be output which occurs in the system and is caused by switching of the data storage area is avoided. Therefore, seamless switching of different delay outputs is achieved, and an authentic echo environment can be better simulated.
Claims(9)  translated from Chinese
1. 一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,包括以下步骤: 初始设置两片FIFO数据存储区的大小;选择两片数据存储区中的一片为输出状态,另一片为仅写入状态;需进行延时的数据不间断依序同时送入两片数据存储区; 当数据存储区被写满后,开始读取并输出处于输出状态的数据存储区的数据,另一片处于仅写入状态数据存储区写满后数据溢出; 当输出数据相对于输入数据的延迟需要进行调整时,在对输出状态的数据存储区进行读取的同时,对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度;待重新设置数据存储区的长度后,处于仅写入状态的数据存储区开始缓存数据,重新写满后,根据时序切换两片数据存储区的状态。 An FPGA-based seamless dual-channel digital delay implemented method comprising the following steps: Set the size of the initial two-chip FIFO data storage area; choose two pieces of data in a storage area for output state, and the other piece To write only the state; the need for delay uninterrupted sequence data into two pieces at the same time the data storage area; when the data storage area is full, start reading and outputting data in the output state of the data storage area, and the other After only write in a state data storage area filled with data overflow; when the output data is delayed relative to the input data need to be adjusted in the output state of the data storage area for reading the same time, just write in the state data store emptied and re-set the length of the data storage area; Upon re-set the length of the data store, in the state of the data written to only cache data storage area began after the re-filled, according to the two pieces of data stored in the timing switch state area.
2.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,输出数据相对于输入数据的延迟需要进行调整的时机为:根据目标运动规律与数据存储区切换所需的系统处理时间,在目标延时变化之前,预先对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度,使得状态切换完成后该数据存储区开始输出数据时,输出数据相对于输入数据满足当前时刻对应的变化后目标延时。 1 2. The FPGA-based digital dual-channel seamless claim delay implemented method wherein the output data with respect to the input data of the delay time needs to be adjusted to: switch the data storage area according to the movement of the target When the processing time required for the system, before the target delay variation, in advance only to write the state data storage area cleared and re-set the length of the data storage area, making the state after completion of the handover of the data storage area starts to output data , the output data with respect to the input data satisfies the corresponding change in the current time after the target delay.
3.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对数据存储区的初始大小进行设置时,两片FIFO数据存储区的长度设置为相同长度。 1. An FPGA-based seamless dual-channel digital delay realization claim, characterized in that when the initial size of the data set storage area, length setting two FIFO data storage area for the same length.
4.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对数据存储区的初始大小进行设置时,两片FIFO数据存储区的长度设置为不同长度,两片FIFO的长度之差为延迟调整的步长。 4. claim 1 FPGA-based seamless dual-channel digital delay implementation, wherein when the initial size of the data set storage area, two length FIFO data storage area is set to different lengths, the difference between the lengths of two FIFO for delay adjustment steps.
5.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对初始化设置之后的两片数据存储区进行第一次状态选择是在数据存储区第一次写满之后。 5. As an FPGA-based seamless dual-channel digital rights to delay the implementation method, wherein the data storage area for two after the initial setup for the first time the state of choice is in the data storage area for the first time filled later.
6.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,对初始化设置之后的两片数据存储区进行第一次状态选择是对数据存储区进行数据写入之前。 6. As described in an FPGA-based seamless dual-channel digital rights to delay the implementation method, wherein the data storage area for two after the initial setup for the first time the state of choice is a data storage area for data write into before.
7.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,所述两片FIFO数据存储区采用FPGA的IP核实现。 7. As described in an FPGA-based seamless dual-channel digital rights to delay the implementation method, characterized in that the two FIFO data store using FPGA IP cores implementation.
8.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,采用USEDW信号对两片FIFO数据存储区大小进行设置。 8. As described in an FPGA-based seamless dual-channel digital rights to delay the implementation method, wherein the signal using USEDW two FIFO data store size setting.
9.如权利要求1所述一种基于FPGA的双通道无缝数字延迟实现方法,其特征在于,采用CLR信号控制数据存储区清空。 9. As described in an FPGA-based seamless dual-channel digital rights to delay the implementation method, wherein the control data signal using CLR store emptied.
Description  translated from Chinese

—种基于FPGA的双通道无缝数字延迟实现方法 - Kind of FPGA-based seamless dual-channel digital delay implementation

技术领域 FIELD

[0001] 本发明属于信号处理技术,具体涉及数字延迟技术。 [0001] The present invention belongs to the signal processing techniques, in particular to digital delay technology.

背景技术 BACKGROUND

[0002] 延迟是信号处理的一个基本操作,随着数字技术的发展,数字延迟线在雷达、通信等领域得到越来越广泛的应用。 [0002] The delay is a basic operation of signal processing, with the development of digital technology, digital delay line in radar, communications and other areas to be more widely used. 采用FPGA芯片,通过硬件编程实现数字延迟线是当前的一个设计趋势。 Using FPGA chip, digital delay line by a hardware programming is the current design trends. 采用FPGA芯片实现数字延迟,其延迟的时长是通过预设队列FIFO(先入先出队列)中数据存储区的长度来实现的。 FPGA chip using a digital delay, duration of its delay by default queue FIFO (first-in, first-out queue) length of the data storage area to achieve. 如图1所示,当需要延时N个时钟周期,则设置数据存储区的长度为N。 Shown in Figure 1, when the need to delay N clock cycles, then set the length of the data storage area for N. 这样,本领域的普通技术人员将会意识到,这里所述的实施例是为了帮助读者理解本发明的实施方法,应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。 Thus, one of ordinary skill in the art will recognize that the embodiment described herein is to help the reader understand the embodiment of the method of the invention, it should be understood that the scope of the present invention is not limited to such special representations Example . 本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合,这些变形和组合仍然在本发明的保护范围内。 Of ordinary skill in the art may be made without departing from the spirit of the invention various other modifications and combinations of various specific teachings of the present invention based on these technologies disclosed, such modifications and combinations are still within the scope of the present invention. 数据存储区中写指针指向存储单元与读指针指向存储单元间隔了长度N。 Datastore write pointer to a pointer to the memory cell and memory cell read interval of length N. 每一个时钟周期,FPGA芯片向写指针指向存储单元写入数据;当数据存储区被写满后,每一个时钟周期FPGA芯片由读指针指向存储单元读取数据。 Each clock cycle, FPGA chip to write pointer to write data to the storage unit; when the data storage area is full, each clock cycle FPGA chip by the read pointer to the memory cell read data. 即从数据写入数据存储区到数据从数据存储区被读出就间隔了N个时钟周期,从而实现输入数据与输出数据之间延时N个时钟周期。 Writing data from the data storage to the data is read out from the data storage area on the interval of N clock cycles, in order to achieve delayed by N clock cycles between input data and output data.

[0003] 在雷达信号模拟中,根据目标的运动规律,回波信号时延会有增大或减小的变化,需对信号进行不同时长的延时处理。 [0003] In the radar signal simulation, according to the movement of the target echo signal delay will increase or decrease of the change, the need for signal processing is not the same long delay. 在输出延时时长需修改时,应将FIFO中数据存储区清空,按照新的时长重新设置数据存储区大小后,等待数据装满再输出新的时延的数据。 Duration to be modified, should empty the FIFO data storage area in the output delay, to reset the size of the data storage area in accordance with the new length after waiting for data filled and then output the new data delay. 数据存储区切换所需的系统处理时间(将清空FIFO并按照新的时长重新装载数据需要耗费的系统处理时间)导致系统出现等待数据输出的空闲状态。 System processing time required to switch the data storage area (the empty FIFO and the length of time according to the new reload system takes data processing time) cause the system idle waiting for data output. 由于真实的回波环境并不存在这样的空闲状态,因此灵活地改变FPGA实现不同数字时延大小的切换,避免出现空闲状态以实现“无缝”变得越来越重要。 Because the true echo does not exist such an environment the idle state, and therefore the flexibility to change FPGA digital delay to switch different sizes, to avoid idle state in order to achieve a "seamless" become increasingly important.

发明内容 SUMMARY

[0004] 本发明所要解决的技术问题是,提供一种基于FPGA的无缝数字延迟线实现方法。 [0004] The technical problem to be solved by the present invention is to provide a seamless digital delay an FPGA-based implementation.

[0005] 本发明为解决上述技术问题所采用的技术方案是,一种基于FPGA的双通道无缝数字延迟实现方法,包括以下步骤: [0005] aspect of the present invention is to solve the above technical problems employed is a FPGA-based dual-channel digital delay seamlessly implemented method comprising the steps of:

[0006] 初始设置两片FIFO数据存储区的大小;选择两片数据存储区中的一片为输出状态,另一片为仅写入状态;需进行延时的数据不间断依序同时送入两片数据存储区; [0006] set the size of the initial two-chip FIFO data storage area; choose two pieces of data in a storage area for output state, and the other piece is written only to the state; the need for delay uninterrupted sequence data into two pieces at the same time data storage area;

[0007] 当数据存储区被写满后,开始读取并输出处于输出状态的数据存储区的读指针指向存储单元的数据,另一片处于仅写入状态数据存储区写满后数据溢出; [0007] When the data storage area is full, start reading and outputting the read pointer in the output state of the data storage area to the storage unit of data, another piece in the state data is written only after the data storage area filled with overflow;

[0008] 当输出数据相对于输入数据的延迟需要进行调整时,在继续对输出状态的数据存储区进行读取的同时,对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度为目标延时长度;待重新设置后的处于仅写入状态的数据存储区重新写满后,根据时序切换两片数据存储区的状态。 [0008] When the output data with respect to the input data delay needs to be adjusted in the state continues to output the data storage area for reading the same time, in the only state of the data written to the storage area were emptied and reset the data storage the length of the target area is the length of the delay; in only after the state of the data written to the storage area to be re-set after the re-filled, according to the timing of the switching state two pieces of data storage area. [0009] 本发明为了克服现有延迟线延迟时间更改切换占用系统处理时间,降低系统工作效率的不足,充分考虑到FIFO的工作特点,采用两个相同结构的FIFO数据存储区,按不同延迟时间要求来设置并选择不同数据存储区对应的通道来输出数据,当一个通道在进行重新设置时,另一个通道还在不间断输出数据,当通道重新设置并写满时,系统切换两个通道的状态,读取最新设置的数据存储区的数据,使得从该数据存储区对应通道的输入数据与输出数据之间的延时满足当前要求并避免了数据存储区切换导致系统出现等待数据输出的空闲状态。 [0009] The present invention, in order to overcome the existing delay line switching delay time change occupation system processing time, reduce the efficiency of the inadequate system, fully taking into account the characteristics of FIFO work, using the FIFO data storage area two identical structures, different delay times requirements and select a different set of data storage area corresponding to the output data channel, when a channel during the re-set, another channel output data is still ongoing, and reset when the channel is full, the system switches both channels data state, read the latest set of data storage area, so the delay from the data storage area corresponding to the channel between the input data and output data to meet current requirements and avoid the data storage area cause the system to switch idle waiting for data output state.

[0010] 更进一步的,为了使得本发明的延时的实时性最强,输出数据相对于输入数据的延迟需要进行调整的时机为:根据目标运动规律与数据存储区切换所需的系统处理时间,在目标延时变化之前,预先对处于仅写入状态的数据存储区进行清空并重新设置该数据存储区的长度,使得状态切换完成后该数据存储区开始输出数据时,输出数据相对于输入数据满足当前时刻对应的变化后目标延时。 [0010] Further, in order to make real-time delay of the present invention the strongest, the output data with respect to the input data of the delay time needs to be adjusted as follows: the processing time required for the switching system according to the movement of the target data storage area Before the target delay variation, in advance of the state of the data is only written to memory area cleared and re-set the length of the data storage area, making the state after completion of the handover of the data storage area starts to output data, output data relative to the input After the data to meet the current time delay corresponding change targets. 即,在目标延时变化之前,根据数据存储区切换所需的系统处理时间提前开始进行数据存储区切换处理,待数据存储区切换完成后,输出数据的延时满足变化后的目标延时要求。 That is, before the target delay variation, based on the data storage area switching system processing time required for data store in advance to start the switching process, the data to be stored after handover completion, the target to meet the changed delay output data latency requirements .

[0011] 本发明的有益效果是,通过两个结构相同的FIFO数据存储区的交替设置与交替输出实现不同延迟输出的无缝切换,可以更好地模拟出真实的回波环境。 [0011] The present invention is a beneficial effect by alternately arranged with the same two alternating output FIFO data structure store seamlessly switch between different output delays can better simulate the real echo environment.

附图说明 Brief Description

[0012] 图1为现有FPGA芯片实现数字延迟的示意图; [0012] Figure 1 is a conventional FPGA chip schematic diagram of the digital delay;

[0013] 图2为实施例FPGA芯片实现数字延迟的示意图。 [0013] FIG. 2 as an example embodiment of digital delay FPGA chip. Fig.

具体实施方式 DETAILED DESCRIPTION

[0014] 如图2所示,实现数字延迟线需要用到:1、两个可预置数据存储区大小的FIFO,用于保存输入数据;用于将带延迟的数据分送到两个这数据存储区的分线器;多路模拟开关MUX,用于选择不同数据存储区对应通道的数据作为输出数据。 [0014] 2, the digital delay line need to use: 1, two data storage areas can be preset size FIFO, to store the input data; Delayed data for distribution to the two that splitter data storage area; multi-channel analog switch MUX, used to select different data storage area corresponding to the data path as the output data. FIFO采用FPGA的IP核实现。 FIFO using FPGA IP core implementation. FIFO数据区大小采用USEDW信号设置。 FIFO data area size using USEDW signal settings. FIFO数据区清空采用CLR信号控制。 FIFO data area emptied using CLR signal.

[0015] 基于FPGA的双通道无缝数字延迟实现方法,以模拟的回波环境中目标的运动越来越近,回波信号时延逐渐减小为例,步骤如下: [0015] FPGA-based seamless dual-channel digital delay implementation, in order to simulate the movement of the target echo environment is getting closer, the echo signal delay decreases, for example, as follows:

[0016] 步骤一、设置两片FIFO数据存储区的初始大小,FIF01设置长度为N,FIF02设置长度为N-1。 [0016] Step one, set the initial size of the two FIFO data storage area, FIF01 set the length of N, FIF02 set the length of N-1. FIFO的存取方式:连续写入时,数据依序输入写指针指向的存储单元;读取时,从读指针指向的存储单元读取数据,设置数据存储区长度后,输出数据延迟时间与存储区长度对应。 FIFO access mode: Continuous writing, the write data is sequentially input pointer points to the memory cell; reading, data is read from the memory cell read pointer, after setting the length of the data storage area, and storing the output data delay time the length of the corresponding region.

[0017] 步骤二、输入数据依序同时送入FIF01和FIF02,直至数据区被写满。 [0017] Step two, the input data sequentially and simultaneously fed FIF01 FIF02, until the data area is full.

[0018] 步骤三、数据写满后,由MUX根据当前的目标延迟值选择从FIF01或FIF02读指针指向的存储单元读取数据。 [0018] Step three, after the data filled by the MUX delay depending on the current target value of the selected memory cell from FIF01 or FIF02 read pointer to read the data.

[0019] 当选择某一片FIFO进行读取数据,则MUX将开通该FIFO的输出通道,即该FIFO处于数据输出的状态;另一片FIFO数据不能输出,处于仅写入状态,数据写满后溢出。 [0019] When selecting a piece of FIFO read data, the MUX will open the FIFO output channels, that is, the data output FIFO in the state; another piece of data can not be output FIFO, write only in the state, after the data is filled with overflow . 选择由FIF01读数时,输出数据相对于输入数据延迟N个时钟周期;选择由FIF02读数时,输出数据相对于输入数据延迟N-1个时钟周期。 When selecting the reading from FIF01, output data with respect to the input data is delayed by N clock cycles; selected from FIF02 reading, the output data with respect to the input data delayed N-1 clock cycles. [0020] 步骤四、如当前选择FIF02进行数据输出。 [0020] Step Four, as the current selection FIF02 data output. 在对FIF02读数的同时,根据目标运动规律,下一次时延调整所需延迟由N-1个时钟周期调整为N-2个时钟周期,此时可通过控制信号CLR将FIFOl清空,设置USEDW,使得FIFOl数据存储区长度为N-2,待FIFOl重新写满后,根据时序切换为由FIFOl输出,输出数据相对于输入数据延迟N-2个时钟周期。 In FIF02 readings simultaneously, according to the movement of the target, the next time delay to adjust the desired delay by N-1 clock cycles is adjusted to N-2 clock cycles, this time by the control signal CLR will FIFOl empty, set USEDW, such FIFOl datastore length N-2, After FIFOl again filled, according to the timing switch grounds FIFOl output, the output data with respect to the input data delayed N-2 clock cycles.

[0021] 步骤五、当输出数据相对于输入数据的延迟需由N-2调整为N-3个时钟周期时,可在对FIFOl读数的同时,通过控制信号CLR将FIF02清空,设置USEDW,使得FIF02数据存储区长度为^3,待FIF02重新写满后,根据时序切换为由FIF02输出,输出数据相对于输入数据延迟N-3个时钟周期。 [0021] Step five, when the output data is delayed with respect to the input data required by the adjustment of N-2 N-3 clock cycles, the reading in of FIFOl same time, through the control signal CLR will FIF02 empty, set USEDW, such that FIF02 datastore length ^ 3, to be re-filled FIF02, according to the timing switch grounds FIF02 output, the output data with respect to the input data delay N-3 clock cycles.

[0022] 通过交替设置、切换FIFOl与FIF02,可实现信号时延由N_3个时钟周期到I个时钟周期的变化。 [0022] By alternately setting, switching FIFOl with FIF02, signal delay by N_3 clock cycles to clock cycles I change can be realized.

[0023] 达到需调整的时延后,停止切换FIFO工作状态。 [0023] is to be adjusted to achieve the delay, stop switch FIFO state.

[0024] 经过上述步骤处理,即可得到符合延时要求的输出信号,由于两个不同延迟时间的延迟输出分别由两片FIFO实现,并通过切换开关进行选择,可实现无缝延迟,避免系统出现等待数据输出的空闲状态。 [0024] After the above steps, you can get the output signals meet the delay requirements, due to the delay of the output of two different delay times, respectively, by two FIFO implementation, and selected by the switch, enabling seamless delay, to avoid the system appears idle state waiting for data output.

[0025] 可选的,在步骤一中,对数据存储区的初始大小进行设置时,两片FIFO的长度也可以设置为相同或不同长度。 [0025] Alternatively, in step 1, when the initial size of the data storage area is set, the length of two FIFO can also be set to the same or different lengths. 如设置为不同长度,两片FIFO的长度之差可以是延迟调整的步长,实施例中设置的延迟调整步长为I个时钟周期,当然也不仅限于此,可以根据实际需求将2或3甚至更长的时钟周期作为延迟调整步长。 If set to different lengths, the length difference between two of the FIFO may be delay adjustment step size, embodiment of the delay step size set for the I clock cycles, of course, not limited thereto, according to the actual needs of the 2 or 3 As the clock cycle even longer delay adjustment step.

[0026] 可选的,在步骤三中,实施例MUX对初始化之后的两片FIFO进行第一读取选择是在FIFO写满之后。 [0026] Alternatively, in step three, the embodiment of the MUX selection after the first reading in the FIFO is full initialization performed after two FIFO. 同样的,也可以在两片FIFO初始设置时默认某一片FIFO为初始读取的对象,默认其为输出状态,当该FIFO写满后对该FIFO读指针指向存储单元进行读取并由MUX开通该FIFO的输出通道。 Similarly, you can also default when two objects in a FIFO initial settings for the initial read a FIFO, which is the default output state when the FIFO is full of the FIFO read pointer to the memory cell is read by the MUX opened The FIFO output channel.

[0027] 用于选择不同数据存储区对应通道的数据作为输出数据的模块不限于现多路模拟开关MUX还可以是其它相同选择功能的模块。 [0027] is used to select different data storage area corresponding to the data path as the module output data is not limited to the current multi-channel analog MUX switch can also select other same module. 甚至,这个选择模块可以同时接收来自两个FIFO对应通道的数据,再根据目标延时选择输出一个通道(输出状态)的数据,丢弃另一个通道(仅写入状态)的数据。 Indeed, the selection module can simultaneously receive data from two FIFO corresponding channel, and then select the output channel (output state) based on objective data latency, dropped another channel (write status only) data.

[0028] 实施例 [0028] Example

[0029] 采用雷达信号模拟器作为平台,根据模拟目标与雷达的相对位置和目标的运动方式,从目标进入雷达波束主瓣到目标离开雷达波束主瓣,一共收到M个回波脉冲。 [0029] The radar signal simulator as a platform, according to the movement simulation and radar target relative position and goals, leaving the main lobe of the radar beam from the target into the main lobe of the radar beam to the target, has received a total of M-echo pulse. 其第一个脉冲重复周期的回波信号与发射信号间的延迟为500时钟周期,第二个脉冲重复周期的回波信号与发射信号间的延迟为499时钟周期,以此类推,第M个回波信号与发射信号间的延迟为500-M+1个时钟周期,因此需设置的FIFO大小为50(T500-M+1。 Delayed echo signals and transmitting a first signal whose pulse repetition period of 500 clock cycles between the delay signal and transmitting the echo signal of the second pulse repetition period between the 499 clock cycles, and so, the M-th the delay between the transmitted signal and the echo signal is 500-M + 1 clock cycles, so the FIFO size should be set to 50 (T500-M + 1.

[0030] 步骤一、设置两片FIFO数据存储区的大小,FIF01设置长度为500,FIF02设置长度为499。 [0030] Step one, set the size of two FIFO data storage area, FIF01 set the length to 500, FIF02 set the length to 499.

[0031] 步骤二、数据依序同时送入FIF01和FIF02,直至数据区被写满。 [0031] Step two, the data sequentially and simultaneously fed FIF01 FIF02, until the data area is full.

[0032] 步骤三、数据写满后,根据模拟目标与雷达的相对位置和目标的运动方式,由选择开关选择首先从FIF01中读取数据,输出数据相对于输入数据延迟500个时钟周期;当目标延迟需要调整为499时,由选择开关选择从FIF02中读取数据,输出数据相对于输入数据延迟499个时钟周期。 [0032] Step three, after the data is filled, according to the movement simulation and radar target relative position and goals, first read the data from the FIF01 by the selector switch, the output data with respect to the input data delayed 500 clock cycles; when delay needs to be adjusted to the target 499, the selection by the selection switch to read data from FIF02, the output data is delayed with respect to the input data 499 clock cycles. [0033] 步骤四、根据实施例假设条件,在对FIF02读数的同时,下一次所需时延应调整为498,则通过控制信号CLR将FIFOl清空,设置USEDW,使得FIFOl数据存储区减少2个长度单位,待FIFOl重新写满后,根据时序切换为由FIFOl输出,输出数据相对于输入数据延迟498个时钟周期。 [0033] Step four, according to an embodiment assumptions, in the reading of FIF02 while next 498 should be adjusted to the desired time delay, the control signal CLR will FIFOl empty, set USEDW, such FIFOl datastore reduction 2 After the length of the unit, to be re-filled FIFOl, according to the timing switch grounds FIFOl output, the output data with respect to the input data delay 498 clock cycles.

[0034] 步骤五、在对FIFOl读数的同时,下一次所需时延应调整为497,则通过控制信号CLR将FIF02清空,设置USEDW,使得FIF02数据存储区减少两个单元,待FIF02重新写满后,根据时序切换为由FIF02输出,输出数据相对于输入数据延迟497个时钟周期。 [0034] Step five, at the same time for FIFOl reading next time delay should be adjusted to the required 497, the control signal CLR will FIF02 empty set USEDW, making FIF02 data storage area is reduced by two units, to be re-written FIF02 After full, according to the timing switch grounds FIF02 output, the output data with respect to the input data delay 497 clock cycles.

[0035] 步骤六、交替进行步骤四和步骤五,可实现信号时延由498个时钟周期到50(T500-M+1个时钟周期的变化。 [0035] Step six, alternating Step Four and Step five, the signal delay can be achieved by 498 clock cycles to 50 (T500-M variation + 1 clock cycle.

[0036] 本领域的普通技术人员将会意识到,这里所述的实施例是为了帮助读者理解本发明的实施方法,应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。 [0036] ordinary skill in the art will recognize that the embodiment described herein is to help the reader understand the embodiment of the method of the invention, it should be understood that the scope of the present invention is not limited to such embodiments specifically stated and cases. 本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合,这些变形和组合仍然在本发明的保护范围内。 Of ordinary skill in the art may be made without departing from the spirit of the invention various other modifications and combinations of various specific teachings of the present invention based on these technologies disclosed, such modifications and combinations are still within the scope of the present invention.

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