CN102736985A - Data merging method, controller and storage device - Google Patents
Data merging method, controller and storage device Download PDFInfo
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- CN102736985A CN102736985A CN2011100838068A CN201110083806A CN102736985A CN 102736985 A CN102736985 A CN 102736985A CN 2011100838068 A CN2011100838068 A CN 2011100838068A CN 201110083806 A CN201110083806 A CN 201110083806A CN 102736985 A CN102736985 A CN 102736985A
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Abstract
The invention provides a data merging method, a controller and a storage device, wherein the data merging method is used for merging the data belonging to a first logic block in a rewritable nonvolatile memory module. The method comprises a step of selecting a second physical block from the physical blocks of an idle region of the rewritable nonvolatile memory module and judging whether the amount of valid logical pages corresponding to the first logic block is less than the predefined amount. The method further comprises the following steps of: when the amount of the valid logical pages corresponding to the first logic block is less than the predefined amount, storing a corresponding page mapping table in a start physical page of the second physical block, and writing at least one valid page data belonging to the first logic block into at least one physical page of the second physical block. Hence, the method can effectively reduce the time for executing data merging.
Description
Technical field
The present invention relates to a kind of Memory Controller and memorizer memory devices that is used for the data merging method of duplicative non-volatility memorizer module and uses the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, make the consumer also increase rapidly the demand of Storage Media.Because characteristics such as duplicative non-volatility memorizer (rewritablenon-volatile memory) has that data are non-volatile, power saving, volume are little, do not have mechanical structure, read or write speed is fast are suitable for portable electronic product most, for example notebook computer.Solid state hard disc is exactly a kind of with the storage device of flash memory module as Storage Media.Therefore, the flash memory industry becomes a ring quite popular in the electronic industry in recent years.
Flash memory module has a plurality of physical blocks (physical block), and each physical blocks has a plurality of physical page (physical page), must write data in order according to the order of physical page when wherein in physical blocks, writing data.In addition, after must being wiped free of earlier, the physical page that has been written into data could be used to write data once more.Particularly, physical blocks is the least unit of wiping, and physical page is the minimum unit of stylize (also claiming to write).Therefore, in general, in the management of flash memory module, physical blocks is divided into data field (data area) and idle district (free area) to I haven't seen you for ages.
The physical blocks of data field (also being called the data entity block) is in order to store the stored data of host computer system.Specifically, memory management circuitry can convert the logic access address of host computer system institute access into the logical page (LPAGE) of blocks and the logical page (LPAGE) of blocks mapped to the physical page of the physical blocks of data field.That is to say that in the management of flash memory module, the physical blocks of data field is to be regarded as the physical blocks that has been used (for example, stored host computer system write data).For example, memory management circuitry can use blocks-physical blocks mapping table to put down in writing the mapping relations between the physical blocks of blocks and data field, and wherein the logical page (LPAGE) in the blocks is the physical page of the physical blocks of shining upon of correspondence in regular turn.
The physical blocks (also being called idle physical blocks) in idle district is in order to the physical blocks in the data field of rotating.Specifically, as stated, just can be used to write data once more after the physical blocks of written data must be wiped free of, and the physical blocks in idle district is to be designed to write Update Information to replace the physical blocks of original mapping logic block.Base this, the physical blocks in idle district be sky or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.
That is to say that the data field is to come the logical page (LPAGE) of mapping logic block with the mode of rotating with the physical page of the physical blocks in idle district, to store the data that host computer system was write.
For example; When host computer system is desired to write the logic access address that upgrades page data and is a certain logical page (LPAGE) of a certain blocks of corresponding storage device; The memory management circuitry of storage device can be extracted daily record (log) physical blocks of a physical blocks as corresponding this blocks from idle district; And this is Updated Information writes in the physical page of daily record physical blocks so far, shortens thus and carries out the time that writes instruction.Afterwards, when the physical blocks in idle district exhausted soon, memory management circuitry can be carried out data to this blocks and merge (Merge) program.For example; In the data consolidation procedure; Memory management circuitry can be extracted a physical blocks as the new data physical blocks from idle district, all up-to-date page datas that will belong to this blocks write so far in the new data physical blocks and with this blocks physical blocks so far that remaps.
As stated; In the data consolidation procedure, memory management circuitry must be with all data-movings (that is, duplicating) that belong to same blocks to empty physical blocks; Thus, carrying out the data consolidation procedure can be quite consuming time and influence the access usefulness of flash memory device.Therefore, shortening and carry out the data required time of consolidation procedure, is the target that these those skilled in the art endeavour.
Summary of the invention
The present invention provides a kind of data merging method, Memory Controller and memorizer memory devices, and it can effectively shorten carries out the data required time of consolidation procedure.
Exemplary embodiment of the present invention proposes a kind of data merging method; Be used for merging the data that belong to first blocks at the non-volatile memory module of duplicative; Wherein this duplicative non-volatility memorizer module has a plurality of physical blocks, and each physical blocks has a plurality of physical page of arranging in regular turn, and these physical blocks are grouped into data field and idle district at least; The physical blocks of data field is shone upon a plurality of blocks; Each blocks has a plurality of logical page (LPAGE)s, and above-mentioned first blocks is one of them of these blocks, and first physical blocks among the physical blocks in the first blocks mapping (enum) data district.Notebook data merging method comprises that whether effective logical page (LPAGE) number of from the physical blocks in idle district, selecting second physical blocks and judging corresponding first blocks is less than defining number in advance.Notebook data merging method also comprises; When effective logical page (LPAGE) number of corresponding first blocks when defining number in advance, write at least one physical page of second physical blocks at least one effective page data that opens the stored logic page in the beginning physical page and change the physical page mapping table and will belong to first blocks of second physical blocks.Notebook data merging method also comprises first blocks is remapped to second physical blocks.At this; Above-mentioned effective page data belongs at least one effective logical page (LPAGE) of first blocks, and logical page (LPAGE) changes that the physical page mapping table writes down effective logical page (LPAGE) of first blocks and in order to the mapping relations between the physical page that writes effective page data.
In one embodiment of this invention; The step that above-mentioned effective page data that will belong to first blocks writes in the part physical page of second physical blocks comprises: be connected in the above-mentioned beginning physical page that opens, effective page data that will belong to first blocks writes in the physical page of second physical blocks.
In one embodiment of this invention; Above-mentioned data merging method also comprises: after effective page data that will belong to first blocks write in the physical page of second physical blocks, to shine upon the storing state of second physical blocks of first blocks be the part effective status to mark in blocks-physical blocks mapping table.
In one embodiment of this invention, above-mentioned data merging method also comprises: discern at least one invalid logical page (LPAGE) among the logical page (LPAGE) of first blocks according at least one housekeeping instruction.
In one embodiment of this invention; Above-mentioned data merging method also comprises; When effective logical page (LPAGE) number of corresponding first blocks is not less than when defining number in advance, many page datas that will belong to first blocks write in the physical page of second physical blocks in order.
In one embodiment of this invention; Above-mentioned data merging method also comprises; When effective logical page (LPAGE) number of corresponding first blocks when defining number in advance; Second physical blocks open that the storage entities page changes the logical page (LPAGE) mapping table in the beginning physical page, wherein this physical page is changeed logical page (LPAGE) mapping table record in order to the mapping relations between effective logical page (LPAGE) of the physical page that writes effective page data and first blocks.
Exemplary embodiment of the present invention proposes a kind of Memory Controller; Be used to control duplicative non-volatility memorizer module; Wherein this duplicative non-volatility memorizer module has a plurality of physical blocks, and each physical blocks has a plurality of physical page of arranging in regular turn.This Memory Controller comprises main frame interface, storer interface and memory management circuitry.The main frame interface is in order to be electrically connected to host computer system.The storer interface is in order to be electrically connected to duplicative non-volatility memorizer module.Memory management circuitry is electrically connected to main frame interface and storer interface, and in order in the non-volatile memory module of duplicative, to merge the data that belong to first blocks.At this; Memory management circuitry is grouped into data field and idle district at least with these physical blocks; And dispose the physical blocks of a plurality of blocks with the mapping (enum) data district; Wherein each blocks has a plurality of logical page (LPAGE)s, and above-mentioned first blocks is one of them of these blocks, and first physical blocks in the first blocks mapping (enum) data district.In addition, memory management circuitry is selected second physical blocks from the physical blocks in idle district, and whether effective logical page (LPAGE) number of judging corresponding first blocks is less than defining number in advance.When this effective logical page (LPAGE) number of corresponding first blocks when defining number in advance, memory management circuitry writes at least one physical page of second physical blocks at least one effective page data that opens the stored logic page in the beginning physical page and change the physical page mapping table and will belong to first blocks of second physical blocks.Moreover; Memory management circuitry remaps first blocks to second physical blocks; Wherein above-mentioned effective page data belongs at least one effective logical page (LPAGE) among the logical page (LPAGE) of first blocks, and logical page (LPAGE) changes that the physical page mapping table writes down effective logical page (LPAGE) of first blocks and in order to the mapping relations between the physical page that writes effective page data.
In one embodiment of this invention, above-mentioned memory management circuitry is connected in and opens the beginning physical page, and effective page data that will belong to first blocks writes in the physical page of second physical blocks.
In one embodiment of this invention; After effective page data that will belong to first blocks write in the physical page of second physical blocks, the storing state that memory management circuitry mark in blocks-physical blocks mapping table shines upon second physical blocks of first blocks was the part effective status.
In one embodiment of this invention, above-mentioned memory management circuitry is discerned at least one invalid logical page (LPAGE) among the logical page (LPAGE) of first blocks according at least one housekeeping instruction that comes from host computer system.
In one embodiment of this invention; When effective logical page (LPAGE) number of corresponding first blocks is not less than when defining number in advance, many page datas that memory management circuitry will belong to first blocks write in the physical page of second physical blocks in order.
In one embodiment of this invention; When effective logical page (LPAGE) number of corresponding first blocks when defining number in advance; Memory management circuitry more second physical blocks open that the storage entities page changes the logical page (LPAGE) mapping table in the beginning physical page, wherein this physical page is changeed logical page (LPAGE) mapping table record in order to the mapping relations between effective logical page (LPAGE) of the physical page that writes effective page data and first blocks.
Exemplary embodiment of the present invention proposes a kind of memorizer memory devices, its packet gateway, duplicative non-volatility memorizer module and Memory Controller.Connector is in order to be electrically connected to host computer system.Duplicative non-volatility memorizer module has a plurality of physical blocks, and wherein each physical blocks has a plurality of physical page of arranging in regular turn.Memory Controller is electrically connected to connector and duplicative non-volatility memorizer module, and in order in the non-volatile memory module of duplicative, to merge the data that belong to first blocks.At this; Memory Controller is grouped into data field and idle district at least with these physical blocks; And dispose the physical blocks of a plurality of blocks with the mapping (enum) data district; Wherein each blocks has a plurality of logical page (LPAGE)s, and above-mentioned first blocks is one of them of these blocks, and first physical blocks in the first blocks mapping (enum) data district.In addition, Memory Controller is selected second physical blocks from the physical blocks in idle district, and whether effective logical page (LPAGE) number of judging corresponding first blocks is less than defining number in advance.When effective logical page (LPAGE) number of corresponding first blocks when defining number in advance, Memory Controller writes at least one physical page of second physical blocks at least one effective page data that opens the stored logic page in the beginning physical page and change the physical page mapping table and will belong to first blocks of second physical blocks.Moreover; Memory Controller remaps first blocks to second physical blocks; Wherein above-mentioned effective page data belongs at least one effective logical page (LPAGE) among the logical page (LPAGE) of first blocks, and logical page (LPAGE) changes that the physical page mapping table writes down effective logical page (LPAGE) of first blocks and in order to a plurality of mapping relations between the physical page that writes effective page data.
In one embodiment of this invention, above-mentioned Memory Controller is connected in and opens the beginning physical page, and effective page data that will belong to first blocks writes at least one physical page of second physical blocks.
In one embodiment of this invention; Above-mentioned wherein after effective page data that will belong to first blocks writes in the physical page of second physical blocks, the storing state that Memory Controller mark in blocks-physical blocks mapping table shines upon second physical blocks of first blocks is the part effective status.
In one embodiment of this invention, above-mentioned Memory Controller is discerned at least one invalid logical page (LPAGE) among the logical page (LPAGE) of first blocks according at least one housekeeping instruction that comes from host computer system.
In one embodiment of this invention, when effective logical page (LPAGE) number of corresponding first blocks is not less than when defining number in advance, many page datas that Memory Controller will belong to first blocks write in the physical page of second physical blocks in order.
In one embodiment of this invention; When effective logical page (LPAGE) number of corresponding first blocks when defining number in advance; Memory Controller more second physical blocks open that the storage entities page changes the logical page (LPAGE) mapping table in the beginning physical page, wherein this physical page is changeed logical page (LPAGE) mapping table record in order to the mapping relations between effective logical page (LPAGE) of the physical page that writes effective page data and first blocks.
Based on above-mentioned, the data merging method of exemplary embodiment of the present invention, Memory Controller and memory storage dress make and can shorten the time of carrying out the data consolidation procedure effectively.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Figure 1A is that exemplary embodiment shows host computer system and memorizer memory devices according to the present invention.
Figure 1B is the synoptic diagram of exemplary embodiment showed according to the present invention computer, input/output device and memorizer memory devices.
Fig. 1 C is another exemplary embodiment showed according to the present invention the host computer system and the synoptic diagram of memorizer memory devices.
Fig. 2 is the summary block scheme that shows the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary block scheme of the Memory Controller that exemplary embodiment showed according to the present invention.
Fig. 4 A and Fig. 4 B are the synoptic diagram of the physical blocks of exemplary embodiment institute display management duplicative non-volatility memorizer module according to the present invention.
Fig. 5～Fig. 7 is the example that writes data to duplicative non-volatility memorizer module that exemplary embodiment showed according to the present invention.
Fig. 8 is the example of the execution data consolidation procedure that exemplary embodiment showed according to the present invention.
Fig. 9 and Figure 10 are the examples that changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table according to the logical page (LPAGE) that state showed shown in Figure 8.
Figure 11 is that the physical page that shows according to another example is changeed the logical page (LPAGE) mapping table.
Figure 12 is another example of the execution data consolidation procedure that exemplary embodiment showed according to the present invention.
Figure 13 is the process flow diagram of the exemplary embodiment institute data presented merging method according to the present invention.
Reference numeral:
1000: host computer system
1100: computer
1102: microprocessor
1104: RAS
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: carry-on dish
1214: memory card
1216: solid state hard disc
1310: digital camera
The 1312:SD card
The 1314:MMC card
1316: memory stick
The 1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104: Memory Controller
106: duplicative non-volatility memorizer module
202: memory management circuitry
204: the main frame interface
206: the storer interface
252: memory buffer
254: electric power management circuit
256: bug check and correcting circuit
502: the data field
504: idle district
506: system region
508: replace the district
410 (0)～410 (N): physical blocks
610 (0)～610 (H): blocks
710 (0)～710 (K): logic access address
S1301, S1303, S1305, S1307, S1309, S1311, S1313: the step that data merge
Embodiment
Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative non-volatility memorizer module and controller (also claiming control circuit).Usually memorizer memory devices is to use with host computer system, so that host computer system can write to memorizer memory devices or reading of data from memorizer memory devices with data.
Figure 1A is host computer system and the memorizer memory devices that exemplary embodiment showed according to the present invention.
Please with reference to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprise microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 like Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is that other elements that see through data transmission interface 1110 and host computer system 1000 electrically connect.Can data be write to memorizer memory devices 100 or reading of data from memorizer memory devices 100 by microprocessor 1102, RAS 1104 with the running of input/output device 1106.For example, memorizer memory devices 100 can be carry-on dish 1212, memory card 1214 or solid state hard disc (Solid StateDrive, SSD) the duplicative non-volatility memory storage device of 1216 grades shown in Figure 1B.
Generally speaking, host computer system 1000 can be to cooperate any system with storage data with memorizer memory devices 100 substantially.Though in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be systems such as digital camera, video camera, communicator, message player or video signal player in another exemplary embodiment of the present invention.For example; In host computer system is digital camera (video camera) 1310 o'clock, and the duplicative non-volatility memory storage device then is its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (shown in Fig. 1 C).Embedded storage device 1320 comprise the built-in multimedia card (Embedded MMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the summary block scheme that shows the memorizer memory devices shown in Figure 1A.
Please with reference to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and duplicative non-volatility memorizer module 106.
In this exemplary embodiment, connector 102 is to be compatible to serial advanced annex (SerialAdvanced Technology Attachment, SATA) standard.Yet; It must be appreciated, the invention is not restricted to this, connector 102 can also be to meet Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers; IEEE) 1394 standards, high-speed peripheral part linkage interface (Peripheral Component Interconnect Express; PCI Express) standard, USB (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) Interface Standard, memory stick (Memory Stick; MS) Interface Standard, Multi Media Card (Multi Media Card; MMC) Interface Standard, compact flash (Compact Flash, CF) Interface Standard, integrated driving electronic interface (Integrated DeviceElectronics, IDE) standard or other standards that is fit to.
Duplicative non-volatility memorizer module 106 is to be electrically connected to Memory Controller 104, and has a plurality of physical blocks to store the data that host computer system 1000 is write.In this exemplary embodiment, each physical blocks has a plurality of physical page respectively, and the physical page that wherein belongs to same physical blocks can be write independently and side by side wiped.For example, each physical blocks is made up of 128 physical page, and the capacity of each physical page be 4 kilobyte (Kilobyte, KB).Yet, it must be appreciated that the invention is not restricted to this, each physical blocks is to be made up of 64 physical page, 256 physical page or other arbitrarily individual physical page.
More detailed, physical blocks is the least unit of wiping.That is each physical blocks contains the memory cell that is wiped free of in the lump of minimal amount.Physical page is the minimum unit that stylizes.That is, physical page is the minimum unit that writes data.Yet, it must be appreciated that in another exemplary embodiment of the present invention, the least unit that writes data can also be entity sector or other sizes.Each physical page generally includes data bit element district and redundant bit district.The data bit element district is in order to storage user's data, and redundant bit district is in order to the data (for example, bug check and correcting code) of stocking system.
In this exemplary embodiment, duplicative non-volatility memorizer module 106 is multistage memory cell (Multi Level Cell, MLC) a NAND flash memory module.Yet, the invention is not restricted to this, duplicative non-volatility memorizer module 106 also the single-order memory cell (Single Level Cell, SLC) NAND flash memory module, other flash memory module or other have the memory module of identical characteristics.
Fig. 3 is the summary block scheme of the Memory Controller that exemplary embodiment showed according to the present invention.
Please with reference to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, main frame interface 204 and storer interface 206.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to come real the work with the software pattern.For example, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and these steering orders are to be burned onto in this ROM (read-only memory).When memorizer memory devices 100 runnings, these steering orders can be carried out to carry out the runnings such as writing, read and wipe of data by microprocessor unit.
In another exemplary embodiment of the present invention; The steering order of memory management circuitry 202 can also the source code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the memory module) of duplicative non-volatility memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and RAS (not shown).Particularly; This ROM (read-only memory) has the sign indicating number of driving section; And when Memory Controller 104 was enabled, microprocessor unit can be carried out this driving yard steering order that section will be stored in the duplicative non-volatility memorizer module 106 earlier and be loaded in the RAS of memory management circuitry 202.Afterwards, microprocessor unit can turn round these steering orders to carry out the runnings such as writing, read and wipe of data.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be come real the work.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252.Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from duplicative non-volatility memorizer module 106.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically; When receiving, memory management circuitry 202 writes when instruction from host computer system 1000; Bug check can produce corresponding bug check and correcting code (ErrorChecking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256; ECC Code), and memory management circuitry 202 can corresponding these data that write instruction be write in the duplicative non-volatility memorizer module 106 with corresponding bug check and correcting code.Afterwards; When memory management circuitry 202 can read these data corresponding bug check and correcting code during reading of data simultaneously from duplicative non-volatility memorizer module 106, and bug check is understood according to this bug check and data execution error inspection and the correction program of correcting code to being read with correcting circuit 256.
Fig. 4 A and Fig. 4 B are the synoptic diagram of the physical blocks of exemplary embodiment institute display management duplicative non-volatility memorizer module according to the present invention.
Please with reference to Fig. 4 A; Duplicative non-volatility memorizer module 106 has physical blocks 410 (0)～410 (N), and the memory management circuitry 202 of Memory Controller 104 can logically be grouped into physical blocks 410 (0)～410-(N) data field (data area) 502, idle district (freearea) 504, system region (system area) 506 and replace district (replacement area) 508.
The physical blocks that belongs to data field 502 and idle district 504 in logic is the data that come from host computer system 1000 in order to storage.Specifically, the physical blocks of data field 502 (also being called the data entity block) is to be regarded as the physical blocks of storage data, and the physical blocks (also being called idle physical blocks) in idle district 504 is in order to write the physical blocks of new data.For example, when receiving the data that write instruction and desire to write from host computer system 1000, memory management circuitry 202 can be extracted physical blocks as daily record (log) physical blocks from idle district 504, and data are write in the daily record physical blocks so far.Again for example; When a certain blocks is carried out the data consolidation procedure; Memory management circuitry 202 can be extracted physical blocks and write data as the new data physical blocks of corresponding this blocks from idle district 504, and the data entity block of this blocks of the original mapping of replacement.
The physical blocks that belongs to system region 506 in logic is in order to the register system data.For example, system data comprises about the manufacturer of duplicative non-volatility memorizer module and model, the physical blocks number of duplicative non-volatility memorizer module, physical page number of each physical blocks etc.
Belonging to the physical blocks that replaces in the district 508 in logic is to be used for bad physical blocks to replace program, with replacing damaged physical blocks.Specifically, if replace when distinguishing the physical blocks damage that still has normal physical blocks and data field 502 in 508, memory management circuitry 202 meetings normal physical blocks of extraction from replace district 508 is changed the physical blocks of damage.
Based on above-mentioned, in the running of memorizer memory devices 100, data field 502, idle district 504, system region 506 can dynamically change with the physical blocks that replaces district 508.For example, the physical blocks in order to the storage data of rotating can belong to data field 502 or idle district 504 with changing.
What deserves to be mentioned is that in this exemplary embodiment, memory management circuitry 202 is to be that unit manages with each physical blocks.Yet, the invention is not restricted to this, in another exemplary embodiment, memory management circuitry 202 also can be grouped into a plurality of solid elements with physical blocks, and is that unit manages with the solid element.For example, each solid element can be made up of at least one physical blocks in same storer submodule or the different memory submodule.
Please with reference to Fig. 4 B; Memory management circuitry 202 can configuration logic blocks 610 (0)～610 (H) with the physical blocks in mapping (enum) data district 502, wherein each blocks has a plurality of logical page (LPAGE)s and these logical page (LPAGE)s are the physical page of shining upon corresponding data entity block in order.For example, when memorizer memory devices 100 was formatd, blocks 610 (0)～610 (H) is the physical blocks 410 (0)～410 (F-1) in mapping (enum) data district 502 initially.
In exemplary embodiment of the present invention, memory management circuitry 202 meeting service logic block-physical blocks mapping tables (logical block-physical block mapping table) are with the mapping relations between the physical blocks of record blocks 610 (0)～610 (H) and data field 502.In addition; Because host computer system 1000 with logic access address (for example is; Sector (Sector)) for unit comes access data, memory management circuitry 202 can convert the logic access address 710 (0)～710 (K) of corresponding stored device storage device 100 to corresponding logical page (LPAGE) when host computer system 1000 access datas.For example; When host computer system 1000 is desired a certain logic access of access address; Memory management circuitry 202 can convert the logic access address of 1000 accesses of host computer system into the multidimensional address that blocks and logical page (LPAGE) with correspondence are constituted, and through blocks-physical blocks mapping table access data in the physical page of correspondence.
In exemplary embodiment of the present invention, when memorizer memory devices 100 was formatd, the memory management circuitry 202 initially storing state of all physical blocks of mapping logic block 610 (0)～610 (H) was labeled as " void in whole state ".Specifically, as stated, the physical blocks of data field 502 can be regarded as the physical blocks of storage data.Yet in fact, when memorizer memory devices 100 was formatd, blocks 610 (0)～610 (H) was not used for storage data.Therefore, the page data on the physical page of all physical blocks of mapping logic block 610 (0)～610 (H) initially is all the invalid page data.For example; The storing state of the physical blocks that memory management circuitry 202 can be shone upon blocks in blocks-physical blocks mapping table is labeled as " void in whole state ", and the logical page (LPAGE) of these blocks can be marked as " invalid logical page (LPAGE) ".
Through after the above-mentioned initialize routine, the instruction that writes that memorizer memory devices 100 just can receive host computer system 1000 writes data.
Fig. 5～Fig. 7 is the example that writes data to duplicative non-volatility memorizer module that exemplary embodiment showed according to the present invention.At this, the storing state of the physical blocks that the logic of propositions block is shone upon initially is all " void in whole state ".
Please with reference to Fig. 5; When blocks 610 (0) be map to physical blocks 410 (0) and Memory Controller 104 from host computer system 1000, receive indication write data to blocks 610 (0) the 2nd～4 logical page (LPAGE) write instruction the time, memory management circuitry 202 can be to map to physical blocks 410 (0) and from idle district 504, extract (or selection) physical blocks 410 (F) to write effective page data of the 2nd～4 logical page (LPAGE) that belongs to blocks 610 (0) as the daily record physical blocks according to blocks-physical blocks mapping table recognition logic block 610 (0) at present.For example, memory management circuitry 202 data in can the 2nd～4 physical page of record physical blocks 410 (0) have been updated and effective page data of upgrading is to be stored in the 0th～2 physical page of physical blocks 410 (F).At this, host computer system 1000 writes data to the 2nd～4 logical page (LPAGE) of blocks 610 (0), and therefore, memory management circuitry 202 can be labeled as the 2nd～4 logical page (LPAGE) of blocks 610 (0) " effectively logical page (LPAGE) ".
Please with reference to Fig. 6; When Memory Controller 104 under state shown in Figure 5 from host computer system 1000, receive indication write data to blocks 610 (0) the 6th logical page (LPAGE) write when instruction, memory management circuitry 202 can be to map to the daily record physical blocks that physical blocks 410 (0) and identification physical blocks 410 (F) are used as counterlogic block 610 (0) at present according to blocks-physical blocks mapping table recognition logic block 610 (0) at present.Base this, effective page data that memory management circuitry 202 can will belong to the 6th logical page (LPAGE) of blocks 610 (0) writes to physical blocks 410 (F) in order.Similarly, memory management circuitry 202 data in can the 6th physical page of record physical blocks 410 (0) have been updated and effective page data of upgrading is to be stored in the 3rd physical page of physical blocks 410 (F).Similarly, host computer system 1000 writes data to the 6th logical page (LPAGE) of blocks 610 (0), and therefore, memory management circuitry 202 can be labeled as the 6th logical page (LPAGE) of blocks 610 (0) " effectively logical page (LPAGE) ".
Please with reference to Fig. 7; When Memory Controller 104 under state shown in Figure 6 from host computer system 1000, receive indication write data to blocks 610 (0) the 0th logical page (LPAGE) write when instruction, memory management circuitry 202 can be to map to the daily record physical blocks that physical blocks 410 (0) and identification physical blocks 410 (F) are used as counterlogic block 610 (0) at present according to blocks-physical blocks mapping table recognition logic block 610 (0) at present.Base this, effective page data that memory management circuitry 202 can will belong to the 0th logical page (LPAGE) of blocks 610 (0) writes to physical blocks 410 (F) in order.Similarly, memory management circuitry 202 data in can the 0th physical page of record physical blocks 410 (0) have been updated and effective page data of upgrading is to be stored in the 4th physical page of physical blocks 410 (F).Similarly, host computer system 1000 writes data to the 0th logical page (LPAGE) of blocks 610 (0), and therefore, memory management circuitry 202 can be labeled as the 0th logical page (LPAGE) of blocks 610 (0) " effectively logical page (LPAGE) ".
What deserves to be mentioned is that in the file administration mechanism of the operating system of host computer system 1000, operating system is to see through FAT to manage the data that are stored in the storage device.Particularly; Carry out in the example of deletion running of data in operating system; Operating system only can be in FAT data in the logic access address of annotation desire deletion be invalid, promptly accomplish the running of deleted data, and can practically stored data not deleted.Afterwards, when the operation system desired in these logic access address, to write data, operating system can be write direct data.In this exemplary embodiment, memory management circuitry 202 can receive deletion record from host computer system 1000, wherein can put down in writing the information that the data in which logic access address have been deleted in this deletion record.For example; In this exemplary embodiment; The operating system of host computer system 1000 is a Microsoft's Window operating system 7, and Microsoft's Window operating system 7 is to see through arrangement (trim) instruction to transmit deletion record, and this housekeeping instruction can supported and discern in main frame interface 206 with memory management circuitry 202.
In this exemplary embodiment, when receiving housekeeping instruction, memory management circuitry 202 can be labeled as according to the logical page (LPAGE) that arrangement (trim) instruction will have been deleted " invalid logical page (LPAGE) ".Base this, in this exemplary embodiment, when a logical page (LPAGE) is marked as invalid logical page (LPAGE), represent that this logical page (LPAGE) do not write or be stored in data on this logical page (LPAGE) by host computer system 1000 deletion by host computer system 1000.
In this exemplary embodiment; Be that a blocks and corresponding data entity block thereof extract the running (like Fig. 5,6 and shown in Figure 7) that the daily record physical blocks writes data and be called unlatching (open) mother and child blocks; And former physical blocks (for example; Above-mentioned physical blocks 410 (0)) is called female physical blocks and daily record physical blocks (for example, above-mentioned physical blocks 410 (F)) is called the fructification block.
What deserves to be mentioned is that the number of physical blocks is limited in the idle district 504, base this, during memorizer memory devices 100 runnings, the group number of the mother and child blocks of unlatching also can be restricted.Therefore; When memorizer memory devices 100 receives when instruction of writing that comes from host computer system 1000; Reach in limited time if opened the group number of mother and child blocks, just can carry out this after the memory management circuitry 202 need execution data consolidation procedures (also be called and close mother and child blocks) and write instruction.
Fig. 8 is the example of the execution data consolidation procedure that exemplary embodiment showed according to the present invention, and it is presented at 202 pairs of blocks of memory management circuitry, 610 (0) execution data consolidation procedures under the state shown in Figure 7.
, be effective logical page (LPAGE) please because the partial logic page is only arranged in blocks 610 (0) with reference to Fig. 8.The base this; Memory management circuitry 202 can be extracted physical blocks 410 (F+1) as the new data physical blocks from idle district 504; Setting up logical page (LPAGE) changes the physical page mapping table and changes the logical page (LPAGE) mapping table with physical page, and effective page data that logical page (LPAGE) is changeed physical page mapping table, physical page commentaries on classics logical page (LPAGE) mapping table and belongs to blocks 610 (0) writes in the physical blocks 410 (F+1).
For example; Memory management circuitry 202 can be changeed the physical page mapping table with the logical page (LPAGE) of being set up and write in the 0th physical page of physical blocks 410 (F+1) with physical page commentaries on classics logical page (LPAGE) mapping table, and effective page data that will belong to the 2nd, 3,4,6 and 0 logical page (LPAGE) of blocks 610 (0) in order writes in the 1st～5 physical page of physical blocks 410 (F+1).At this, logical page (LPAGE) commentaries on classics physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table are in order to the mapping relations between the physical page of the logical page (LPAGE) of record blocks 610 (0) and physical blocks 410 (F+1).
Fig. 9 and Figure 10 are the examples that changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table according to the logical page (LPAGE) that state showed shown in Figure 8.
Please with reference to Fig. 9; See through logical page (LPAGE) and change physical page mapping table 902; Memory management circuitry 202 can know that effective page data of the effective logical page (LPAGE) (that is the 2nd, 3,4,6 and 0 logical page (LPAGE)) that belongs to blocks 610 (0) is to be stored in respectively in the physical blocks 410 (F+1) in that physical page.
Please with reference to Figure 10, seeing through physical page changes logical page (LPAGE) mapping table 904, and memory management circuitry 202 can know that the physical page of physical blocks 410 (F+1) is the effective page data that stores that logical page (LPAGE) that belongs to blocks 610 (0) respectively.
After accomplishing the writing of data, memory management circuitry 202 can be in blocks-physical blocks mapping table remaps blocks 610 (0) to the storing state of physical blocks 410 (F+1) and mark-up entity block 410 (F+1) and is " part effective status ".Afterwards; When if host computer system 1000 is desired to read the data of blocks 610 (0); Memory management circuitry 202 can be that the storing state that shines upon physical blocks 410 (F+1) and physical blocks 410 (F+1) is " part effective status " according to blocks-other blocks 610 (0) of physical blocks mapping expression at present; Thus, memory management circuitry 202 can read logical page (LPAGE) from the 0th physical page of physical blocks 410 (F+1) changes the physical page mapping table and comes reading of data according to the logical page (LPAGE) commentaries on classics physical page mapping table that is read.That is to say that in the physical blocks of " part effective status ", the page data right and wrong of the blocks of being shone upon are stored in order.Therefore, memory management circuitry 202 can be set up with the stored logic page changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table, so that the mapping relations between the recognition logic page and the physical page to be provided.
What deserves to be mentioned is that as stated, memory management circuitry 202 can be labeled as " invalid logical page (LPAGE) " according to the logical page (LPAGE) that housekeeping instruction will have been deleted.In exemplary embodiment of the present invention, memory management circuitry 202 can adjust in the lump physical page change the logical page (LPAGE) mapping table and will upgrade after physical page change the logical page (LPAGE) mapping table and be stored in the memory buffer 252, be beneficial to execution data consolidation procedure thus.
For example; Suppose under state shown in Figure 8; During the data of the 3rd logical page (LPAGE) of host computer system 1000 deletion blocks 610 (0), memory management circuitry 202 can physical page shown in Figure 10 be changeed logical page (LPAGE) mapping table 904 be adjusted to physical page commentaries on classics logical page (LPAGE) mapping table 904 shown in figure 11.Specifically; Memory management circuitry 202 can be searched the maximum physical page of numbering in the physical page that has data; With the mapping value of the physical page that is searched (that is the 5th physical page) copy to the logical page (LPAGE) (that is the 3rd logical page (LPAGE)) deleted thus the physical page of mapping (promptly; The 2nd physical page) and with the mapping value of the physical page that is searched (that is the 5th physical page) change null value into.The base this; When carrying out the data merging next time; Memory management circuitry 202 can copy to the page data in the 5th physical page in the 2nd physical page, so that the effective page data in the physical page is stored in order, can promote the efficient of reading of data thus.
Particularly, logical page (LPAGE) changes during storage area that physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table must take this physical blocks stores.Therefore, only when effective logical page (LPAGE) number of a blocks (that is, in blocks effectively the number of logical page (LPAGE)) when defining number in advance, data shown in Figure 8 merge mode and just can be performed.At this, define number in advance and be 1/2nd of the page number that is set to a physical blocks.Yet, it must be appreciated, the invention is not restricted to this.For example; In another exemplary embodiment of the present invention, this defines number in advance and can and be used to the stored logic page according to the page number of a physical blocks and change the physical page mapping table and set with the page number of the physical page of physical page commentaries on classics logical page (LPAGE) mapping table.For example, if when need using 1 physical page to come the stored logic page to change the physical page mapping table with physical page commentaries on classics logical page (LPAGE) mapping table, the above-mentioned number that defines in advance is that the page number of a physical blocks deducts 1 page number.
It must be appreciated that in this exemplary embodiment, as stated, physical page is changeed the logical page (LPAGE) mapping table and can be established to promote the efficient of reading of data.Yet; It must be appreciated; In another exemplary embodiment of the present invention; Also can only set up logical page (LPAGE) changes the physical page mapping table and is recorded in the mapping relations between the logical page (LPAGE) and physical page in the physical blocks of " part effective status ", changes the logical page (LPAGE) mapping table and need not to set up physical page.
Figure 12 is another example of the execution data consolidation procedure that exemplary embodiment showed according to the present invention; Effective page data that its hypothesis belongs to the 2nd, 3,4,6,0 logical page (LPAGE) of blocks 610 (0) has been stored in the data entity block (promptly; Physical blocks 410 (F+1)) in; The effective page data that belongs to the 1st, 5,7～(K-1) logical page (LPAGE)s of blocks 610 (0) has been stored in the daily record physical blocks (that is physical blocks 410 (F+2)) and memory management circuitry 202 needs blocks 610 (0) is carried out the data consolidation procedures.
Please with reference to Figure 12, effective logical page (LPAGE) number of memory management circuitry 202 meeting identification counterlogic blocks 610 (0) is not less than and defines number in advance.Base this, memory management circuitry 202 can be extracted physical blocks 410 (F+3) as the new data physical blocks from idle district 504, all effective page datas that will belong to blocks 610 (0) write in the physical blocks 410 (F+3).And; After accomplishing the writing of data, memory management circuitry 202 can be in blocks-physical blocks mapping table remaps blocks 610 (0) and is labeled as " all effective statuses " to physical blocks 410 (F+3) and with the storing state of physical blocks 410 (F+3).
Afterwards; When if host computer system 1000 is desired to read the data of blocks 610 (0); Memory management circuitry 202 can be that the storing state that shines upon physical blocks 410 (F+3) and physical blocks 410 (F+3) is " all effective statuses " according to the other blocks 610 (0) of blocks one physical blocks mapping expression at present; Thus, memory management circuitry 202 can be according to the direct reading of data of putting in order of the page.That is to say that when the storing state of data entity block was marked as " all effective statuses ", the logical page (LPAGE) of blocks was to shine upon the physical page of physical blocks in order according to putting in order.
Figure 13 is the process flow diagram of the exemplary embodiment institute data presented merging method according to the present invention, and it shows the step of a blocks of mapping data entity block (below be called first physical blocks) (below be called first blocks) being carried out the data consolidation procedure.
Please with reference to Figure 13, in step S1301, Memory Controller 104 can extract (or selection) physical blocks (below be called second physical blocks) from the physical blocks in idle district 504.And in step S1303, Memory Controller 104 judges that whether effective logical page (LPAGE) number of corresponding first blocks is less than defining number in advance.
If effective logical page (LPAGE) number of corresponding first blocks is when defining number in advance; In step S1305; Memory Controller 104 can change the physical page mapping table at opening of second physical blocks stores correspondence in the beginning physical page (that is the 0th physical page) logical page (LPAGE) and physical page is changeed the logical page (LPAGE) mapping table.Then, in step S1307, Memory Controller 104 can continue and open the beginning physical page, and the data that will belong to effective logical page (LPAGE) of first blocks write in the part physical page of second physical blocks.
Afterwards, in step S1309, Memory Controller 104 can be in blocks-physical blocks mapping table remaps first blocks and is labeled as the part effective status to second physical blocks and with the storing state of second physical blocks.
If effective logical page (LPAGE) number of corresponding first blocks is not less than when defining number in advance, in step S1311, the page data that Memory Controller 104 can will belong to first blocks writes in the physical page of second physical blocks in order.Afterwards, in step S1313, Memory Controller 104 can be in blocks-physical blocks mapping table remaps first blocks and is labeled as whole effective statuses to second physical blocks and with the storing state of second physical blocks.
In sum; The data merging method of exemplary embodiment of the present invention and the Memory Controller that uses the method and memorizer memory devices can be non-when all effective at the logical page (LPAGE) of blocks; When carrying out the data consolidation procedure, only move the partial page data (; Effective page data), thus, effectively shorten and carry out the required time of data merging.
Though the present invention discloses as above with embodiment, so it is not in order to limiting the present invention, any under the those of ordinary skill of technical field, when can doing a little change and retouching, and do not break away from the spirit and scope of the present invention.
Claims (18)
1. data merging method; Be used for merging the data that belong to one first blocks at the non-volatile memory module of a duplicative; Wherein this duplicative non-volatility memorizer module has a plurality of physical blocks; Each said physical blocks has a plurality of physical page of arranging in regular turn, and said physical blocks is grouped into a data field and an idle district at least, and the said physical blocks of this data field is shone upon a plurality of blocks; Each said blocks has a plurality of logical page (LPAGE)s; This first blocks is one of them of said blocks, and one first physical blocks among the said physical blocks of this this data field of first blocks mapping, and this data merging method comprises:
From the said physical blocks in this idle district, select one second physical blocks;
Whether judgement defines number less than one in advance to an effective logical page (LPAGE) number that should first blocks;
When this effective logical page (LPAGE) number that should first blocks is defined number in advance less than this, open at least one effective page data that stores a logical page (LPAGE) in the beginning physical page and change the physical page mapping table and will belong to this first blocks in one of this second physical blocks and write at least one physical page of this second physical blocks; And
This first blocks is remapped to this second physical blocks,
Wherein this at least one effective page data belong to this first blocks said logical page (LPAGE) at least one effective logical page (LPAGE),
Wherein this logical page (LPAGE) changes the mapping relations between this at least one physical page of this at least one effective logical page (LPAGE) and this second physical blocks of this first blocks of physical page mapping table record.
2. the step that data merging method according to claim 1, this at least one effective page data that wherein will belong to this first blocks write in this at least one physical page of this second physical blocks comprises:
Be connected in this and open the beginning physical page, this at least one effective page data that will belong to this first blocks writes in this at least one physical page of this second physical blocks.
3. data merging method according to claim 1 also comprises:
After this at least one effective page data that will belong to this first blocks write in this at least one physical page of this second physical blocks, a storing state of this second physical blocks of this first blocks of mark mapping was a part of effective status in one blocks-physical blocks mapping table.
4. data merging method according to claim 1 also comprises:
According at least one invalid logical page (LPAGE) among the said logical page (LPAGE) of at least one this first blocks of housekeeping instruction identification.
5. data merging method according to claim 1 also comprises:
When this effective logical page (LPAGE) number that should first blocks being not less than this defining number in advance, many page datas that will belong to this first blocks write in the said physical page of this second physical blocks in order.
6. data merging method according to claim 1 also comprises:
When this effective logical page (LPAGE) number that should first blocks is defined number in advance less than this, open at this of this second physical blocks and to store a physical page in beginning physical page and change the logical page (LPAGE) mapping table,
Wherein this physical page is changeed the mapping relations between this at least one effective logical page (LPAGE) of this at least one physical page and this first blocks of this second physical blocks of logical page (LPAGE) mapping table record.
7. Memory Controller; Be used to control a duplicative non-volatility memorizer module; Wherein this duplicative non-volatility memorizer module has a plurality of physical blocks, and each said physical blocks has in regular turn a plurality of physical page of arranging, and this Memory Controller comprises:
One main frame interface is in order to be electrically connected to a host computer system;
One storer interface is in order to be electrically connected to this duplicative non-volatility memorizer module; And
One memory management circuitry is electrically connected to this main frame interface and this storer interface, and in order in the non-volatile memory module of this duplicative, merging the data belong to one first blocks,
Wherein this memory management circuitry is grouped into a data field and an idle district at least with said physical blocks,
Wherein this memory management circuitry disposes a plurality of blocks shining upon the said physical blocks of this data field,
Wherein each said blocks has a plurality of logical page (LPAGE)s, and this first blocks is one of them of said blocks, and one first physical blocks among the said physical blocks of this this data field of first blocks mapping,
Wherein this memory management circuitry is selected one second physical blocks from the said physical blocks in this idle district,
Wherein this memory management circuitry is judged whether an effective logical page (LPAGE) number that should first blocks is defined number less than one in advance,
Wherein when this effective logical page (LPAGE) number that should first blocks is defined number in advance less than this; This memory management circuitry opens at least one effective page data that stores logical page (LPAGE) commentaries on classics physical page mapping table in the beginning physical page and will belong to this first blocks in one of this second physical blocks and writes at least one physical page of this second physical blocks
Wherein memory management circuitry remaps this first blocks to this second physical blocks,
Wherein this at least one effective page data belongs at least one effective logical page (LPAGE) among the said logical page (LPAGE) of this first blocks,
Wherein this logical page (LPAGE) changes the mapping relations between this at least one physical page of this at least one effective logical page (LPAGE) and this second physical blocks of this first blocks of physical page mapping table record.
8. Memory Controller according to claim 7; This memory management circuitry wherein; Be connected in this and open the beginning physical page, this at least one effective page data that will belong to this first blocks writes in this at least one physical page of this second physical blocks.
9. Memory Controller according to claim 7; Wherein after this at least one effective page data that will belong to this first blocks write in this at least one physical page of this second physical blocks, a storing state of this memory management circuitry this second physical blocks of this first blocks of mark mapping in one blocks-physical blocks mapping table was a part of effective status.
10. Memory Controller according to claim 7, wherein this memory management circuitry is according at least one invalid logical page (LPAGE) among the said logical page (LPAGE) of at least one this first blocks of housekeeping instruction identification that comes from this host computer system.
11. Memory Controller according to claim 7; Wherein when this effective logical page (LPAGE) number that should first blocks being not less than this defining number in advance, many page datas that this memory management circuitry will belong to this first blocks write in the said physical page of this second physical blocks in order.
12. Memory Controller according to claim 7; Wherein when this effective logical page (LPAGE) number that should first blocks is defined number in advance less than this; This memory management circuitry more opens at this of this second physical blocks and stores a physical page in beginning physical page and change the logical page (LPAGE) mapping table
Wherein this physical page is changeed the mapping relations between this at least one effective logical page (LPAGE) of this at least one physical page and this first blocks of this second physical blocks of logical page (LPAGE) mapping table record.
13. a memorizer memory devices comprises:
A connector is in order to be electrically connected to a host computer system;
One duplicative non-volatility memorizer module has a plurality of physical blocks, and wherein each said physical blocks has a plurality of physical page of arranging in regular turn; And
One Memory Controller is electrically connected to this connector and this duplicative non-volatility memorizer module, in order in the non-volatile memory module of this duplicative, merging the data belong to one first blocks,
Wherein this Memory Controller is grouped into a data field and an idle district at least with said physical blocks,
Wherein this Memory Controller disposes a plurality of blocks shining upon the said physical blocks of this data field,
Wherein each said blocks has a plurality of logical page (LPAGE)s, and this first blocks is one of them of said blocks, and one first physical blocks among the said physical blocks of this this data field of first blocks mapping,
Wherein this Memory Controller is selected one second physical blocks from the said physical blocks in this idle district,
Wherein this Memory Controller is judged whether an effective logical page (LPAGE) number that should first blocks is defined number less than one in advance,
Wherein when this effective logical page (LPAGE) number that should first blocks is defined number in advance less than this; This Memory Controller opens at least one effective page data that stores logical page (LPAGE) commentaries on classics physical page mapping table in the beginning physical page and will belong to this first blocks in one of this second physical blocks and writes at least one physical page of this second physical blocks
Wherein this Memory Controller remaps this first blocks to this second physical blocks,
Wherein this at least one effective page data belongs at least one effective logical page (LPAGE) among the said logical page (LPAGE) of this first blocks,
Wherein this logical page (LPAGE) changes the mapping relations between this at least one physical page of this at least one effective logical page (LPAGE) and this second physical blocks of this first blocks of physical page mapping table record.
14. memorizer memory devices according to claim 13; This Memory Controller wherein; Be connected in this and open the beginning physical page, this at least one effective page data that will belong to this first blocks writes in this at least one physical page of this second physical blocks.
15. memorizer memory devices according to claim 13; Wherein after this at least one effective page data that will belong to this first blocks write in this at least one physical page of this second physical blocks, a storing state of this Memory Controller this second physical blocks of this first blocks of mark mapping in one blocks-physical blocks mapping table was a part of effective status.
16. memorizer memory devices according to claim 13, wherein this Memory Controller is according at least one invalid logical page (LPAGE) among the said logical page (LPAGE) of at least one this first blocks of housekeeping instruction identification that comes from this host computer system.
17. memorizer memory devices according to claim 13; Wherein when this effective logical page (LPAGE) number that should first blocks being not less than this defining number in advance, many page datas that this Memory Controller will belong to this first blocks write in the said physical page of this second physical blocks in order.
18. memorizer memory devices according to claim 13; Wherein when this effective logical page (LPAGE) number that should first blocks is defined number in advance less than this; This Memory Controller more opens at this of this second physical blocks and stores a physical page in beginning physical page and change the logical page (LPAGE) mapping table
Wherein this physical page is changeed the mapping relations between this at least one effective logical page (LPAGE) of this at least one physical page and this first blocks of this second physical blocks of logical page (LPAGE) mapping table record.
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