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Publication numberCN102567778 A
Publication typeApplication
Application numberCN 201110450409
Publication date11 Jul 2012
Filing date29 Dec 2011
Priority date29 Dec 2011
Also published asCN102567778B
Publication number201110450409.X, CN 102567778 A, CN 102567778A, CN 201110450409, CN-A-102567778, CN102567778 A, CN102567778A, CN201110450409, CN201110450409.X
Inventors丁一, 张俊, 李晶, 王德明, 胡建国, 谭洪舟
Applicant广州中大微电子有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates
CN 102567778 A
Abstract
The invention discloses a radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates. The coding circuit comprises a counter unit, a coding mode selecting circuit, a coding state machine, a coding output control circuit and a byte coding control circuit, wherein the counter unit is used for receiving a system coding clock signal and outputting a counting signal to the coding mode selecting circuit; the coding mode selecting circuit is respectively connected with a double-speed selecting signal, a single and double subcarrier selecting signal and a rate selecting signal and used for outputting a counting signal for distinguishing multiple coding modes to the coding state machine; the coding state machine is used for receiving bit information from the byte coding control circuit and outputting a control signal to the coding output control circuit; and the coding output control circuit is connected with an analog front end of an RFID tag chip. The multiple coding modes are supported by the coding circuit, so that the area of the chip is reduced, the power consumption of a system is reduced, and the circuit is simple in structure, high in stability and convenient to maintain.
Claims(8)  translated from Chinese
1. 一种支持单双副载波和高低速率的RFID标签芯片编码电路,包括计数器单元(1)、 编码模式选择电路(2)、编码状态机(3)、编码输出控制电路(5)和字节编码控制电路(4), 所述计数器单元(1)接收系统编码时钟信号(cllencoder)并输出计数信号(cnt28、 cnt32)给编码模式选择电路(2),其特征在于:所述编码模式选择电路(2)分别连接有双速选择信号(fast_inv_read)、单双副载波选择信号(sub_carrier_flag)及速率选择信号(data_rate_flag),所述编码模式选择电路(2)输出用于区别多种编码模式的计数信号给编码状态机(3 ),所述编码状态机(3 )还接收来自字节编码控制电路(4 )的比特信息(cnt_ bit)并输出控制信号(doU_r)给编码输出控制电路(5),所述编码输出控制电路(5)与RFID标签芯片的模拟前端连接。 A sub-carrier and the level of support for single and double rate of RFID tag chip encoding circuit comprises a counter unit (1), the coding mode selection circuit (2), the code state machine (3), encoded output control circuit (5) and word coding control circuit section (4), (1) the receiving system clock signal counter unit encoding (cllencoder) and outputs the count signal (cnt28, cnt32) to the encoding mode selection circuit (2), characterized in that: said coding mode selection circuit (2) are connected to a double speed select signal (fast_inv_read), single and double subcarrier selection signal (sub_carrier_flag) and the rate selection signal (data_rate_flag), the coding mode selection circuit (2) outputs a difference between multiple encoding modes count signal to the encoder state machine (3), the coding state machine (3) also receives (4) of the control circuit from the byte code bits of information (cnt_ bit) and outputs a control signal (doU_r) to encode the output control circuit (5 ), the encoded output control circuit (5) is connected to an analog front-end chip of the RFID tag.
2.根据权利要求1所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述计数器单元(1)包括第一计数器(11)和第二计数器(12),系统时钟信号(elk)和编码使能信号(tX_en)相与后分别与第一计数器(11)和第二计数器(12)的输入端连接,所述第一、第二计数器(11、1幻的复位端还连接有来自编码状态机C3)的计数器复位信号(cnt_Clr),所述第一、第二计数器输出的计数信号(cnt28、cnt3》分别传输给所述编码模式选择电路O)的输入端。 The kind of support and the level of odd and even sub-carrier rate of RFID tag chip encoding circuit as claimed in claim 1, characterized in that: the counter unit (1) comprises a first counter (11) and a second counter (12 ), the system clock signal (elk) and encoding enable signal (tX_en) phase with the first counter (11) and a second counter (12) connected to the input terminal, the first and second counters (11, reset terminal further connected to a magic counter reset signal (cnt_Clr) from coding state machine C3), said first and second counter output count signal (cnt28, cnt3 "are transmitted to said coding mode selection circuit O) of input.
3.根据权利要求1所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路,其特征在于:所述编码输出控制电路(5)输入端分别连接有系统时钟第一分频信号(C1M8)、系统时钟第二分频信号(clk32)、编码使能信号(tX_en)及单双副载波选择信号(SUb_carrier_flag),控制端接收来自编码状态机(3)输出的控制信号(doU_r)。 3. A support according to odd and even sub-carriers and low rate of RFID tag chip encoding circuit as claimed in claim 1, characterized in that: the encoded output control circuit (5) inputs are connected to the system clock of the first divider signal (C1M8), the system clock of the second divided signal (clk32), encoding enable signal (tX_en) and even-odd sub-carrier selection signals (SUb_carrier_flag), terminated (3) output from the encoder state machine control signal (doU_r control ).
4.根据权利要求3所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码输出控制电路(包括一三输入与非门(II),系统时钟第一分频信号(clM8)、编码使能信号(tX_en)和单双副载波选择信号(SUb_carrier_flag)经所述三输入与非门(Il)连接有一多路选择器,所述多路选择器的另一输入端连接有一二输入与非门(14),所述二输入与非门(14)的一路信号来自系统时钟第二分频信号(clk32)、另一路为单双副载波选择信号(sub_carrier_flag)取反后与编码使能信号(tX_en)相或后得到的信号,所述多路选择器的选择控制端的输入信号为来自编码状态机C3)输出的控制信号(dou_r)ο A support according to odd and even sub-carriers and low rate of RFID tag chip encoding circuit according to claim 3, wherein: the coded output control circuit ( including a three-input NAND gate (II), system first frequency division clock signal (clM8), encoding enable signal (tX_en) and the odd and even sub-carrier selection signals (SUb_carrier_flag) via the three-input NAND gate (Il) connected with a multiplexer, said multiplexer the other input of the selector is connected to a two-input NAND gate (14), the two-input NAND gate (14) all the way to the second signal from the system clock frequency divided signal (clk32), another way for the odd and even deputy control signal (dou_r) signal carrier selection signal (sub_carrier_flag) and encoding enable signal is negated after (tX_en) phase or obtained by the multiplexer selection control terminal of the input signal from the encoder state machine C3) output ο
5.根据权利要求1所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述字节编码控制电路(4)采用位编码,接收来自编码状态机(的副载波计数信号(fS_num)并输出帧尾输出控制信号(eof_Start)给编码状态机(3)。 A support according to odd and even sub-carriers and low rate of RFID tag chip encoding circuit as claimed in claim 1, characterized in that: the byte encoding control circuit (4) digit code, the reception from the encoder state machine ( count subcarrier signal (fS_num) and outputs the frame end output control signal (eof_Start) to the encoder state machine (3).
6.根据权利要求5所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码状态机C3)根据来自编码模式选择电路O)的所述区别多种编码模式的计数信号和所述帧尾输出控制信号(eof_Start)切换状态。 A support according to odd and even sub-carriers and the low rate encoding circuit chip RFID tag according to claim 5, characterized in that: said coding state machine C3) in accordance with the difference from the coding mode selection circuit O) of the multi- count signal encoding schemes and the frame end output control signal (eof_Start) switching state.
7.根据权利要求6所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码状态机(3)的状态包括帧头状态、数据状态和帧尾状态,所述帧头状态的切换与帧尾状态的切换首尾对应。 A support according to odd and even sub-carriers and low rate of RFID tag chip encoding circuit as claimed in claim 6, wherein: the coded state machine (3) states include header status, data status and end of frame end to a corresponding switching state, the switching state of the header and the frame end state.
8.根据权利要求7所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码模式选择电路(支持多种编码模式编码,包括单副载波高速、单副载波低速、单副载波双高速、单副载波双低速、双副载波高速、双副载波低速。 A support according to claim Mono subcarriers and low rate of RFID tag chip encoding circuit 7, wherein: the coding mode selection circuit ( supports multiple encoding mode, including single sub-carrier high speed single subcarrier low, single subcarrier dual high-speed, single subcarrier double low, double subcarrier speed, low speed double subcarrier.
Description  translated from Chinese

一种支持单双副载波和高低速率的RFID标签芯片编码电 That supports single and double subcarriers and low rate of RFID tag chip coding circuit

Road

技术领域 Technical Field

[0001] 本发明涉及射频识别技术,尤其是一种RFID标签芯片编码电路。 [0001] The present invention relates to radio frequency identification technology, especially RFID tag chip encoding circuit. 背景技术 Background

[0002] 射频识别技术即RFID,是一种非接触的,能自动识别目标物体的通信技术。 [0002] The radio frequency identification technology that is RFID, is a non-contact communication technology can automatically identify the target object. 为了实现阅读器和标签芯片之间的可靠数据传输,不同的RFID技术其编码方法也有所不同,如符合IS0/IEC 15693协议的芯片采用脉冲位置编码和曼彻斯特编码、符合IS0/IEC 14443协议的芯片则采用曼彻斯特编码和改进型密勒编码。 In order to achieve reliable data transmission between the reader and the tag chip and different RFID technology is also different encoding methods, such as compliance with IS0 / IEC 15693 protocol chip pulse position encoding and Manchester encoding, in line with IS0 / IEC 14443 protocol chip Manchester encoding is used and modified Miller coding. 本发明将针对符合IS0/IEC 15693协议的编码电路。 The invention will be in line for IS0 / IEC 15693 protocol encoding circuit.

[0003] 从标签芯片(VICC)到阅读器(V⑶)有六种编码模式:单副载波高速、单副载波低速、双副载波高速、双副载波低速、单副载波双高速和单副载波双低速模式。 [0003] from the tag chip (VICC) to the reader (V⑶) six coding modes: single sub-carrier high-speed, single subcarrier low speed, double speed of subcarriers, subcarrier low speed double, single subcarrier dual high-speed and single subcarrier double low-speed mode. 每次通信可以选择任何一种编码方式,如果VICC编码电路对每种模式采用一个编码电路,那么必须要6 个编码电路,这样就会大大增加VICC的面积和功耗。 Each communication can choose any kind of coding, if VICC encoding circuit for each mode uses a coding circuit, it must be 6 encoding circuit, which would greatly increase the VICC area and power consumption.

[0004] 由于单副载波和双副载波采用不同的频率进行编码,前者编码数据频率采用fc/32 ;后者编码数据频率采用fc/32和fc/观两个频率,这就为编码带来难度,一般的做法都需要分别对单副载波和双副载波进行编码,因此至少需要两个独立的编码电路。 [0004] Since the single sub-carrier and dual subcarriers using different frequency coding, the former frequency encoded data using fc / 32; the latter frequency encoded data using fc / 32 and fc / view of two frequencies, which is encoded bring difficulty, the general practice must be made separately for single and double subcarrier subcarrier is encoded, so at least two separate encoding circuit.

发明内容 DISCLOSURE

[0005] 本发明要解决的技术问题是:本发明提供一种支持单双副载波和高低速率的RFID标签芯片编码电路,该编码电路能对多种不同模式进行编码。 [0005] The technical problem to be solved is: The present invention provides a support for single and double subcarriers and low rate of RFID tag chip coding circuit, the encoding circuit can be encoded on a variety of different modes.

[0006] 为了解决上述技术问题,本发明所采用的技术方案是: [0006] In order to solve the above problems, the technical aspect of the present invention is used:

本发明采用低功耗小面积的设计理念,只需要一个编码电路,就能对六种不同的编码模式进行选择编码。 The present invention uses a small area of low-power design, only one coding circuit can be for six different coding modes selected encoding. 本发明支持单双副载波和高低速率的RFID标签芯片编码电路,包括计数器单元、编码模式选择电路、编码状态机、编码输出控制电路和字节编码控制电路,所述计数器单元接收系统编码时钟信号并输出计数信号给编码模式选择电路,所述编码模式选择电路分别连接有双速选择信号、单双副载波选择信号及速率选择信号,所述编码模式选择电路输出用于区别多种编码模式的计数信号给编码状态机,所述编码状态机还接收来自字节编码控制电路的比特信息并输出控制信号给编码输出控制电路,所述编码输出控制电路与RFID标签芯片的模拟前端连接。 The present invention supports single and double subcarriers and low rate of RFID tag chip encoder circuit includes a counter unit, encoding mode selection circuit, state machine coding, coding and byte coding output control circuit control circuit, said counter unit receiving system encoded clock signal and outputs the count signal to the encoding mode selection circuit, said coding mode selection circuit are connected to the two-speed selection signal, odd and even sub-carrier selection signal and rate selection signal, the coding mode selection circuit output is used to distinguish multiple encoding modes count signal to the encoder state machine, the state machine also receives the encoded information bits from the byte codes and the control circuit outputs a control signal to the encoder output control circuit, the encoded output control AFE connection with the RFID tag chip.

[0007] 进一步作为优选的实施方式,所述计数器单元包括第一计数器和第二计数器,系统时钟信号和编码使能信号相与后分别与第一计数器和第二计数器的输入端连接,所述第一、第二计数器的复位端还连接有来自编码状态机的计数器复位信号,所述第一、第二计数器输出的计数信号分别传输给所述编码模式选择电路的输入端。 Are respectively connected to the input of the first counter and the second counter [0007] As a further preferred embodiment, the counter unit comprises a first counter and a second counter, and the system clock signal after the phase encoding enable signal, the First, the second counter is also connected to the reset terminal of the counter reset signal from the encoder state machine, said first and second counter output count signal respectively transmitted to said coding mode selection input of the circuit.

[0008] 进一步作为优选的实施方式,所述编码输出控制电路输入端分别连接有系统时钟第一分频信号、系统时钟第二分频信号、编码使能信号及单双副载波选择信号,控制端接收来自编码状态机输出的控制信号。 [0008] As a further preferred embodiment, the encoded output control circuit has an input terminal connected to a first frequency dividing the system clock signal, a second frequency dividing the system clock signal, and encoding enable signal to select odd and even sub-carrier signal, the control receives control signals from the encoder state machine outputs.

[0009] 进一步作为优选的实施方式,所述编码输出控制电路包括一三输入与非门,系统时钟第一分频信号、编码使能信号和单双副载波选择信号经所述三输入与非门连接有一多路选择器,所述多路选择器的另一输入端连接有一二输入与非门,所述二输入与非门的一路信号来自系统时钟第二分频信号、另一路为单双副载波选择信号取反后与编码使能信号相或后得到的信号,所述多路选择器的选择控制端的输入信号为来自编码状态机输出的控制信号。 [0009] Further, as a preferred embodiment, the encoded output control circuit includes a three-input NAND gate, the system clock is first divided signals, encoding enable signal and the odd and even sub-carrier signal by the selection of the three-input NAND gate connected to a multiplexer, and the other input of the multiplexer is connected to a two-input NAND gate, one signal of the two-input NAND gate of a second from the system clock frequency divided signal, the other way Select Mono subcarrier signal is inverted to obtain and encoding enable signal phase or after the signal, the multiplexer selection control terminal of the input signal is a control signal output from the encoder state machine.

[0010] 进一步作为优选的实施方式,所述字节编码控制电路采用位编码,接收来自编码状态机的副载波计数信号并输出帧尾输出控制信号给编码状态机。 [0010] As a further preferred embodiment, the control byte encoding bit coding circuit, receives from the subcarrier coding state machine count signal and outputs a control signal to the output end of frame coding state machine.

[0011] 进一步作为优选的实施方式,所述编码状态机根据来自编码模式选择电路的所述区别多种编码模式的计数信号和所述帧尾输出控制信号切换状态。 [0011] As a further preferred embodiment, the coding state machine in accordance with the difference from the coding mode selection circuit count signal of said plurality of coding modes and a control signal output end of frame switching state.

[0012] 进一步作为优选的实施方式,所述编码状态机的状态包括帧头状态、数据状态和帧尾状态,所述帧头状态的切换与帧尾状态的切换首尾对应。 [0012] As a further preferred embodiment, the state of the state machine includes header coded state, end to end data corresponding switching state and the frame end state, the switching state of the header and the frame end state.

[0013] 进一步作为优选的实施方式,所述编码模式选择电路支持多种编码模式编码,包括单副载波高速、单副载波低速、单副载波双高速、单副载波双低速、双副载波高速、双副载波低速。 [0013] As a further preferred embodiment, the coding mode selection circuit supports multiple coding mode, comprising a single sub-carrier high-speed, low-speed single subcarrier, subcarrier single double-speed, low-speed single subcarrier pair, double-speed subcarriers double subcarrier low.

[0014] 本发明的有益效果是:本发明RFID标签芯片编码电路采用编码模式选择电路实现了对多种编码模式的选择编码,节省了芯片面积、降低了系统功耗,并且通过一个编码状态机实现了编码电路中帧头、数据和帧尾多状态的切换,电路结构简单、稳定性高并且便于维护。 [0014] the beneficial effects of the present invention are: the present invention, an RFID tag chip coding circuit coding mode selection circuit to achieve a variety of coding modes selective encoding, saving chip area, lower power consumption, and by a coding state machine achieve a coding circuit header, data, and multi-state switching frame end, the circuit structure is simple, high stability and ease of maintenance.

附图说明 Brief Description

[0015] 下面结合附图对本发明的具体实施方式作进一步说明: 图1是本发明RFID标签芯片编码电路实施例的原理方框图; [0015] the following with reference to the specific embodiments of the present invention will be further illustrated: Figure 1 is a schematic block diagram of the present invention RFID tag chip encoder circuit of the embodiment;

图2是本发明编码电路中编码输出控制电路实施例的具体电路原理图; 图3是本发明编码电路中编码状态机实施例的状态转换图。 Figure 2 is a circuit of the present invention coding coded output control circuit of the embodiment of a specific circuit diagram; Figure 3 is a circuit of the present invention coding state transition diagram coding state machine embodiment.

具体实施方式 DETAILED DESCRIPTION

[0016] 本发明提供了一种支持单双副载波和高低速率的RFID标签芯片编码电路,该编码电路能够对六种编码方式进行帧格式的编码,并将编码结果输出给芯片模拟前端。 [0016] The present invention provides a support for the odd and even sub-carriers and low rate of RFID tag chip coding circuit, the circuit is capable of coding for six encoding encoding frame format and coding result to the analog front-end chip.

[0017] 参照图1,本发明编码电路包括计数器单元1、编码模式选择电路2、编码状态机3、编码输出控制电路5和字节编码控制电路4,计数器单元1接收系统编码时钟信号clk_ encoder并输出计数信号Cnt28、Cnt32给编码模式选择电路2,所述编码模式选择电路2分别连接有双速选择信号fast_inv_read、单双副载波选择信号Sub_carrier_flag及速率选择信号data_rate_flag,所述编码模式选择电路2输出用于区别多种编码模式的计数信号给编码状态机3,所述编码状态机3还接收来自字节编码控制电路4的比特信息cnt_bit并输出控制信号doU_r给编码输出控制电路5,所述编码输出控制电路5与RFID标签芯片的模拟前端连接并输出编码信号dout。 [0017] Referring to FIG. 1, the encoding circuit of the present invention comprises a counter unit, the coding mode selection circuit 2, a state machine 3 coding, the coding control circuit 5 and the output control circuit 4 byte encoding, the counter unit 1 receives the system clock signal encoded clk_ encoder and outputs the count signal Cnt28, Cnt32 for encoding mode selection circuit 2, the encoding mode selection circuit 2 are connected to a two-speed selection signal fast_inv_read, odd and even sub-carrier signal Sub_carrier_flag selection and rate selection signal data_rate_flag, the coding mode selection circuit 2 output count signal for distinguishing a plurality of coding modes to encode the state machine 3, the coding state machine control circuit 3 also receives a byte code from the bit information cnt_bit 4 and outputs a control signal to an encoder doU_r output control circuit 5, the analog front-end coding output control circuit 5 and the RFID tag chip connection and outputs the encoded signal dout.

[0018] 进一步,所述计数器单元1包括第一计数器11和第二计数器12,系统编码时钟信号clk_enc0der为系统时钟信号elk与编码使能信号tX_en经与门IlO相与后的输出。 [0018] Further, the counter unit 1 comprises a first counter 11 and second counter 12, the system clock signal clk_enc0der encoded system clock signal elk and encoding enable signal tX_en via the output phase of the rear gate IlO. 在编码使能信号tX_en为低电平时,与门IlO输出为低电平,这时系统编码时钟信号clk_ encoder无效,这种门控时钟可在没有编码请求时使编码电路不工作,可降低芯片的功耗。 In the encoding enable signal tX_en is low, the AND gate IlO output is low, then the system clock signal clk_ encoder encodes invalid, this gated clock can make coding circuit in the absence of a code request is not working, it can reduce the chip power consumption. 系统编码时钟信号cllencoder作为第一计数器11和第二计数器12的工作时钟,连接到第一计数器11和第二计数器12的时钟输入端。 The system clock signal coding cllencoder as the first counter 11 and second counter operating clock 12 connected to the first counter 11 and second counter clock input terminal 12. 编码使能信号tX_en连接到第一计数器11和第二计数器12的使能输入端,在编码使能时,使其工作,在没有编码请求时,关闭计数器。 TX_en encoding enable signal is connected to the first counter 11 and the second counter 12 is able to make input in coding enabled to make it work, in the absence of a code request to close the counter. 第一计数器11和第二计数器12的复位信号为Cnt_Clr,当编码状态机3发生状态跳变时,编码状态机3使能Cnt_Clr信号,使第一计数器11和第二计数器12复位,从而在下一个状态可利用这两个计数器重新计数。 The first counter 11 and the second counter reset signal 12 is Cnt_Clr, when coding state machine 3 transition occurs, the encoder state machine 3 enable Cnt_Clr signal, the first counter 11 and the second counter 12 is reset, so that the next the state can take advantage of these two counters count again.

[0019] 在介绍编码模式选择电路2之前,先介绍本发明提到的六种编码模式: [0019] In the presentation before the selection circuit 2 encoding mode, first introduced the present invention mentioned six coding modes:

对单副载波高速模式来说,其帧头(SOF)包含三个部分:非调制时间56. 64 μ S、频率为fc/32 (423. 75kHz)的M个脉冲、逻辑1以非调制时间18. 88 μ s开始,接着是频率为fc/32 (423. 75kHz)的8 个脉冲。 Single sub-carrier high-speed mode, its header (SOF) consists of three parts: the non-modulation time 56. 64 μ S, the frequency fc / 32 (423. 75kHz) of M pulses, logic 1 in a non-modulation time 18. 88 μ s start, followed by a frequency fc / 32 (423. 75kHz) of 8 pulses.

[0020] 对单副载波低速模式来说,其帧头(SOF)的三个部分分别是单副载波高速模式时间的4倍,第一部分非调制时间是226. 56 μ s,第二部分是96脉冲,第三部分逻辑1开始是75. 52 μ s的非调制时间,接着是32个脉冲。 [0020] The single subcarrier low-speed mode, its header (SOF) in three parts, respectively, four times the single subcarrier time high-speed mode, the first part of the non-modulation time is 226. 56 μ s, the second part is 96 pulse, the third part of the logic 1 starts is 75. 52 μ s unmodulated time, followed by 32 pulses.

[0021] 单副载波双速模式SOF的时间是各自高低速模式时间的二分之一。 [0021] The double-speed mode single subcarrier SOF was on half their time of high and low speed mode.

[0022] 双副载波高速模式的帧头(SOF)也包括三个部分:频率为fc/观的27个脉冲、频率为fc/32的M个脉冲、逻辑1以频率为fc/28的9个脉冲开始,接着是频率为fc/32的8个脉冲。 [0022] The double-speed mode subcarrier header (SOF) also consists of three parts: a pulse frequency of 27 fc / concept, frequency of M pulses fc / 32, and a logic 1 to the frequency fc / 28 9 pulse start, followed by a frequency fc / 32 of 8 pulses. 双副载波低速模式SOF的三个部分的时间是双副载波高速模式的4倍,分别是: 频率为fc/28的108个脉冲、频率为fc/32的96个脉冲、逻辑1以频率为fc/28的36个脉冲开始,接着是频率为fc/32的32个脉冲。 Time three parts of the low-speed mode double subcarrier SOF is four times subcarrier dual high-speed mode, namely: the frequency of 108 pulses fc / 28, the frequency of 96 pulses fc / 32, and a logic 1 to the frequency 36 pulses fc / 28 start, followed by a frequency fc / 32 of 32 pulses.

[0023] 上述六种模式的帧尾(EOF)是和各自的帧头(SOF)是首尾对应的,即它们SOF的第一部分是EOF的第三部分、SOF的第三部分是EOF的第一部分。 [0023] The end of the six modes of frame (EOF) is and respective header (SOF) is the corresponding end to end, that is the first part of the third part of their SOF EOF and SOF is the third part of the first part of EOF .

[0024] VICC到VCD的数据编码采用位编码。 [0024] VICC to VCD data encoding using bit encoding. 对单副载波模式来说,逻辑0以频率为fc/32 (约423. 75kHz)的8个(高速模式)或32个(低速模式)脉冲开始,接着是非调制时间256/fc (高速模式)或lOM/fc (低速模式)。 Single subcarrier mode, a logic 0 to the frequency fc / 32 (approximately 423. 75kHz) of eight (speed) or 32 (low-speed mode) pulse starts, followed by non-modulation time 256 / fc (high-speed mode) or lOM / fc (low-speed mode). 单副载波双速模式的逻辑0开始是4个(双高速模式)或16个(双低速模式)频率为fc/32的脉冲,接着是非调制时间U8/fc (双高速模式)或512/fc (双低速模式)。 Logic 0 single subcarrier double-speed mode is 4 (double speed) or 16 (dual low-speed mode) frequency fc / 32 pulses, then a non-modulation time U8 / fc (double speed) or 512 / fc (dual low-speed mode). 对双副载波,逻辑0以频率为fc/32的8个(高速模式)或32个(低速模式)脉冲开始,接着是频率为fc/28的9个(高速模式)或36个(低速模式)脉冲。 Double subcarrier frequency logic 0 to fc / 32 of 8 (high speed mode) or 32 (low-speed mode) pulse start, followed by a frequency of 9 (high-speed mode) fc / 28 or 36 (low-speed mode ) pulse. 逻辑1和各自模式的逻辑0相对应,即逻辑0的第一部分是逻辑1的第二部分,而其第二部分是逻辑1的第一部分。 Logic 1 and a logic 0 for each mode corresponding to, i.e. the first part of the logic 0 is a logic 1, the second part, while the second part is the first part 1 of the logic.

[0025]所述编码模式选择电路 2 的输出S0F_12_NUM、S0F_34_NUM、DATA_01、CNT_NUM、 CNT_DATA、cnt接编码状态机的输入端,这些输出信号都是用于区别各种编码模式的信息计数信号。 [0025] The encoding mode selection circuit 2 outputs S0F_12_NUM, input S0F_34_NUM, DATA_01, CNT_NUM, CNT_DATA, cnt pick coding state machine, these output signals are used to distinguish between the various count signal coding mode information. 其中,S0F_12_NUM是用于区别单双副载波帧头第一,第二部分高低速模式的副载波计数值,S0F_34_NUM是用于选择单双副载波帧头第三部分高低速模式的副载波计数值。 Wherein, S0F_12_NUM is the difference between single and double subcarrier header first, the second part of the count value subcarrier for high or low speed mode, S0F_34_NUM for subcarrier count value subcarrier choose single or double header part of the third high-low speed mode . DATA_01是用于选择单双副载波数据编码速率的计数值。 DATA_01 count value is used to select the single or double data subcarrier encoding rate. CNT_NUM、CNT_DATA用于对齐波形的计数值。 CNT_NUM, CNT_DATA count value for the alignment of the waveform. cnt用于选择各种编码模式的副载波类型的计数值,可以为cnt32或cnt28。 cnt is used to select the various coding modes count value subcarrier type, which can be cnt32 or cnt28. 当双速选择信号fast_inv_read为高电平且单双副载波信号sub_Carrier_f lag为低电平时, When the double-speed selection signal fast_inv_read is high and sub_Carrier_f lag odd and even sub-carrier signal is low,

5若速率选择信号data_rate_flag为“1”时,即选择单副载波双高速模式,则S0F_12_NUM值为12,S0F_34_NUM值为4 ;若速率选择信号data_rate_flag为“0”时,即选择单副载双波低速模式,则S0F_12_NUM值为48,S0F_34_NUM值为16。 5 If data_rate_flag rate selection signal is "1", that is select a single subcarrier dual high-speed mode, the S0F_12_NUM is 12, S0F_34_NUM value of 4; if data_rate_flag rate selection signal is "0", that is select a single subcarrier double wave the low-speed mode, the S0F_12_NUM is 48, S0F_34_NUM is 16. 当双速选择信号fast_inv_read和单双副载波信号sub_carrier_flag皆为低电平时,若速率选择信号data_rate_flag为高电平时,即选择单副载波高速模式,S0F_12_NUM值为24,S0F_34_NUM值为8 ;若速率选择信号data_rate_flag为低电平时,即选择单副载波低速模式,S0F_12_NUM值为96,S0F_34_NUM 值为32。 When the two-speed selection signal fast_inv_read and odd and even sub-carrier signal sub_carrier_flag both low, if the selection signal data_rate_flag rate is high, choose a single sub-carrier high-speed mode, S0F_12_NUM value of 24, S0F_34_NUM is 8; if rate selection data_rate_flag signal is low, choose single subcarrier low-speed mode, S0F_12_NUM value of 96, S0F_34_NUM is 32. 当双速选择信号fast_inv_read为低电平且单双副载波选择信号sub_Carrier_ flag为高电平时,若速率选择信号data_rate_flag为高电平时,即选择双副载波高速模式,S0F_12_NUM值为27,S0F_34_NUM值为9 ;若速率选择信号data_rate_f lag为低电平时, 即选择双副载波低速模式,S0F_12_NUM值为108,S0F_34_NUM值为36。 When the double-speed selection signal fast_inv_read low and odd and even sub-carrier selection signal sub_Carrier_ flag is high, if the selection signal data_rate_flag rate is high, choose double subcarrier speed mode, S0F_12_NUM value of 27, S0F_34_NUM value 9; if the rate selection signal data_rate_f lag is low, choose double subcarrier slow mode, S0F_12_NUM value of 108, S0F_34_NUM value of 36.

[0026] 所述编码状态机3输入端连接编码模式选择电路2的输出端。 [0026] The state machine coding 3 coding mode selection input connected the output of circuit 2. 编码状态机3的输出为控制信号dout_r、计数器复位信号Cnt_Clr、帧编码结束信号tX_0Ver、字节编码结束信号tX_empty、副载波计数信号fs_nUm。 Output coding state machine 3 is a control signal dout_r, counter reset signal Cnt_Clr, frame coding end signal tX_0Ver, byte coding end signal tX_empty, subcarrier count signal fs_nUm. 在编码状态机3的每个状态,当cnt计数到7时,副载波计数信号fS_num加1。 Each state in the state machine coding 3, when cnt count to 7, the subcarrier signal fS_num count is incremented. 参照图3,当编码状态机3处于S0F_1状态时,判断副载波计数信号fs_num的值是否为S0F_12_NUM,如果副载波计数信号fs_num值为S0F_12_NUM,帧尾输出控制信号eof_Start (该信号为帧尾输出控制信号,即数据编码完成后,该信号置为高电平,帧尾EOF开始输出)为低电平并且cnt的值为CNT_NUM时,状态机跳转到S0F_2状态, 否则就一直处于S0F_1状态,直到条件满足。 Referring to Figure 3, when the encoder state machine 3 is S0F_1 state determines subcarrier signal fs_num count value is a S0F_12_NUM, if subcarrier signal fs_num count value S0F_12_NUM, frame end output control signal eof_Start (the frame end signal output control signal, that is, after the completion of data coding, the signal is set high, the end of frame EOF start output) is low and the value of cnt CNT_NUM, the state machine jumps to S0F_2 state, or has been in S0F_1 until conditions. 当编码状态信号enCOder_State值为S0F_2, 即编码状态机3处于S0F_2状态时,判断副载波计数信号fs_num是否为S0F_12_NUM,cnt是否为CNT_NUM,若条件满足,且e0f_Start为低电平,状态跳转到S0F_3,否则一直等待直到条件满足。 When the encoder state signal enCOder_State value S0F_2, namely coding state machine 3 is S0F_2 state, the judge subcarrier count signal fs_num whether S0F_12_NUM, cnt whether CNT_NUM, if the conditions are met, and e0f_Start low, the state jumps to S0F_3 Otherwise, wait until the conditions are met. 当处于S0F_3状态时,判断副载波计数信号fs_num是否为SF0_34_NUM,cnt是否为CNT_NUM,若条件满足且e0f_Start为低电平状态跳转到S0F_4。 When in S0F_3 state determines subcarrier count signal fs_num whether SF0_34_NUM, cnt whether CNT_NUM, if the conditions are met and the low state e0f_Start jump to S0F_4. 在S0F_4状态,开始装载编码数据tX_data。 In S0F_4 state, start loading the encoded data tX_data. 当编码状态机3处于数据编码状态时,数据比特信息输出给dout_r, 作为编码输出控制电路5的控制信号。 When the encoder state machine 3 is data coding status, data bit information output to dout_r, the control circuit 5 as an encoded signal output control. 当编码状态机3处于数据编码状态DATA_1时,判断副载波计数信号fs_num是否为DATA_01,cnt是否为CNT_DATA,若满足,则跳转到数据编码状态DATA_2。 When the encoder state machine 3 is in data coding state DATA_1, judge subcarrier count signal fs_num whether DATA_01, cnt whether CNT_DATA, if met, then jump to the data coding state DATA_2. 在数据编码状态DATA_2,判断字节编码控制电路4输出的数据比特信息cnt_ bit是否为7,若为7表示一个字节的数据编码完成,发出字节编码结束信号tX_empty,通知发送下一字节编码数据,在下一个时钟周期,字节编码控制电路4判断数据装载信号tx_ load是否为高电平,若为高电平则接收编码数据,若为低,向编码状态机3发送帧尾输出控制信号eof_start,表示一帧数据编码完成,编码状态机转向S0F_4,开始发送帧尾EOF信息。 In the data coding state DATA_2, judging byte coding control circuit 4 outputs the data bit information cnt_ bit is 7, if it is 7 represents a byte of data encoding is complete, issue-byte coding end signal tX_empty, notification is sent to the next byte encoded data, the next clock cycle, byte coding control circuit 4 judges whether data loading signal tx_ load is high, if it receives the encoded data is high, if it is low, the state machine 3 transmits the encoded output frame end control signal eof_start, represents a data coding is complete, the coding state machine turned S0F_4, end of frame EOF start sending messages. 帧尾EOF与帧头SOF的数据正好相反,如前所述,SOF的第一部分是EOF的第三部分、 SOF的第三部分是EOF的第一部分,因此编码状态机3帧头SOF和帧尾EOF状态切换正好首尾对应,因而节省了系统的功耗和芯片面积。 End of frame EOF and SOF header data contrary, as mentioned above, the first part of the third EOF SOF is part of the third part is the first part of the SOF EOF, so coding state machine 3 and the frame header SOF tail EOF state switch just end to correspond, and thus saves system power consumption and chip area. 当状态编码机3按逆序执行完帧尾EOF的状态转换后,则转入OVER状态,表示帧编码结束,发出帧编码结束信号tX_0Ver,进一步转入IDLE状态等待下一帧数据编码。 When the STATUS coding machine 3 in reverse order executed end of frame EOF conversion, then transferred OVER state indicates the frame coding end, issue-frame coding end signal tX_0Ver, further into the IDLE state waiting for the next frame data encoding.

[0027] 参照图2,所述编码输出控制电路5输入端分别连接有系统时钟第一分频信号clk28、系统时钟第二分频信号clk32、编码使能信号tX_en及单双副载波选择信号sub_ Carrier_flag,控制端接收来自编码状态机3输出的控制信号doU_r。 [0027] Referring to FIG. 2, the encoder output control circuit 5 are respectively connected to the input terminal of the first frequency dividing the system clock signal clk28, second frequency dividing the system clock signal clk32, encoding enable signal tX_en and even-odd sub-carrier selection signal sub_ Carrier_flag, control terminal for receiving a control signal from the state machine coding doU_r 3 outputs. 所述编码输出控制电5包括一三输入与非门II,系统时钟第一分频信号clk28、编码使能信号tX_en和单双副载波选择信号Sub_carrier_flag经所述三输入与非门Il连接有一多路选择器,所述多路选择器的另一输入端连接有一二输入与非门14,所述二输入与非门14的一路信号来自系统时钟第二分频信号clk32、另一路为单双副载波选择信号SUb_carrier_flag取反后与编码使能信号tX_en相或后得到的信号,所述多路选择器的选择控制端的输入信号为来自编码状态机3输出的控制信号doU_r。 The encoded output control circuit 5 comprises a three-input NAND gate II, first dividing the system clock signal clk28, encoding enable signal tX_en and single and double subcarrier selection signals Sub_carrier_flag through the three-input NAND gate Il connected with a multiplexer, the other input of the multiplexer is connected to a two-input NAND gate 14, one signal of the two-input NAND gate 14, the second from the system clock frequency divided signal clk32, another way for the odd and even sub-carrier signal inverted select signal SUb_carrier_flag and encoding enable signal tX_en phase or obtained, the multiplexer selection control terminal of the input signal is output from the encoder state machine 3 control signals doU_r. 多路选择器的输出信号经过反相器15后输出为已编码数据dout。 Multiplexer output signal passes through the inverter 15 outputs the encoded data after dout. 当单双副载波选择信号sub_carrier_flag为低电平时,控制信号dout_r为低电平时,编码输出dout没有调制信息;控制信号dout_r为高电平时,编码输出dout输出系统时钟第二分频信号clk32。 When single and double subcarrier selection signal sub_carrier_flag is low, the control signal dout_r is low, the encoded output dout no modulation information; dout_r control signal is high, the output of the system clock encoded output dout second divided signal clk32. 当单双副载波选择信号SUb_carrier_flag为高电平时,控制信号高电平时,编码输出dout输出系统时钟第二分频信号clk32 ;当控制信号dout_r为低电平时,编码输出dout为系统时钟第一分频信号clk28。 When the odd and even sub-carrier selection signal SUb_carrier_flag is high, high level control signal, encoded output dout output system clock of the second divided signal clk32; dout_r when the control signal is low, the encoded output for the system clock dout first points frequency signal clk28.

[0028] 本发明所述字节编码控制电路4采用位编码,接收来自编码状态机3的副载波计数信号fs_nUm并输出帧尾输出控制信号eof_Start给编码状态机3。 [0028] The present invention uses byte coding control circuit 4-bit code is received from the encoder state machine subcarrier 3 fs_nUm count signal and outputs a control signal output end of the frame to the encoder state machine eof_Start 3. 所述编码状态机3根据来自编码模式输出电路2的所述区别多种编码模式的计数信号和所述帧尾输出控制信号eof_start切换状态。 The coding state machine 3 according to the difference between the output from the encoder circuit mode 2 multiple count signal coding mode and the frame end output control signal eof_start switching state.

[0029] 本发明编码电路支持支持多种编码模式编码,包括单副载波高速、单副载波低速、 单副载波双高速、单副载波双低速、双副载波高速、双副载波低速。 [0029] The present invention encoding circuitry supports multiple coding mode support, including single sub-carrier high-speed, single subcarrier low, single subcarrier dual high-speed, single subcarrier double low, double sub-carrier high speed, low speed double subcarrier. 第一计数器cnU8在单副载波模式下停止工作,第一计数器cnU8和第二计数器cnt32在双副载波模式下分时工作,节省了系统的编码功耗,并且本发明帧头SOF和帧尾EOF在同一编码状态机的不同状态工作顺序下实现,首尾对应,节省了芯片的面积。 The first counter cnU8 stop in single subcarrier mode, the first counter and the second counter cnt32 cnU8 sharing work in dual subcarrier pattern, saving the system of coding power, and the present invention and the frame header SOF EOF End In order to work under different conditions to achieve the same coding state machine corresponding end to end, saving chip area.

[0030] 以上是对本发明的较佳实施进行了具体说明,但本发明创造并不限于所述实施例,熟悉本领域的技术人员在不违背本发明精神的前提下还可以作出种种的等同变形或替换,这些等同的变形或替换均包含在本申请权利要求所限定的范围内。 [0030] The above is a preferred embodiment of the present invention have been specifically described, but the creation of the present invention is not limited to the embodiments, those skilled in the art without departing from the spirit of the present invention may be made provided all sorts of equivalent deformation or alternatively, such modifications or equivalent replacement are included within the application scope defined by the claims.

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Referenced by
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CN103647558A *3 Dec 201319 Mar 2014北京中电华大电子设计有限责任公司Manchester encoder circuit
Classifications
International ClassificationG06K19/077
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