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Publication numberCN102545908 B
Publication typeGrant
Application numberCN 201210004220
Publication date28 May 2014
Filing date9 Jan 2012
Priority date1 Dec 2011
Also published asCN102545908A, US8471744, US20130141264
Publication number201210004220.2, CN 102545908 B, CN 102545908B, CN 201210004220, CN-B-102545908, CN102545908 B, CN102545908B, CN201210004220, CN201210004220.2
Inventors温皓明, 王一涛, 陈桂枝
Applicant香港应用科技研究院有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Sigma-delta modulator with stable chopped wave
CN 102545908 B
Abstract  translated from Chinese
模数转换器(ADC)有斩波稳定∑Δ调制器(SDM)。 Digital converter (ADC) has ΣΔ chopper-stabilized modulator (SDM). SDM使用开关电容积分器去取样、保持和积分模拟输入,以响应非重叠多相位时钟。 SDM using switched capacitor integrator to sampling, maintenance and integration analog input, in response to the multi-phase non-overlapping clock. 在第一阶段积分器里的运算放大器的输入和输出上加入斩波乘法器。 In the first stage integrator in the op amp's input and output added multiplier on the chopper. 斩波乘法器交换或传输通过差分输入,以响应非重叠斩波时钟。 Chopper multiplier switching or transmission through differential input, in response to a non-overlapping chopper clock. 主时钟运行在多相位时钟的频率上,该频率除降后产生斩波时钟。 Master clock running at a frequency multi-phase clock generation chopping clock frequency divided after the fall. 延迟线保证斩波时钟边沿出现在多相位时钟边沿之前。 Delay line to ensure that the chopping clock edge occurs before the multi-phase clock edge. 当多相位时钟发生变化时,斩波乘法器已经切换并因此稳定了,所以由多相位时钟控制的开关上的电荷注入不会立刻被斩波乘法器调制。 When the multi-phase clock is changed, the chopper has been switched multipliers and therefore stable, so the multi-phase clock by the charge control switch on the injection is not immediately chopper modulation multiplier. 这样的计时安排增加了时间去响应开关上的电荷注入,提高了线性特征。 Such timing arrangement increases the time to respond to the charge injection switch improves the linear characteristic.
Claims(20)  translated from Chinese
1.一个斩波稳定Σ Δ调制器,包括: 第一取样保持积分模块,其接收模拟输入,并接收一差分反馈信号, 所述第一取样保持积分模块有第一取样电容器和第一相位开关和第一差分输出; 第一运算放大器,其有第一运算放大器差分输入和第一运算放大器差分输出; 第一斩波乘法器,其连接在所述第一差分输出和第一运算放大器差分输入之间,第一斩波乘法器将第一差分输出传输到第一运算放大器差分输入上,以响应第一斩波时钟,第一斩波乘法器交换来自第一差分输出的差分信号而驱动第一运算放大器差分输入,以响应第二斩波时钟; 第二斩波乘法器,其连接在第一运算放大器差分输出和一个中间差分信号之间,第二斩波乘法器将第一运算放大器差分输出传输到中间差分信号上,以响应第一斩波时钟,第二斩波乘法器交换来自第一运算放大器差分输出的差分信号以驱动中间差分信号,以响应第二斩波时钟; 第二取样保持积分模块,其接收中间差分信号,并接收所述差分反馈信号,第二取样保持积分模块有第二取样电容和第二相位开关和第二差分输出; 第二运算放大器,其接收所述第二差分输出并产生第二运算放大器差分输出; 均衡器,其将第二运算放大器差分输出转换为二进制比特,以产生所述差分反馈信号作为所述斩波稳定Σ Δ调制器的一个输出; 第一相位时钟应用在所述第一相位开关和所述第二相位开关上; 第二相位时钟应用在所述第一相位开关和所述第二相位开关上; 时钟产生器,其产生第一斩波时钟和第二斩波时钟,作为有第二频率的非重叠时钟,其还产生第一相位时钟和第二相位时钟,作为有第一频率的非重叠时钟,第一频率是第二频率的倍数,所述时钟产生器产生的第一和第二斩波时钟的边沿出现在第一和第二相位时钟边沿之前,第一相位时钟、第二相位时钟、第一斩波时钟、第二斩波时钟都在斩波时钟周期开始时变化; 由此,在斩波时钟周期里,斩波时钟边沿是在相位时钟边沿之前产生的。 1. A chopper-stabilized Σ Δ modulator, comprising: a first sample and hold integrator module that receives an analog input, and receives a differential feedback signal, said first sample and hold integrator module has a first sampling capacitor and a first phase switch and a first differential output; a first operational amplifier having a first differential input operational amplifier and the first differential output operational amplifier; a first chopper multiplier, which is connected to the first differential output of the first operational amplifier differential input between the first chopper first differential output multiplier will be transferred to the first operational amplifier differential input, in response to the first chopper clock multiplier first chopper switching differential signal from the first differential output to drive the first a differential input operational amplifier in response to a second chopper clock; a second chopper multiplier, which is connected between the first operational amplifier and a differential output intermediate differential signal, the second chopper differential multiplier of the first operational amplifier transferred to the intermediate differential output signal in response to a first clock chopper, a second chopper signal from the first multiplier switching differential outputs of the differential operational amplifier to drive an intermediate differential signals, in response to a second clock chopper; second sampling holding integration module, which receives the intermediate differential signal, and receiving the differential feedback signal, a second sample and hold integrator module has a second sampling capacitor and the second phase switch and the second differential output; the second operational amplifier, which receives the first two differential outputs and generating a second differential output of the operational amplifier; equalizer, which second differential operational amplifier output is converted to binary bits to generate said feedback signal as said differential chopper-stabilized Σ Δ modulator output; the first One phase of the clock used in the first phase of the switch and the second phase switch; a second phase of the clock used in the first phase of the switch and the second phase switch; a clock generator that generates a first cut wave clock and a second chopper clock, as there is a second non-overlapping clock frequency, which also generates a first phase and a second phase clock clock, as a first non-overlapping clock frequency, the first frequency is a second frequency The first and second chopper edge multiples, the clock generator generates the clock occurs before the first and second phase clock edge, the first phase of the clock, the second phase of the clock, the first chopper clock, second cut wave clock are changing chopping clock cycle; thus, the chopper clock cycle, chopping clock edge before the phase of the clock edge occurs.
2.如权利要求1所述的斩波稳定Σ Δ调制器,其中在第一取样保持积分模块里的第一相位开关切换状态之前,在第二取样保持积分模块里的第二相位开关切换状态之前,第一斩波乘法器和第二斩波乘法器互换差分信号; 由此,斩波乘法器在相位开关状态变化之前是稳定的。 2. The chopper-stabilized 1 Σ Δ modulator according to claim, wherein prior to the integral module of a first phase in a first switching state holding the sample, the second sample and hold integrator module in the second switching state phase Prior to the first and second chopper chopper multiplier multiplier interchanged differential signal; Thus, prior to the phase multiplier chopper switch state change is stable.
3.如权利要求2所述的斩波稳定Σ Δ调制器,其中时钟产生器还包括: 时钟分频器,其接收主时钟并将主时钟分频而产生分频时钟,主时钟运行在第一频率上; 第一非重叠时钟产生器,其接收主时钟,其产生第一相位时钟和第二相位时钟,其中第一相位时钟和第二相位时钟从不在同一时间处于活动状态; 第二非重叠时钟产生器,其接收主时钟,其产生第一斩波时钟和第二斩波时钟,其中第一斩波时钟和第二斩波时钟从不在同一时间处于活动状态。 According to claim 2, wherein the chopper steady Σ Δ modulator, wherein a clock generator further comprising: a clock divider, which receives the master clock and the master clock divider to generate a divided clock, the master clock runs in the first on a frequency; a first non-overlapping clock generator, which receives the master clock, which generates a first clock phase and second phase clock, wherein the first and second phase clock phase clock never active at the same time; the second non- overlapping clock generator that receives the master clock, which generate a first and a second chopper chopping clock clock, wherein the first and second chopper chopping clock clock never be active at the same time.
4.如权利要求3所述的斩波稳定Σ Δ调制器,其中第一非重叠时钟产生器有输入延迟,其用于延迟主时钟的边沿,保证第一相位时钟和第二相位时钟的边沿出现在由第二非重叠时钟产生器产生的第一斩波时钟和第二斩波时钟的边沿之后。 The chopper-stabilized 3 Σ Δ modulator according to claim, wherein the first non-overlapping clock generator has input delay, the delay for the master clock edge, to ensure a first edge and a second phase of the clock phase of the clock It appears after the edge is generated by the second non-overlapping clock generated by the first and second chopper chopping clock clock.
5.如权利要求2所述的斩波稳定ΣΛ调制器,其中每个差分信号包括真线(trueline)和补线(complement line),还包括: 第一真积分电容器,其连接在第一运算放大器差分输入和第一运算放大器差分输出的真线之间; 第一补积分电容器,其连接在第一运算放大器差分输入和第一运算放大器差分输出的补线之间; 第二真积分电容器,其连接在第二运算放大器差分输入和第二运算放大器差分输出的真线之间; 第二补积分电容器,其连接在第二运算放大器差分输入和第二运算放大器差分输出的补线之间。 5. ΣΛ chopper-stabilized modulator according to claim 2, wherein each of the differential signal comprises a true line (trueline) and complement lines (complement line), further comprising: a first true integration capacitor connected to the first computing between the amplifier and the true differential input differential output lines of the first operational amplifier; a first fill integrating capacitor connected between the first operational amplifier differential input and differential output of the first operational amplifier fill line; the second true integration capacitor, true line connected between the second operational amplifier differential input and differential output of the second operational amplifier; second complementary integration capacitor connected between the second operational amplifier differential input and differential output of the second operational amplifier fill line.
6.如权利要求5所述的斩波稳定Σ Δ调制器,其中第一取样保持积分模块还包括: 第一真取样电容器; 第一补取样电容器; 其中第一真取样电容器是第一取样电容器; 第一真输入相位开关,其于第一相位时钟处于活动状态时,连接所述模拟输入的真线到所述第一真取样电容器的前极板; 第一真固定相位开关,其于第一相位时钟处于活动状态时,应用一固定电压到所述第一真取样电容器的后极板上;` 第一真反馈相位开关,其于第二相位时钟处于活动状态时,连接所述差分反馈信号的真线到所述第一真取样电容器的前极板; 第一真连接相位开关,其于第二相位时钟处于活动状态时,连接第一真取样电容器的后极板到第一斩波乘法器的第一差分输出的真线上; 第一补输入相位开关,其于第一相位时钟处于活动状态时,连接所述模拟输入的补线到所述第一补取样电容器的前极板; 第一补固定相位开关,其于第一相位时钟处于活动状态时,应用所述固定电压到所述第一补取样电容器的后极板上; 第一补反馈相位开关,其于第二相位时钟处于活动状态时,连接所述差分反馈信号的补线到所述第一补取样电容器的前极板; 第一补连接相位开关,其于第二相位时钟处于活动状态时,连接第一补取样电容器的后极板到第一斩波乘法器的第一差分输出的补线上。 6. The chopper-stabilized 5 Σ Δ modulator according to claim, wherein the first sample and hold integrator module further comprises: a first sampling capacitor true; first fill sampling capacitor; wherein the first sampling capacitor is true first sampling capacitor ; first true input phase switch, which is active in the first phase of the clock, true line connected to the analog input of the front plate of the first true sampling capacitor; the first true fixed phase switch, which in the first a phase clock is active, a fixed voltage is applied to the first true after sampling capacitor plates; true when `a first feedback phase switch, which is active in the second phase clock, the differential feedback connection front plate real line signal to the first true sampling capacitor; the first real connection phase switch, which is active in the second phase clock, connecting the first true sampling capacitor plate after the first chopper The multiplier of the first differential line outputs true; the first fill phase input switch, which is active in the first phase of the clock, connect the analog input lines to complement the first pre-fill sampling capacitor plates ; the first complement fixation phase switch, which is active in the first phase of the clock, the fixed voltage applied to the sample after the first patch capacitor plates; first fill feedback phase switch, which in a second phase When the clock is active, up the line connecting the differential feedback signal to the first patch of the front plate of the sampling capacitor; the first phase switch up connection, it is active in the second phase of the clock, connect the first supplement After sampling capacitor plates to the first chopper differential output of the first multiplier fill line.
7.如权利要求6所述的斩波稳定Σ Δ调制器,其中第二取样保持积分模块还包括: 第二真取样电容器; 第二补取样电容器; 其中第二真取样电容器是第二取样电容器; 第二真输入相位开关,其于第一相位时钟处于活动状态时,连接所述中间差分信号的真线到所述第二真取样电容器的前极板; 第二真固定相位开关,其于第一相位时钟处于活动状态时,应用所述固定电压到所述第二真取样电容器的后极板上; 第二真反馈相位开关,其于第二相位时钟处于活动状态时,连接所述差分反馈信号的真线到所述第二真取样电容器的前极板; 第二真连接相位开关,其于第二相位时钟处于活动状态时,连接第二真取样电容器的后极板到第二运算放大器的第二差分输出的真线上; 第二补输入相位开关,其于第一相位时钟处于活动状态时,连接所述中间差分信号的补线到所述第二补取样电容器的前极板; 第二补固定相位开关,其于第一相位时钟处于活动状态时,应用所述固定电压到所述第二补取样电容器的后极板上; 第二补反馈相位开关,其于第二相位时钟处于活动状态时,连接所述差分反馈信号的补线到所述第二补取样电容器的前极板; 第二补连接相位开关,其于第二相位时钟处于活动状态时,连接第二补取样电容器的后极板到第二运算放大器的第二差分输出的补线上。 7. The chopper-stabilized 6 Σ Δ modulator according to claim, wherein the second sample and hold integrator module further comprises: a second real sampling capacitor; a second sampling capacitor complement; wherein the second sampling capacitor is really the second sampling capacitor ; the second true input phase switch, which is active in the first phase of the clock, true line connecting the intermediate differential signals to the front plate of the second real sampling capacitor; a second really fixed phase switch, which in the first phase clock is active, the fixed voltage applied to the rear of the second real sampling capacitor plates; second true feedback phase switch, which is active in the second phase clock, the differential connection true line of the feedback signal to the plate before the second real sampling capacitor; the second phase of the switch really connected, it is active in the second phase of the clock, connect a second real sampling capacitor plate after the second operation True second differential amplifier output line; the second phase up input switch, which is active in the first phase of the clock, connect up the line in the middle of the front plate of the differential signal to the second up sampling capacitor ; second complementary fixed phase switch, which is active in the first phase of the clock, the application of the fixed voltage to the sample after the second patch capacitor plates; second complementary feedback phase switch, which in a second phase When the clock is active, up the line connecting the differential feedback signal to the second up before sampling capacitor plates; the second phase switch up connection, it is active in the second phase of the clock, connect a second patch After the sample plate of the capacitor to the second operational amplifier second differential output up line.
8.如权利要求6所述的斩波稳定Σ Δ调制器,其中第一真输入相位开关、第一真固定相位开关、第一真反馈相位开关、第一真连接相位开关、第一补输入相位开关、第一补固定相位开关、第一补反馈相位开关、第一补连接相位开关,每个包括η沟道晶体管,其在η沟道晶体管的栅极上接收第一相位时钟或第二相位时钟。 8. The chopper as claimed in claim 6, wherein the stabilizing Σ Δ modulator, wherein the phase of the first true input switch, a first fixed phase switch really, really a first feedback phase switch, the first phase of real connection switch, a first input the complement phase switch, first make a fixed phase switch, first fill the feedback phase switch, first make the connection phase switch, each comprising η-channel transistor, which receives the first or second phase clock channel transistor in the gate η phase clock.
9.一个模数转换器ADC,包括: 时钟分频器,其将经过延迟的触发时钟分频,以产生有除降频率的分频时钟; 多相位非重叠时钟产生器,其接收延迟的触发时钟,触发产生第一相位时钟和第二相位时钟,第一相位时钟和第二相位时钟有非重叠及处于活动状态的脉冲,并在第一频率上运行,第一频率是所述除降频率的倍数; 斩波非重叠时钟产生器,其接收分频`时钟,触发产生第一斩波时钟和第二斩波时钟,第一斩波时钟和第二斩波时钟有非重叠及处于活动状态的脉冲,并在所述除降频率上运行;其中延迟的触发时钟触发所述多相位非重叠时钟产生器,转换第一相位时钟和第二相位时钟; 其中分频时钟触发所述斩波非重叠时钟产生器,转换第一斩波时钟和第二斩波时钟;其中第一斩波时钟和第二斩波时钟的边沿出现在斩波时钟周期要早于第一相位时钟和第二相位时钟的边沿,它们是被所述触发时钟的同一边沿触发的; 第一取样电容器,其有一前极板和一后极板; 第一输入晶体管开关,其栅极接收所述第一相位时钟,其沟道连接模拟信号到所述第一取样电容器的前极板; 第一反馈晶体管开关,其栅极接收所述第二相位时钟,其沟道连接反馈信号到所述第一取样电容器的前极板; 第一连接晶体管开关,其栅极接收所述第二相位时钟,其沟道连接所述第一取样电容器的后极板到第一输入信号; 第一运算放大器,其连接在第一运算放大器输入信号和第一运算放大器输出信号之间,第一运算放大器有一反相输入和一非反相输入,其接收第一运算放大器输入信号,第一输出和第二输出驱动所述第一运算放大器输出; 第一斩波通过晶体管开关,其栅极接收所述第一斩波时钟,其沟道连接所述第一输入信号到所述第一运算放大器的反相输入;第一斩波交越晶体管开关,其栅极接收所述第二斩波时钟,其沟道连接所述第一输入信号到所述第一运算放大器的非反相输入; 第二斩波通过晶体管开关,其栅极接收所述第一斩波时钟,其沟道连接所述第一运算放大器的第一输出到一中间信号; 第二斩波交越晶体管开关,其栅极接收所述第二斩波时钟,其沟道连接所述第一运算放大器的第二输出到所述中间信号; 第一积分电容器,其连接在中间信号和第一输入信号之间; 均衡器,其通过均衡一均衡器输入信号而产生所述反馈信号。 9. a digital converter ADC, including: clock divider, which will trigger the delayed clock divider to produce a lower frequency in addition to the divided clock; a multi-phase non-overlapping clock generator receives a trigger delay clock, trigger generate a first phase and a second phase clock clock, clock phase and the second phase of the first non-overlapping clock and is active pulse, and run on a first frequency, the first frequency is in addition to reducing the frequency multiples; chopping non-overlapping clock generator which receives divided by `clock, the trigger for generating a first clock and a second chopper chopping clock, the first and second chopper chopping clock non-overlapping clock and is active pulse, and running on the inter-off frequency; wherein the delayed trigger clock to trigger the multi-phase non-overlapping clock generator, converting the first phase and the second phase clock clock; wherein the divided clock to trigger the non-chopper overlapping clock generator, converting the first and second chopper chopping clock clock; wherein the edges of the first and second chopper chopping clock clock appears in the chop clock cycle earlier than the first phase and the second phase clock clock edge, which is the same edge of the clock Trigger; a first sampling capacitor, which has a front plate and a rear plate; a first input transistor switch having a gate receiving the first clock phase, which before the first feedback transistor switch pole having a gate receiving the second phase clock, whose channel is connected to the feedback signal of the first sampling capacitor; channel connected to said first analog signal before sampling capacitor plates plate; having a gate receiving the second phase clock after the first switching transistor is connected, which channel is connected to the first plate of the sample capacitor to a first input signal; a first operational amplifier, which is connected in a first operation between the amplifier input signal and the output signal of the first operational amplifier, a first operational amplifier having a non-inverting input and an inverting input, a first operational amplifier that receives an input signal, a first output and a second output driving said first operation amplifier output; through a first chopper transistor switch having a gate receiving said first clock chopping, which channel is connected to the first input signal of said first operational amplifier inverting input; a first chopper cross the transistor switch having a gate receiving said second clock chopping, which channel is connected to the first input signal of said first operational amplifier non-inverting input; a second chopper transistor switch through its gate receiving said first chopper clock, its channel connecting the first operational amplifier output to a first intermediate signal; a second chopping transistor crossover switch having a gate receiving said second clock chopping, which said channel connecting the second output of the first operational amplifier to the intermediate signal; a first integrating capacitor connected between a first input signal and the intermediate signal; equalizer, which is generated by an equalizer input signal equalizer The feedback signal.
10.如权利要求9所述的模数转换器ADC,其中均衡器是I比特数模转换器DAC。 10. The ADC of claim ADC 9, wherein the equalizer is I bit digital to analog converter DAC.
11.如权利要求9所述的模数转换器ADC,其中中间信号是均衡器输入信号。 11. The ADC of claim ADC 9, wherein the intermediate signal is an input signal of the equalizer.
12.如权利要求9所述的模数转换器ADC,还包括: 第二取样电容器,其有一前极板和一后极板; 第二输入晶体管开关,其栅极接收所述第一相位时钟,其沟道连接所述中间信号到所述第二取样电容器的前极板; 第二反馈晶体管开关,其栅极接收所述第二相位时钟,其沟道连接所述反馈信号到所述第二取样电容器的前极板; 第二连接晶体管开关,其栅极接收所述第二相位时钟,其沟道连接所述第二取样电容器的后极板到第二运算放大`器输入信号; 第二运算放大器,其连接在第二运算放大器输入信号和均衡器输入信号之间; 第二积分电容器,其连接在第二运算放大器输入信号和均衡器输入信号之间。 12. The ADC of claim ADC 9, further comprising: a second sampling capacitor, which has a front plate and a rear plate; a second input transistor switch having a gate receiving the first clock phase its channel connected to said intermediate signal before said second sampling capacitor plate; a second feedback transistor switch having a gate receiving the second phase clock, which channel is connected to the feedback signal of the first Two front plates sampling capacitor; a second transistor switch is connected, its gate receiving the second phase clock, its channel connecting the second plate of the sampling capacitor after the second operational amplifier `input signal; Second operational amplifier, whose input is connected between the input signal and the equalizer in the second operational amplifier; a second integrator capacitor connecting the input signal between the input signal and the equalizer in the second operational amplifier.
13.一个斩波Σ Δ调制器,包括: 时钟产生器装置,用于产生第一斩波时钟和第二斩波时钟,以及第一相位时钟和第二相位时钟; 时钟边沿次序装置,其在所述时钟产生器装置内,用于产生第一斩波时钟和第二斩波时钟的边沿出现在第一相位时钟和第二相位时钟的边沿之前,第一相位时钟、第二相位时钟、第一斩波时钟、第二斩波时钟都在斩波时钟周期开始时发生改变; 其中斩波时钟周期是相位时钟周期的倍数; 相位非重叠装置,其在所述时钟产生器装置内,用于产生第一相位时钟和第二相位时钟作为具有同一频率的非重叠时钟,其中第一相位时钟和第二相位时钟不是在同一时间都处于活动状态的; 第一取样保持积分装置,用于取样模拟输入,用于将反馈输出积分到第一取样电容器上,第一取样电容器是由相位开关来切换的,其中当第一相位时钟处于活动状态时,模拟输入被取样,当第二相位时钟处于活动状态时,反馈输出被应用到第一取样电容器上,当第二相位时钟处于活动状态时,还用于连接第一取样电容器到第一输出; 第一放大器装置,用于放大第一放大器输入,以产生第一放大器输出; 输入斩波器装置,其连接在所述第一输出和第一放大器输入之间,当第一斩波时钟处于活动状态时,用于连接第一输出到第一放大器输入,当第二斩波时钟处于活动状态时,用于改变第一放大器输入; 输出斩波器装置,其连接在所述第一放大器输出和中间输出之间,当第一斩波时钟处于活动状态时,用于连接第一放大器输出到中间输出,当第二斩波时钟处于活动状态时,用于改变中间输出; 第一积分电容器装置,用于电容连接所述中间输出到所述第一输出,用于绕过所述输入斩波器装置、第一放大器装置和输出斩波器装置; 其中所述中间输出是一个用于一阶Σ Δ调制器的均衡器输入; 均衡器装置,用于将均衡器输入转换为一个二进制比特以产生所述反馈输出; 由此,在斩波时钟周期里,斩波时钟边沿就在相位时钟边沿之前产生。 13. a chopper Σ Δ modulator, comprising: a clock generator means for generating a first and a second clock chopping chopping clock, and a first clock phase and second phase clock; clock edge sequence means that the The internal clock generator means for generating a first edge and a second chopper chopping clock clock occurs before the edge of the first phase of the clock and the second phase of the clock, the first phase of the clock, the second phase of the clock, the first phase non-overlapping apparatus within the clock generator means for; a chopping clock, the second chopper clocks are altered by chopping clock cycle; wherein the chopping clock cycle is a multiple phase clock cycle generating a first phase and second phase clock clock as a non-overlapping clock with the same frequency, wherein the first and second phases of the clock phase clock is not at the same time are active; the first sample and hold integrator means for sampling analog input for the feedback output of the integrator to the first sampling capacitor, the first sampling capacitor is switched by a phase switch, wherein when the first phase of the clock is active, the analog input is sampled, when the second phase of the clock is active When the state feedback output is applied to the first sampling capacitor, when the second phase of the clock is active, but also for connecting the first sampling capacitor to a first output; a first amplifier means for amplifying the first amplifier input, to generate a first amplifier output; an input chopper device connected between the first output of the first amplifier input, when the first chopper clock is active, the first output for connection to a first amplifier input, when the second chopper clock is active, for changing the first amplifier input; output chopper device connected between the first amplifier output and intermediate output, when the first chopper clock is active state, for connecting the first amplifier output to the intermediate output, when the second chopper clock is active for varying intermediate output; a first integrating capacitor means for the intermediate output capacitor connected to the first output chopper for bypassing said input means, a first amplifier means and an output chopper means; wherein said intermediate output is used for a first-order Σ Δ modulator equalizer input; equalizer means for in the equalizer input is converted to a binary bits to produce the feedback output; thus, the chopper clock cycle, chopping clock edge just before the phase of the clock edge occurs.
14.如权利要求13所述的斩波Σ Δ调制器,其中所述斩波Σ Δ调制器是一个二阶Σ Δ调制器,还包括: 第二取样保持积分装置,用于取样所述中间输出,用于将反馈输出集成到第二取样电容器上,第二取样电容器是由相位开关来切换的,其中当第一相位时钟处于活动状态时,中间输出被取样,当第二相位时钟处于活动状态时,反馈输出被应用到第二取样电容器上,当第二相位时钟处于活动状态时,还用于连接第二取样电容器到第二输出; 第二放大器装置,用于放大第二输出,以产生所述均衡器输入; 第二积分电容器装置,用于电容连接所述第二输出到所述均衡器输入。 14. The chopper Σ Δ modulator according to claim 13, wherein said chopper Σ Δ modulator is a second-order Σ Δ modulator, further comprising: a second sample and hold integrator means for sampling said intermediate output for the feedback output integrated into the second sampling capacitor, a second sampling capacitor is switched by a phase switch, wherein when the first phase of the clock is active, the intermediate output is sampled, when the second phase of the clock is active When the state feedback output is applied to the second sampling capacitor, when the second phase of the clock is active, but also for the second sampling capacitor is connected to a second output; a second amplifier means for amplifying the second output to generating the equalizer input; a second integration capacitor means for connecting said second output capacitor to the input of the equalizer.
15.如权利要求14所述的斩波Σ Δ调制器,其中所述输入斩波器装置包括: 输入通过晶体管开关,每个都在栅极接收所述第一相位时钟,用于将所述第一输出毫无改变地传输到所述第一放大器输入; 输入交叉晶体管开关,每个都在栅极接收所述第二相位时钟,用于交换第一输出上的差分信号,毫无改变地通过差分交换而驱动所述第一放大器输入; 其中所述输出斩波器装置包括: 输出通过晶体管开关,每个都在栅极接收所述第一相位时钟,用于将所述第一放大器输出毫无改变地传输到所述中间输出; 输出交叉晶体管开关,每个都在栅极接收所述第二相位时钟,用于交换所述第一放大器输出上的差分信号,毫无改变地通过差分交换而驱动所述中间输出。 15. The chopper Σ Δ modulator according to claim 14, wherein said input means includes a chopper: input via the transistor switch, each gate receiving said first clock phase, for the The first output without change is transmitted to the first amplifier input; input cross transistor switch, each gate receiving the second phase clock, differential signaling for the first output switching on without change exchange by driving the first differential amplifier input; wherein said output chopper means comprises: output through transistor switch, each gate receiving the first phase clock, said first amplifier output for There is no change to the transfer to the intermediate output; output cross transistor switch, each gate receiving the second phase clock, differential signaling for switching said first amplifier output, there is no change by the difference driving said intermediate output exchange.
16.如权利要求15所述的斩波Σ Δ调制器,还包括: 斩波非重叠装置,其在所述时钟产生器装置内,用于产生所述第一斩波时钟和第二斩波时钟作为具有同一频率的非重叠时钟,其中所述第一斩波时钟和第二斩波时钟不是在同一时间都处于活动状态的。 16. The chopper Σ Δ modulator according to claim 15, further comprising: a non-overlapping chopper means, in which the clock generator means for generating said first and second chopper chopper clock As a non-overlapping clock clocks have the same frequency, wherein the first and second chopper chopping clock clock not at the same time are active.
17.如权利要求14所述的斩波Σ Δ调制器,其中所述第一取样保持积分装置还包括: 第一输入相位开关,当第一相位时钟处于活动状态时,其连接所述模拟输入到所述第一取样电容器的前极板; 第一反馈相位开关,当第二相位时钟处于活动状态时,其连接所述反馈输出和所述第一取样电容器的前极板; 第一连接相位开关,当第二相位时钟处于活动状态时,其连接所述第一取样电容器的后极板到所述第一斩波器装置。 17. The chopper Σ Δ modulator according to claim 14, wherein said first sample and hold integrator means further comprises: a first switch input phase, when the first phase clock is active, which connects the analog input to the front plate of the first sampling capacitor; a first feedback phase switch, when the second phase of the clock is active, the front plate connecting the feedback output and the first sampling capacitor; a first connection phase switch, when the second phase of the clock is active, connected after the first sampling capacitor plate to said first chopper means.
18.如权利要求17所述的斩波Σ Δ调制器,其中所述第一取样保持积分装置还包括: 第一固定相位开关,当第一相位时钟处于活动状态时,其应用一固定电压到所述第一取样电容器的后极板上。 18. The chopper Σ Δ modulator according to claim 17, wherein said first sample and hold integrator means further comprises: a first fixed phase switching, when the first phase clock is active, to apply a fixed voltage After the first sampling capacitor plates.
19.如权利要求18所述的斩波Σ Δ调制器,其中所述固定电压是接地电压。 19. The chopper Σ Δ modulator according to claim 18, wherein said fixed voltage is a ground voltage.
20.如权利要求17所述的斩波Σ Δ调制器,其中所述第一输入相位开关包括η沟道晶体管,其在栅极接收所述第一相位时钟;其中第一反馈相位开关和第一连接相位开关,每个都包括η沟道晶体管, 其在栅极接收所述第二相位时钟。 20. The chopper Σ Δ modulator according to claim 17, wherein said first switch comprises a η phase input channel transistor, its gate receiving at a first phase of the clock; wherein the first switch and the second feedback phase a switch connecting phase, each including η-channel transistor, a second gate receiving the clock phase.
Description  translated from Chinese

一种斩波稳定西格玛-德尔塔调制器 A form of chopper stabilized sigma - delta modulator

【技术领域】 TECHNICAL FIELD

[0001] 本发明涉及西格玛-德尔塔调制器(sigma-delta modulator,以下简称Σ Δ调制器),特别涉及用于斩波稳定(chopper stabilization)放大器的计时时钟的改善。 [0001] The present invention relates to a sigma - delta modulator (sigma-delta modulator, hereinafter referred to as Σ Δ modulator), and more particularly to chopper stabilization (chopper stabilization) to improve amplifier timing clock.

【背景技术】 BACKGROUND OF THE INVENTION

[0002] Σ Δ调制器广泛用于消费电子音频设备和精密测量设备,如24比特音频模数转换器(ADC)。 [0002] Σ Δ modulator widely used in consumer electronic audio equipment and precision measuring equipment, such as 24-bit audio digital converter (ADC). 信号处理是在数字域而非模拟域进行的,随着半导体进程的提高,也就使得节电和性能提高得以实现。 The signal processing in the digital domain rather than the analog domain, with the increase of the semiconductor process also makes energy-saving and performance improvements can be achieved. Σ △调制器在一个很高的频率上对输入信号进行采样,并在一个很宽的频带上扩展噪声(spread noise)。 Σ △ modulator on a very high frequency of the input signal is sampled, and extended noise (spread noise) over a wide frequency band. 这种超取样(over-sampling)和噪声整形(noiseshaping)可以提供更高的线性和动态范围。 This super sampling (over-sampling) and noise shaping (noiseshaping) can provide higher linearity and dynamic range.

[0003] 有时使用斩波稳定将噪声搬移到一个更高的频率上,然后在放大后去除噪声。 [0003] The use of chopper-stabilized noise sometimes move to a higher frequency, and then amplified noise removal. 在第一阶段放大器的输入之前加入一个乘法器,而在第一阶段放大起的输出上加入第二个乘法器。 Prior to the first input of the amplifier stage to join a multiplier, and the addition of the second multiplier from the output of the first stage of the amplification. 这些乘法器由一个斩波时钟(chopping clock)来控制。 The multiplier consists of a chopper clock (chopping clock) to control. 输入信号被第一乘法器调制搬移到斩波时钟的奇次谐波上。 The input signal is modulated onto a moving first multiplier odd harmonics chopping clock. 在放大器输入上的不想要的噪声仍然在一个低频上。 Noise amplifier input unwanted still on a low frequency. 在噪声和谐波放大后,第二乘法器将信号从奇次谐波搬回到低频带上,同时将放大的低频噪声调制搬移到它能被滤除的谐波上。 After the noise and harmonic amplification, the signal from the second multiplier odd harmonics to move back to the low frequency band, while the larger move to the low-frequency noise modulation harmonics can be filtered out. 因此在低频带上的信号去除了不想要的噪声。 Therefore, in addition to the low-frequency band signal to unwanted noise.

[0004] 图1是一个斩波稳定Σ Δ调制器的示意图。 [0004] FIG. 1 is a stable Σ Δ modulator schematic chopper. 图1是发明人想到的一个系统的方框图,不是现有技术。 Figure 1 is a block diagram of the prior art is not the inventor of a system of thought. 差分输入信号VINP、VINN是模拟信号,输入到取样保持积分模块120。 Differential input signals VINP, VINN is an analog signal, is input to the sample and hold integrator module 120. 非重叠相位时钟P1、P2控制取样保持积分模块120内的开关,在Pl时连接模拟输入VINP、VINN到取样电容,在P2时断开该模拟输入并适用反馈到该取样电容。 Non-overlapping clock phases P1, P2 control sample and hold switch integration module 120 when Pl connect analog input VINP, VINN to the sampling capacitor, disconnect the analog input at P2 and apply feedback to the sampling capacitor. 取样电容在P2时驱动取样保持积分模块120的输`出,但是在Pl时与该输出隔离。 When P2 drive sampling capacitor sample and hold integrator module output `the 120, but when the output isolation Pl. Pl即是取样阶段,而P2是积分阶段。 Pl That is the sampling stage, and P2 is the integration phase.

[0005] 第一阶段放大器140因为增加的输入斩波器132和输出斩波器134而稳定。 [0005] The first stage amplifier 140 because of the increased input and output chopper 132 chopper 134 and stability. 当斩波时钟C2处于活动状态(active)时,斩波器132、134交换该差分信号,但是当Cl处于活动状态(active)时,则让该差分信号通过。 When the chopping clock C2 is active (active), the chopper 132,134 exchange difference signal, but when Cl is active (active), then let the differential signal. 斩波时钟C1、C2是非重叠的并在一个比相位时钟P1、P2更低的频率上运行。 Chopping clock C1, C2 and in a non-overlapping run over the phase of the clock P1, P2 lower frequency.

[0006] 积分电容(图中未显示)也可以加在输入斩波器132、第一阶段放大器140和输出斩波器134的附近。 [0006] The integration capacitor (not shown) may also be added near the input chopper 132, a first stage amplifier 140 and the output chopper 134. 第二阶段取样保持积分模块122和第二阶段放大器142以类似的方式运行,但是没有斩波器在第二阶段放大器142旁。 The second sample and hold integrator stage 122 and second stage amplifier module 142 to run in a similar manner, but without a chopper amplifier in the second stage 142 side. 量化器14(quantizer)是一个1-比特量化器、微分器、德尔塔函数(delta function)、比较器、或者单比特数模转换器(DAC),其产生差分输出0UTP、0UTN反馈回到取样保持积分模块120、122。 Quantizer 14 (quantizer) is a 1-bit quantizer, differentiator, delta function (delta function), a comparator, or a single-bit digital to analog converter (DAC), which generates a differential output 0UTP, 0UTN fed back to the sampling maintaining integration module 120, 122.

[0007] 高精度Σ Δ调制器为了有更好的线性,取样保持积分模块120内的开关需要更大的导通电阻Ron(on-resistance)。 [0007] Σ Δ modulator with high accuracy in order to have better linearity, the sample and hold switch 120 integral module requires a larger on-resistance Ron (on-resistance). 对开关使用稍微大点的晶体管就可以达到较大的Ron。 Use slightly larger switching transistors can achieve greater Ron. 但是,这些较大的晶体管也会有较大的电容值,因此当接通时,它们的沟道下就会有更多的电荷。 However, these larger transistors will have a larger capacitance value, so that when turned on, there will be more charge them under the channel. 当晶体管开关断开时,有一些电荷会推入到源极(source)节点和漏极(drain)节点。 When the transistor switch is turned off, there are some of the charge will be pushed to the source (source) node and the drain (drain) node. 较大的Ron需要较大的栅极尺寸(gate size),因此有更多的电荷被推入源极节点和漏极节点。 Ron larger size requires a large gate (gate size), so there is more of a charge is pushed into the source node and the drain node.

[0008] 当取样保持积分模块120内的晶体管开关断开时,如在Pl或P2结束时,注入电荷150就是不想要的被推入源极节点和漏极节点的电荷。 [0008] When the transistor switch 120 is disconnected, as at the end of Pl or P2, the injected charge just do not want to charge 150 is pushed into the source node and the drain node when the sample and hold integrator module. 这些注入电荷150通过输入斩波器132,在第一阶段放大器140的输入上产生电压尖峰。 The injected charge 150 through the input chopper 132, a voltage spike on the input of the first stage amplifier 140. 然后这些电压尖峰被第一阶段放大器140放大,导致产生错误的偏移,其会反馈回并通过第二阶段放大器142而到达输出。 Then these voltage spikes are the first stage amplifier 140 amplifies, resulting in wrong offsets, which will be fed back through the second stage amplifier 142 and to the output.

[0009] 注入电荷150可能就在斩波时钟Cl、C2切换之前被注入,产生错误的斩波稳定。 [0009] The injected charge 150 may be in the chopping clock Cl, C2 is injected before switching, chopper stabilization error. 当电荷注入发生在一个关键时刻,刚好在斩波时钟切换之前,这样会加入杂散信号(spurs)到信号频带上。 When the charge injection occurs at a critical moment, just before the chopper clock switch, which will join the spurious signals (spurs) to the signal band.

[0010] 图2显示一个传统的斩波时钟计时时间安排,当刚好在斩波时钟切换之前P2时钟断开,这会产生电压尖峰。 [0010] Figure 2 shows a conventional chopper clocking schedule, when P2 clock just before the chopper clock is switched off, which produces voltage spikes. 相位时钟P1、P2是非重叠的,它们控制取样保持积分模块120 (图1)内的取样和积分。 Phase clock P1, P2 are non-overlapping, they control the sampling and sample and hold Points Points module 120 (Figure 1) within. 斩波时钟C1、C2也是非重叠的,但是在一个已除降的(divided-down)频率上运行,如在相位时钟P1、P2频率的1/2或1/4频率上运行。 Chopping clock C1, C2 is non-overlapping, but has been eliminated in a drop of (divided-down) frequency operation, such as running on a 1/2 or 1/4 of the frequency-phase clock P1, P2 frequency.

[0011] 在该传统计时上,P2降导致斩波时钟C2降,Pl升导致Cl有一些传输延迟后也升。 [0011] On the traditional time, P2 led to the chopping clock C2 drop down, Pl rise has led to Cl also rose after some of the propagation delay. 当P2降时,在取样保持积分模块120内的晶体管开关上出现电压尖峰152。 When P2 fall on the sample and hold integrator module 120 of the transistor switch of a voltage spike 152. 这些电压尖峰152出现在P2降之后、但是C2降之前、C2仍然处于活动状态时。 These voltage spikes 152 appear after P2 fall, but fall before C2, C2 still is active. 因此注入电荷就传输通过输入斩波时钟132内的晶体管。 Thus the injected charge to transport by chopping clock input 132 of the transistor. 当C2降时,然后额外的电荷(未显示)也会注入到这些相同的节点处。 When C2 down, then an additional charge (not shown) will be injected into the same node. 因此电压尖峰152被输入斩波器132和输出斩波器134调制和解调,产生无法消除的误差。 Therefore, voltage spikes 152 are input chopper 132 and output chopper 134 modulating and demodulating, errors can not be eliminated.

[0012] 图3显示另一个现有技术的斩波时钟计时,当刚好在斩波时钟切换之前Pl时钟断开,这会产生电压尖峰。 [0012] Figure 3 shows another prior art chopper clock time, when just before chopping off Pl clock clock switch, which will generate voltage spikes. 请参看Groeneold的美国专利公开2010/0289682之图4。 See U.S. Patent Publication 2010/0289682 Groeneold of Figure 4.

[0013] 在此现有技术计时里,Pl降导致斩波时钟C2降。 [0013] In this prior art timing in, Pl chop clock C2 lead to drop down. 然后另一个斩波时钟Cl升。 Then another chop clock Cl liters. 最后P2升。 Finally P2 liters. 当P1、P2都是低位时,在处于非活动状态,斩波时钟Cl、C2改变。 When the P1, P2 are low in inactive, chopping clock Cl, C2 change.

[0014] 当Pl降时,在取样保持积分模块120内的晶体管开关上出现电压尖峰154。 [0014] When Pl fall on the sample and hold integrator module 120 of the transistor switch of a voltage spike 154. 这些电压尖峰154出现在Pl降之后、但是C2降之前、C2仍然处于活动状态时。 These voltage spikes occur after 154 Pl drop, but drop before C2, C2 still is active. 因此注入电荷就传输通过输入斩波时钟132内的晶体管。 Thus the injected charge to transport by chopping clock input 132 of the transistor. 电压尖峰154被输入斩波器132和输出斩波器134调制和解调,产生无法消除的误差。 Voltage spikes 154 are input chopper 132 and output chopper 134 modulating and demodulating, errors can not be eliminated. 而且,当C2降时,然后额外的电荷(未显示)也会通过输出斩波器134的晶体管而注入到输出上。 Moreover, when C2 down, then an additional charge (not shown) will be through the output transistor chopper 134 is injected into the output.

[0015] 在图2和图3,当主要的相位时钟下降时,就会出现电压尖峰,因为晶体管开关闭合而注入电荷。 [0015] In FIGS. 2 and 3, when the main phase of the clock fall, there will be a voltage spike, since the transistor switch is closed and the injection charge. 这些电压尖峰出现在一个关键时刻,刚好在斩波时钟切换之前。 These voltage spikes appear at a crucial moment, just before the chopper clock switch. 因此,在这个关键时刻,电压尖峰和输入信号一同被调制和解调。 Therefore, at this critical moment, with the input signal voltage spikes and is modulated and demodulated.

[0016] 期望能有一个具有改良的斩波时钟计时的Σ Λ调制器。 [0016] expect to have an improved chopper clocking of Σ Λ modulator has. 期望有一个开关电容积分器的Σ Δ调制器, 不会刚好在斩波时钟转换之前注入电荷。 Expect to have a switched-capacitor integrator Σ Δ modulator, not just before the chopper clock transition injection charge. 期望Σ Δ调制器有改善的线性和噪声容限(linearity and noise margins)。 Expect improvement Σ Δ modulator linearity and noise margin (linearity and noise margins).

【附图说明】 BRIEF DESCRIPTION

[0017] 图1是一个斩波稳定Σ Δ调制器的示意图。 [0017] FIG. 1 is a stable Σ Δ modulator schematic chopper.

[0018] 图2显示传统的斩波时钟计时安排,因为P2时钟正好在斩波时钟切换之前关闭,这会导致电压尖峰。 [0018] Figure 2 shows a conventional arrangement of the chopping clock timing, since the P2 clock just before the chopper clock switching off, which causes voltage spikes.

[0019] 图3显示另一个现有技术斩波时钟计时安排,因为Pl时钟正好在斩波时钟切换之前关闭,这会导致电压尖峰。 [0019] Figure 3 shows another prior art arrangement the chopping clock timing, since Pl clock just before the chopper clock switching off, which causes voltage spikes.

[0020] 图4显示一个改善的计时安排,其中斩波时钟在相位时钟之前改变。 [0020] Figure 4 shows an improved timing arrangement wherein the phase of the clock prior to chopping clock change.

[0021] 图5是实现斩波稳定Σ Δ调制器功能的开关电容积分器的示意图。 [0021] FIG. 5 is a chopper-stabilized Σ Δ modulator function switched capacitor integrator schematic realized.

[0022] 图6显示在取样阶段Pl的斩波稳定Σ Δ调制器的示意图。 [0022] Figure 6 shows the sampling phase of the chopper-stabilized Pl Σ Δ modulator of FIG.

[0023] 图7显示在积分阶段P2的斩波稳定Σ Δ调制器的示意图。 [0023] Figure 7 shows the integration phase P2 of chopper-stabilized Σ Δ modulator schematic diagram.

[0024] 图8是时钟产生器的示意图,其在相位时钟之前转换斩波时钟,虽然斩波时钟是从相位时钟除降的。 [0024] FIG. 8 is a schematic diagram of a clock generator, which converts the chopper clock phase of the clock before, although chopping clock from the phase of the clock in addition to drop.

[0025] 图9是斩波稳定Σ Λ调制器的信号性能图。 [0025] FIG. 9 is a chopper-stabilized modulator signal Σ Λ performance graphs.

【具体实施方式】 [DETAILED DESCRIPTION]

[0026] 本发明涉及一个改进的斩波稳定Σ Δ调制器。 [0026] The present invention relates to an improved chopper stabilized Σ Δ modulator. 以下描述使本领域技术人员能够依照特定应用及其要求制作和使用在此提供的本发明。 The following description so skilled in the art in accordance with the particular application and its requirements can be produced and used in the invention provided herein. 所属领域的技术人员将明了对优选实施例的各种修改,且本文所界定的一般原理可应用于其它实施例。 Those skilled in the art will appreciate that various modifications of the preferred embodiment and the generic principles defined herein may be applied to other embodiments. 因此,本发明不希望限于所展示和描述的特定实施例,而是应被赋予与本文所揭示的原理和新颖特征一致的最广范围。 Thus, the present invention is not intended to be limited as shown and described specific embodiments, but is to be consistent with the principles disclosed herein and novel features of the widest scope.

[0027] 本发明已经认识到现有技术里的斩波时钟计时是有缺陷的,因为相位时钟刚好早斩波时钟改变之前关掉,会有注入电荷。 [0027] The present invention has been recognized in the prior art chopper clock timing is flawed, since the phase of the clock immediately before chopping clock changing switch off early, there is charge injection. 而该注入电荷出现在一个关键时刻,正是当节点电压需要是稳定的时刻。 And that the injected charge appears at a critical moment, it is required when the node voltage is stable at the moment. 本发明还认识到可以改变斩波时钟计时,以使得来自相位时钟的电荷在改变斩波时钟之后(在关键时刻过去之后)被注入。 The present invention also recognizes the chopping clock timing can be changed, so that the charge from the phase of the clock after changing the chopping clock (after a critical moment in the past) is injected. 那么该电路需要较长的时间从注入电荷中恢复过来。 Then the circuit takes a long time to recover from the injected charge.

[0028] 图4显示一个改善的计时时间,其中斩波时钟在相位时钟之前改变。 [0028] Figure 4 shows an improvement in the timing of time, wherein the phase of the clock prior to chopping clock change. 因为斩波时钟是从相位时钟除降的(divided-down),从较慢的时钟产生较快的时钟,这是反直觉的(counter-1ntuitive)。 Because the chopping clock is from the phase clock except drop (divided-down), generated from a slower clock fast clock, which is counter-intuitive (counter-1ntuitive). 但是,这个反直觉的时间安排会给基于斩波器的Σ △调制器带来好处。 However, the counter-intuitive timeline-based chopper will Σ △ modulator benefit.

[0029] 在一个实际的电路里,斩波时钟可以被相位时钟除以一个除数2或更大,如2、4、 [0029] In a practical circuit, the chopper clock phase of the clock can be divided by a divisor of 2 or more, such as 2, 4,

16、32、64等等。 16,32,64 and so on. 尽管斩波时钟C1、C2在比相位时钟P1、P2更低的频率上运行,但是斩波时钟Cl、C2在相位时钟P1、P2改变之前就转换。 Although the chopping clock C1, run on P2 C2 lower frequency than the phase of the clock P1,, but chopping clock Cl, C2 before the phase of the clock P1, P2 change is converted. 当斩波时钟和相位时钟都改变时,斩波时钟的边沿出现在相位时钟的边沿之前。 When the chopping clock and phase clock has changed, the chopper clock edge occurs before the edge of the phase of the clock.

[0030] 当P2仍处于活动状态时,斩波时钟C2降,然后斩波时钟Cl升。 [0030] When P2 is still active, chopping clock C2 down, then chop clock Cl liters. 在Cl升之后,相位时钟P2降,导致电荷注入和电压尖峰156。 After Cl liter, the phase clock P2 drop, resulting in charge injection and voltage spikes 156. 但是当出现电压尖峰156时斩波时钟Cl、C2是稳定的,使得在相位时钟P1、P2下一次变化之前,允许有节点的稳定性。 However, when there is a voltage spike 156 when the clock chopping Cl, C2 is stable, so that the phase of the clock prior to P1, P2 next time variation, allowing nodes stability. 确实是,因为P2降,使得刚好在电压尖峰156之后Pl升,一些注入电荷被晶体管开关(其由Pl升而控制)吸收,而不会传输通过输入斩波器132到达第一阶段放大器140。 Indeed, since the P2 down, so that just after the voltage spikes 156 Pl l, are some of the charge injection transistor switch (which is controlled by the Pl l) absorbed and not transmitted by the input chopper 132 reaches the first stage amplifier 140. 因为Pl升,一些注入电荷被转移到新形成的沟道(newly-formed channels)。 Because Pl liter, some of the injected charge is transferred to the channel (newly-formed channels) newly formed. 无论如何,在下一次相位时钟改变之前,电荷共享需要较长的时间去进入稳定状态(settle)。 In any case, before the next phase of the clock change, charge sharing takes a long time to enter the stable state (settle). 要有足够的时间使积分进入稳定状态(for integration to settle),用于第一阶段放大器140去运行并驱动其输出到一个稳定的数值。 Have enough time for the integration into a stable state (for integration to settle), for the first stage amplifier 140 and drives its outputs to run to a stable value. 应该可以达到更好的线性。 You should be able to achieve better linearity.

[0031] 当斩波时钟Cl降时,C2稍微延迟点而上升,然后P2降,Pl升。 [0031] When the chopper down clock Cl, C2 slight delay point rise, then fall P2, Pl liter. 当斩波时钟C1、C2不转换时,相位时钟P1、P2产生其他边沿。 When the chopping clock C1, C2 are not converted, the phase clock P1, P2 produce other edge. 可以使用一个在相位时钟P1、P2频率上运行的主时钟,来产生具有理想计时安排的所有时钟P1、P2、Cl、C2,通过重新同步除降的时钟到该主时钟,然后使用控制的延迟来产生理想次序的时钟边沿,如稍后的图8所示。 You can use a running clock in the phase P1, P2 frequency of the master clock, to generate all the clocks have ideal timing arrangements P1, P2, Cl, C2, except by re-synchronizing clock down to the master clock, and then use the control delay clock edge to produce the desired order, as later shown in Figure 8.

[0032] 图5是开关电容积分器的示意图,其实现一个斩波稳定Σ Δ调制器。 [0032] FIG. 5 is a schematic diagram of a switched capacitor integrator, which achieve a chopper-stabilized Σ Δ modulator. 图4所示的斩波时钟Cl、C2和相位时钟P1、P2的计时安排应用到图5-图7的时钟Cl、C2、P1、P2上。 As shown in Figure chopping clock Cl 4, C2 and phase clock P1, P2 timing arrangements apply to Figures 5 clock Cl 7 of the C2, P1, P2. 特别地,在斩波时钟Cl、C2和相位时钟P1、P2改变的那段时间里,斩波时钟Cl、C2在相位时钟P1、P2之前转换。 In particular, the chopping clock Cl, C2 and the phase of the clock P1, P2 change that time, the chopping clock Cl, C2 before phase clock P1, P2 conversion. 因为相位时钟P1、P2的运行频率高于斩波时钟C1、C2的运行频率,所以仍有时间当相位时钟P1、P2转换时,斩波时钟Cl、C2还保持稳定。 Because the phase of the clock P1, P2 is higher than the operating frequency of the chopping clock C1, C2 operating frequency, so there is still time when the phase of the clock P1, P2 when the conversion, chopping clock Cl, C2 also remained stable.

[0033] 差分输入信号VINP、VINN应用到开关42、44上,开关42、44在Pl阶段闭合,对电容器58、60充电。 [0033] The differential input signal VINP, VINN applied to the switches 42, 44, 42, 44 is closed at Pl stage switch, the capacitor 58, 60 is charged. 开关50、52在Pl阶段也是闭合,将电容器58、60的背板接地。 Switches 50, 52 at Pl stage is closed, the capacitor 58, 60 back to ground.

[0034] 在P2阶段,开关42、44、50、52断开,而开关54、56闭合,将存储在电容58、60上的电荷传输到运算放大器110的输入。 [0034] In the P2 stage, 42,44,50,52 disconnect switch, and the switch 54 is closed, the transmission charge stored in the capacitor to the input of the operational amplifier 58, 60, 110. 非重叠斩波时钟Cl、C2应用到开关22、24、26、28上,要么传输要么反转信号到运算放大器110的反相和非反相输入上。 Non-overlapping chopper clock Cl, C2 is applied to the switch 22,24,26,28, or transfer or reverse the inverted signal of the operational amplifier 110 and the non-inverting input. 类似的斩波开关32、34、36、38在运算放大器110的输出上。 Similar chopping switch 32, 34 in the output of the operational amplifier 110. 反馈电容器102、104连接运算放大器110的输入和输出,具有增益配置kl,其中kl是电容器58和电容器102的比率。 Feedback capacitor 102 connecting the input and output of the operational amplifier 110 has a gain configuration kl, where kl is the ratio of capacitor 58 and the capacitor 102.

[0035] 第二个取样保持积分模块通过开关62、64和电容器78、80连接到运算放大器110的输出上,开关62、64在Pl阶段也是闭合的。 [0035] The second sample and hold integrator module switches 62, 64 and capacitors 78, 80 connected to the output of the operational amplifier 110, 62, 64 Pl stage switch is closed. 接地开关70、72在Pl时是闭合的。 Pl 70, 72 at the time of the grounding switch is closed. 在P2阶段,开关62、64、70、72断开,开关74、76闭合,将存储在电容器78、80上的电荷传输到第二运算放大器112的输入。 In phase P2, switch 62,64,70,72 OFF, the switch 74, 76 is closed, the transfer charge stored on the capacitor 78, 80 to the input of the second operational amplifier 112. 反馈电容器106、108连接第二运算放大器112的输入和输出,具有增益配置k2,其中k2是电容器78和电容器106的比率。 106, 108 are connected to the feedback capacitor of the second operational amplifier 112 input and output, configuration having a gain k2, where k2 is the ratio of the capacitor 78 and the capacitor 106.

[0036] 量化器14接收第二运算放大器112的输出V0P2、V0N2,并产生差分输出C0UTP、C0UTN。 [0036] quantizer 14 receives the output of the second operational amplifier V0P2 112's, V0N2, and generates a differential output C0UTP, C0UTN. 一旦V0P2、V0N2之间的差值达到一个阈值,量化器14就转换C0UTP、C0UTN,驱动一个至高,另一个至低。 Once V0P2, the difference between V0N2 reaches a threshold value, the quantizer 14 is converted C0UTP, C0UTN, drives a high, the other low.

[0037] COUTP、COUTN可以输出到一个滤波器,或者其他下游电路。 [0037] COUTP, COUTN can be output to a filter, or other downstream circuitry. COUTP、COUTN也可以反馈回第一取样保持积分模块的开关46、48,和反馈回第二取样保持积分模块的开关66、68。 COUTP, COUTN also be fed back to the first sample and hold switch integration module 46, 48, and fed back to the second sample and hold switch integration module 66,68.

[0038] 运算放大器110和附近的元件起到第一积分器的作用,如图1中的取样保持积分模块120,而运算放大器112及其附近的元件起到第二积分器的作用,如取样保持积分模块122。 [0038] an operational amplifier 110 and close to the first integrator element plays a role in maintaining the sample in Figure 1 integration module 120, and an operational amplifier 112 and its components in the vicinity of the second integrator role to play, such as sampling maintaining integration module 122. 反馈信号的加总由开关46、48提供到电容器58、60,作为第一加法器,由开关66、68提供到电容器78、80,作为第二加法器。 Sum of the feedback signal provided by the switch 46, 48 to the capacitor 58, 60, as the first adder, provided by the switch 66, 68 to the capacitor 78, 80, as the second adder.

[0039] 开关22、24、26、28执行输入斩波器132的功能,而开关32、34、36、38执行输出斩波器134的功能。 [0039] Switch 22,24,26,28 perform the function of input chopper 132 and the switch 32, 34 perform the function output chopper 134. 这些及其他开关可以由η-沟道晶体管来实现,或者由P-沟道晶体管来实现,或者是并联的η-沟道和P-沟道晶体管的传输门。 These and other switches can be implemented by η- channel transistor, or to achieve the P- channel transistor or a transmission gate connected in parallel η--channel and P- channel transistor. 增益调整(scaling)可以通过电容器比率来实现。 Gain adjustment (scaling) can be achieved by capacitor ratios.

[0040] 图6显示斩波稳定Σ Δ调制器在取样阶段Pl时的示意图。 [0040] Figure 6 shows a schematic diagram Δ Σ chopper-stabilized modulator sampling phase Pl of. 当Pl高而P2低时,开关42、44、50、52闭合,开关46、48、54、56保持断开,允许取样电容器58、60去取样模拟输入。 When high and low Pl P2, the switch 42,44,50,52 closed, the switch 46,48,54,56 remains open, allowing the sampling capacitor 58, 60 to sampling analog inputs. 在第二积分器,开关62、64、70、72闭合,开关66、68、74、76保持断开,允许取样电容器78、80去取样第一积分器的输出。 In a second integrator, the switch is closed 62,64,70,72, 66,68,74,76 switch remains open, allowing sampler sampling capacitors 78, 80 to the first output of the integrator.

[0041] 斩波器可以是两者中任一状态,因为斩波时钟是从相位时钟中除降的(divided-down),但是在次例子里Cl是高C2是低。 [0041] The chopper may be either, a state, since the phase of the clock from the clock chopping, in addition to reducing the (divided-down), but in the second example is a high-Cl C2 is low. 由Cl控制的开关22、24将反馈从积分电容器102、104传输到运算放大器110的输入上,而由C2控制的开关26、28保持断开,防止交越(cross-over)。 Cl controlled by the switch 22, the feedback input 110 from integrating capacitor 102 is transmitted to the operational amplifier, and a switch controlled by the C2 26, 28 remains open, preventing crossover (cross-over). 在输出斩波器,由Cl控制的开关32、34,将运算放大器110的输出传输到第二阶段和积分电容102、104,而由C2控制的开关36、38保持断开,防止交越(cross-over)。 Output chopper switch controlled by a Cl 32, the output of the operational amplifier 110 is transmitted to the second stage and integrating capacitors 102, 104, and the C2 control switch 36, 38 remains open, preventing crossover ( cross-over).

[0042] 当P2关闭,紧接着Pl打开,斩波时钟C1、C2是稳定的,所以在取样阶段结束之前,有整个Pl脉宽去共享注入电荷。 [0042] When P2 is closed, followed Pl open, chopping clock C1, C2 is stable, so before the end of the sampling stage, have to share the entire width Pl injection charge. 由P2关闭引起的噪声不会被输入斩波器132和输出斩波器134调制和解调,因为出现注入电荷时斩波时钟没有变化。 Close P2 caused by the noise will not be input chopper 132 and output chopper 134 modulating and demodulating, since no change occurs chopping clock charge injection.

[0043] 图7显示斩波稳定Σ Λ调制器在积分阶段P2时的示意图。 [0043] Figure 7 shows a schematic diagram Σ P2 chopper-stabilized modulator when Λ integration phase. 当Pl低而Ρ2高时,开关42、44、50、52保持断开,开关46、48、54、56闭合。 When Pl low Ρ2 high, the switch 42,44,50,52 remains open, switch 46,48,54,56 closed. 反馈被驱动到取样电容器58、60的一块极板上,而另一块极板通过开关54、56和输入斩波器(开关22、24、26、28)连接到运算放大器110的输入上。 Feedback is driven to a sampling capacitor plates 58 and 60, while the other plate is connected to the input of the operational amplifier 110 through the switch 54 and the input chopper (switch 22,24,26,28).

[0044] 在第二积分器上,开关62、64、70、72断开,开关66、68、74、76闭合。 [0044] In the second integrator, 62,64,70,72 switch off, switch 66,68,74,76 closed. 反馈被驱动到取样电容器78、80的一块极板上,而另一块极板通过开关74、76连接到运算放大器111的输入上。 Feedback is driven into the sample plates of a capacitor 78, 80, while the other plate is connected to the input of the operational amplifier 111 through the switch 74, 76.

[0045] 当Pl关闭,紧接着Ρ2打开,斩波时钟C1、C2是稳定的,所以在积分阶段结束之前,有整个P2脉宽去共享注入电荷。 [0045] When Pl closed, followed Ρ2 open, chopping clock C1, C2 is stable, so before the end of the integration phase, have to share the entire P2 pulse injection charge. 由Pl关闭引起的噪声不会被输入斩波器132和输出斩波器134调制和解调,因为出现注入电荷时斩波时钟没有变化。 Pl off caused by the noise is not input chopper 132 and output chopper 134 modulating and demodulating, since no change occurs chopping clock charge injection. 线性得到提高。 Linearity is improved.

[0046] 图8是一个时钟产生器的示意图,该时钟产生器在转化相位时钟之前转换斩波时钟,即使斩波时钟是从相位时钟除降的。 [0046] FIG. 8 is a schematic view of a clock generator, the clock generator before converting the phase of the clock conversion chopping clock, even chopping clock phase clock except from the drop. 主时钟CLKIN运行在相位时钟P1、P2的频率上。 Master clock running on the phase of the clock CLKIN P1, P2 frequency. 触发器(flip-flop) 196、198将CLKIN除以4,产生CLKD4。 Flip-flop (flip-flop) 196,198 will CLKIN divided by four to generate CLKD4. 图4的计时只需要其中一个触发器196、198,因为图4里斩波时钟的频率只是相位时钟频率的一半。 Timing of Figure 4 requires only one flip-flop 196, 198, since the frequency of 4 in just chop clock phase of the clock frequency by half.

[0047] 当CLKD4是高时,逆变器194(inverter)反转CLKD4,驱动一个O信号到与非门(NAND gate) 164,然后驱动一个I信号,传输穿过延迟线168,被逆变器192反转,驱动斩波时钟C2至低。 [0047] When CLKD4 is high, inverter 194 (inverter) reverse CLKD4, driving a O signal to the NAND gate (NAND gate) 164, and then I drive a signal transmitted through the delay line 168 is inverted 192 reverse, driving the chopper clock C2 to low. 由延迟线168的高输出被反馈回与非门162的输入,使得高CLKD4反转,传输穿过延迟线166,被逆变器190反转,驱动斩波时钟Cl至高。 High output by the delay line 168 is fed back to the input of NAND gate 162, so that high CLKD4 reversal, transmitted through the delay line 166, an inverter 190 is inverted to drive the chopper clock Cl supreme. 因此Cl和C2是非重叠的。 So Cl and C2 are non-overlapping.

[0048] 延迟线170保证了相位时钟P1、P2是在斩波时钟C1、C2变化之后才变化的。 [0048] delay line 170 to ensure that the phase of the clock P1, P2 is after chopping clock C1, C2 change before change. 延迟线170和其他元件的延迟量可以由电路设计者设定以确保可以达到图4的计时安排。 The amount of delay of the delay line 170 and other elements can be set by a circuit designer to ensure that the timing can be achieved Figure 4 arrangement. 特别地,触发器198的时钟输出延迟(clock-to-output delay)应该小于产生CLKIN的延迟加上延迟线170的延迟,才能保证斩波时钟C1、C2在相位时钟P1、P2转换之前完成转换。 In particular, the flip-flop 198 clock output delay (clock-to-output delay) should be less than produce CLKIN delay and the delay of the delay line 170, in order to ensure the chopping clock C1, C2 complete the conversion before the phase of the clock P1, P2 conversion .

[0049] 当CLKIN是高时,逆变器184反转来自延迟线170的延迟了的CLKIN,驱动一个O信号到与非门174的输入,然后驱动I传输通过延迟线178,再被逆变器182反转,驱动相位时钟P2至低。 [0049] When CLKIN is high, inverter 184 inverted from the delay line 170 CLKIN, driving an O signal to the input of a NAND gate 174, and then transmitted through the drive I delay line 178 is inverted again 182 reverse, drive P2 to the low phase of the clock. 然后延迟线178的高输出被反馈回与非门172的一个输入,高的延迟的CLKIN被反转,传输通过延迟线176,被逆变器180反转,驱动相位时钟Pl至高。 Then the delay line 178 is a high output is fed back to an input of NAND gate 172, the high latency of CLKIN is reversed, transmitted through the delay line 176, an inverter 180 is inverted, the drive phase clock Pl supreme. 因此P1、P2是非重叠的。 So P1, P2 are non-overlapping.

[0050] 图9是斩波稳定Σ Δ调制器的信号性能图。 [0050] FIG. 9 is a chopper-stabilized modulator signal Σ Δ performance graphs. 图5电路是使用图4的相位和斩波时钟的计时安排来运行的。 Circuit in Figure 5 is the use of the phase diagram and chopping clock timing arrangements 4 to run. 尖峰出现在基本频率和奇次谐波上。 Spikes on the fundamental frequency and odd harmonics. 但是,功率谱密度(PSD)在大约50000Hz保持低位,显示良好的信噪比。 However, the power spectral density (PSD) at about 50000Hz remain low, showing good signal to noise ratio. 信噪失真比(SNDR)是154.3dB,精度的等效比特位数(ENOB)是21.5比特。 Signal to noise and distortion ratio (SNDR) is 154.3dB, accuracy equivalent number of bits (ENOB) is 21.5 bits. 相比之下,使用图2的计时安排的仿真模拟,产生20.4的ΕΝ0Β,而使用图3的计时安排的仿真模拟,产生19.1的ΕΝ0Β。 In contrast, the use of simulation in Fig. 2 timing arrangements, resulting in 20.4 ΕΝ0Β, using FIG. 3 simulation timing arrangements, resulting in 19.1 ΕΝ0Β. 因此改善的计时方式提高了等效精度I〜2比特。 Thereby improving the timing accuracy I~2 ways to enhance the equivalent bits. [0051]【替代实施例】 [0051] [Alternate Embodiment]

[0052] 发明人还想到一些其他的实施例。 [0052] The inventors also think of some other examples. 例如时钟产生器可以由各种方法来实现,如一个或多个锁相环(PLL)、延迟线、其他类型时钟分频器、反转触发器、锁存器、或者其他安排和类型的逻辑门。 Such as a clock generator may be implemented by a variety of methods, such as one or more phase-locked loop (PLL), delay lines, other types of clock divider, toggle flip-flop, latch, or other arrangements and types of logic Gate. 虽然图8已经显示了反馈回与非门用于产生非重叠时钟,但是也可以使用仔细的计时分析,使用延迟线产生非重叠时钟,不需要反馈。 Although Figure 8 shows the feedback loop has a NAND gate for generating non-overlapping clock, it may also be used carefully timing analysis using the delay line to generate a non-overlapping clock, no feedback.

[0053] 相位时钟也可以称为多相位时钟。 [0053] The phase of the clock to be referred to as multi-phase clock. 主时钟可以在另一个频率上运行,该频率被第一除数除降以触发产生相位时钟,以及被另一个较大的除数除降以触发产生斩波时钟。 The master clock can be run on another frequency, which is the first divisor except drop to trigger the generation of phase clock, and by another big drop to trigger generate divisor except chop clock.

[0054] 为了时序和管线式目的,可以在逻辑和数据路径上加入锁存器、触发器、寄存器和其他存储设备,以允许时钟同步。 [0054] For the purpose of timing and line style, can be added in the logic and data path latches, flip-flops, registers and other storage devices to allow clock synchronization. 也可以为了各种目的而增加缓存、电容器、滤波器、电阻器和其他元件。 It can also increase the cache for various purposes, capacitors, filters, resistors and other elements. 可以不使用相位开关50、52、70、72使取样电容器的背板接地,而是使用另一个固定电压,如电源或者共模电压。 May not be used to make the phase switches 50,52,70,72 backplane sampling capacitor to ground, but the use of another fixed voltage, such as the power supply or the common mode voltage.

[0055] 通过互换反相和非反相输入,可以增加逆变,但是不改变整个功能,因此可以看成是等同的。 [0055] The exchange inverting and non-inverting input of the inverter can be increased, but does not change the overall function, it can be seen as equivalent. 开关可以是η沟道晶体管、P沟道晶体管,或具有并联的η沟道和P沟道晶体管的传输门,或更复杂的电路,可以是无源的或有源的,放大的或非放大的。 Channel transistor switch can be η, P-channel transistors, or transmission gates having parallel η-channel and P-channel transistors, or more complex circuits, it can be passive or active, amplified or amplification a. 可以反转时钟去驱动P沟道晶体管的栅极。 You can reverse the clock to drive the gate of the P-channel transistor. 可以使用低触发时钟(Active-low clocks),其有非重叠的低电平脉冲,而不是非重叠的高电平脉冲。 You can use low trigger clock (Active-low clocks), which has a low level of non-overlapping pulses, rather than non-overlapping high pulse.

[0056] 可在各种节点处添加额外组件,例如电阻器、电容器、电感器、晶体管等,且还可存在寄生组件。 [0056] In various nodes can add additional components, such as resistors, capacitors, inductors, transistors, etc., and also the presence of parasitic components. 启用和停用所述电路或者停电时钟可用额外晶体管或以其它方式实现。 Enable and disable the circuit or power outage clock available additional transistors or otherwise achieve. 可添加传送门晶体管或传输门以用于隔离。 You can add or transfer gate transistor portal for isolation. 虽然已经显示了差分逻辑,但是可以使用具有固定电压的单端信号,如对补差分信号(complement differential signals)接地,或者使用真差分路径(true differential path)。 Although differential logic has been shown, but you can use a single-ended signal having a fixed voltage, such as making it sub-signal (complement differential signals) to ground, or true differential path (true differential path).

[0057] 晶体管和电容最终的尺寸可以在电路仿真或现场测试之后进行选择。 [0057] The ultimate size of transistors and capacitors can be selected after the circuit simulation or field test. 可以使用金属掩膜或其他可编程部件,去确定最终的电容、电阻、或晶体管尺寸。 Metal mask may be used or other programmable means, to determine the final capacitors, resistors, transistors, or size. 在差分信号之间可以加入均衡开关。 Between the differential signal can be added to balance switch.

[0058] 加法器可以加入正或负值。 [0058] The adder can add a positive or negative value. 当加入负值时,加法器可以认为是减法器。 When adding a negative value, the adder can be considered subtractor. 术语“加法器”包括加法运算和减法运算。 The term "adder" includes addition and subtraction. 虽然在两阶段Σ Λ调制器的第一阶段已经加入斩波乘法器,但是斩波乘法器可以加在第二阶段而非第一阶段,或者是两个阶段都加入。 Although the two-phase modulator Σ Λ has joined the first phase of the chopper multipliers, but the chopper can be added in the second stage multiplier rather than the first phase, or both phases added. 虽然已经显示了两阶段Σ Δ调制器,但是也可以使用单阶段Σ Δ调制器,或者三阶段Σ Δ调制器。 Although two stage shows Σ Δ modulator, but you can also use a single stage Σ Δ modulator, or a three-stage Σ Δ modulator.

[0059] 虽然描述的是Σ Δ调制器在ADC里的应用,但是Σ Δ调制器也可以使用在其他应用里。 [0059] Although the description is Σ Δ modulator in ADC in the application, but Σ Δ modulator can also be used in other applications.

[0060] 本发明背景技术部分可含有关于本发明的问题或环境的背景信息而非描述其它现有技术。 Background of the Invention section [0060] This may contain background information on the issue or the environment rather than the description of the present invention other prior art. 因此,在背景技术部分中包括材料并不是申请人承认现有技术。 Thus, in the background section includes material not recognize the applicant prior art.

[0061] 本文中所描述的任何方法或工艺为机器实施或计算机实施的,且既定由机器、计算机或其它装置执行且不希望在没有此类机器辅助的情况下单独由人类执行。 [0061] Any method or process described herein is a machine implemented or computer-implemented and established by a machine, computer or other device to perform and do not want to separate performed by humans in the absence of such machine-assisted situation. 所产生的有形结果可包括在例如计算机监视器、投影装置、音频产生装置和相关媒体装置等显示装置上的报告或其它机器产生的显示,且可包括也为机器产生的硬拷贝打印输出。 Produced tangible results on the display device may include associated media devices and a display device such as a computer monitor, a projection device, or other audio producing reports produced by the machine, and may also include a machine-generated hardcopy printout. 对其它机器的计算机控制为另一有形结果。 Other machine's control computer to another tangible result.

[0062] 已出于说明和描述的目的呈现了对本发明实施例的先前描述。 [0062] purposes of illustration and description has been presented previously described embodiments of the present invention. 其不希望为详尽的或将本发明限于所揭示的精确形式。 It is not intended to be exhaustive or to limit the invention to the precise form disclosed. 鉴于以上教示,许多修改和变型是可能的。 In view of the above teachings, many modifications and variations are possible. 希望本发明的范围不受此详细描述限制,而是由所附权利要求书限制。 It intended that the scope of the present invention is not affected by this detailed description, but is limited by the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
CN101044684A16 Sep 200526 Sep 2007模拟装置公司Multi-bit continuous-time front-end sigma-delta adc using chopper stabilization
US2006/0139192 Title not available
Classifications
International ClassificationH03M3/02
Cooperative ClassificationH03M3/34, H03M3/43, H03M3/454
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