CN102541805A - Multi-processor communication method based on shared memory and realizing device thereof - Google Patents
Multi-processor communication method based on shared memory and realizing device thereof Download PDFInfo
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- CN102541805A CN102541805A CN2010105803268A CN201010580326A CN102541805A CN 102541805 A CN102541805 A CN 102541805A CN 2010105803268 A CN2010105803268 A CN 2010105803268A CN 201010580326 A CN201010580326 A CN 201010580326A CN 102541805 A CN102541805 A CN 102541805A
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Abstract
The invention discloses a multi-processor communication method based on a shared memory and a realizing device thereof. The multi-processor communication method comprises the following steps of: dividing a section of shared memory space or shared PCI (Peripheral Component Interconnect) address space from the memory of a main processor module, directly mapping the section of shared memory space or shared PCI address space to a system PCI bus through a transparent PCI bus bridge, and mapping the section of shared memory space or shared PCI address space to the shared PCI address space or the shared memory space of sub processor modules through a nontransparent PCI bus bridge, thereby forming a section of shared memory space which can be accessed by the main processor module and the sub processor modules; and data exchange in the shared memory space is realized by reading and writing data information in a function interface manner. The realizing device of the multi-processor communication method is characterized in that the main processor module is connected with the system PCI bus through a transparent PCI bridge, and the sub processor module is connected with the system PCI bus through a nontransparent PCI bridge. The multi-processor communication method and the realizing device, disclosed by the invention, have the advantages of capability of improving operation speed of a system, and higher reliability, flexibility and extendibility.
Description
Technical field
The present invention relates to the computer realm in a kind of high-performance digital control system, particularly a kind of communication means and implement device thereof of the multiprocessor based on the shared drive structure.
Background technology
Along with the progress of Modern Manufacturing Technology, efficiently, at a high speed, the important indicator of estimating the high-performance digital control system that become such as high-precision.Therefore, also increasingly high to the functional requirement in the digital control system, in same system, depend merely on the application demand that a processor has been difficult to satisfy the Mixed Real-Time task of digital control system.What original system architecture adopted is the serial processing mode, and the data transmission channel utilization factor between the functional task is lower.In the Mixed Real-Time task of digital control system; Real-time task is to operate in kernel spacing; And un-real time job is to operate in user's space; Each processor need be accomplished the various tasks function, and this just requires to have between the distributed processors a kind of mechanism to realize exchanges data, guarantees the normal operation of system.All be autonomous subsystem between the different processors,, the method for data information exchange between a kind of each single sub-processor need be provided for guaranteeing the integrality of system.
Summary of the invention
For solving above-mentioned system's operation processing power difference and the low problem of exchanges data speed; The object of the present invention is to provide and a kind ofly satisfy the high-performance digital control system to processing capability in real time, the multiprocessor communication method and the implement device thereof based on shared drive of the requirement of high speed and super precision motion control ability and exchanges data speed aspect.
In order to realize the foregoing invention purpose, technical scheme of the present invention is following:
A kind of multiprocessor communication method based on shared drive comprises the steps:
Divide one section shared memory space or share the PCI address space at the internal memory of main processor modules; Map directly on system's pci bus through transparent mode pci bus bridge; Be mapped on the shared PCI address space or shared drive address space of processor module the shared memory space that forms one section main processor modules and can both visit again from processor module by nontransparent formula pci bus bridge; Adopt function interface that the data in the shared memory space are read and write exchange.
The partition process of the communal space is following:
The address window of each processor in virtual address space is through corsspoint switch matrix Route Selection Memory Controller Hub or pci controller; And the address window register is set, correspondingly on physical address space, be divided into and share PCI address space and shared drive address space.
Nontransparent formula pci bus bridge map addresses process is following:
Base register address mask and base register in the nontransparent formula pci bus bridge configuration space are provided with; With the plot of conversion in the preceding address and base register and base register address mask with the result compare; If equate; Convert the plot after the conversion to through plot conversion and control register, the plot after the side-play amount in the preceding address of conversion and the conversion is merged, formed the address after the conversion.
Reading and writing data exchange step in the shared memory space comprises as follows:
Through opening function interface, distribute shared drive, scanning shared drive updating mark; Whether the data in the inspection shared drive are upgraded; If the mutex amount is then applied for and obtained to read to Data Update, read the data message in the shared drive through reading function interface; After read data information finishes, release read mutex amount.
Inspection scanning shared drive termination flag if termination flag is not set, is carried out shared drive Data Update inspection next time.
If there is not Data Update, then apply for and obtain to write the mutex amount, upgrade the data message in the shared drive through writing function interface, behind the end of message (EOM) that Updates Information, discharge the mutex amount of writing; Inspection scanning shared drive termination flag if termination flag is not set, is carried out shared drive Data Update inspection next time.
If termination flag is set, close shared drive through closing function interface.
A kind of multiprocessor communication method and implement device thereof based on shared drive comprises main processor modules and a plurality of from connecting through system's pci bus between the processor module.Main processor modules and processor, IO interface, network interface card, video card and transparent mode pci bus bridge are all arranged from processor module; IO interface in the above-mentioned principal and subordinate processor module, network interface card, video card and transparent mode pci bus bridge are connected with local pci bus respectively, and processor is connected through the internal system bus with internal memory in the above-mentioned principal and subordinate processor module; Main processor modules is received on system's pci bus through transparent mode PCI bridging, receives on system's pci bus through nontransparent formula PCI bridging from processor module.
The present invention compared with prior art, beneficial effect is following:
1. the present invention combines the free software (SuSE) Linux OS, has adopted the master-slave mode multiprocessor system communication means, when carrying out system's control, has realized the parallel processing of complex data, has improved the arithmetic speed of system.
2. main processor modules and be pci bus among the present invention from what adopt between the processor module; Carry out exchanges data through the read-write shared drive, event of data loss seldom occurs, have very high reliability; Exchanges data delay simultaneously is less, can guarantee the real time data switching requirement of system.
3. the present invention allows dynamically to reconfigure internal memory, and the user can freely dispose the size of shared drive according to system's needs, and data transfer is transparent alternately, has stronger dirigibility.
4. what adopt among the present invention is pci bus, through bus bridge, can expand much from processor module and other assistance application function, has extendability well.
Description of drawings
Fig. 1 is a communication apparatus structure synoptic diagram of the present invention;
Fig. 2 is an address window mapping block synoptic diagram of the present invention;
Fig. 3 is an address of the present invention routing selecting module synoptic diagram;
Fig. 4 is a bus bridge address conversion module synoptic diagram of the present invention;
Fig. 5 is an exchanges data process flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention program is described in further detail.
As shown in Figure 1; Processor adopting is based on the Godson processor of MIPS architecture; Divide one section shared memory space or share the PCI address space at the internal memory of main processor modules; Map directly on system's pci bus through transparent mode pci bus bridge, be mapped on the shared PCI address space or shared drive address space of processor module the shared memory space that forms one section main processor modules and can both visit again by nontransparent formula pci bus bridge from processor module; Adopt function interface that the data in the shared memory space are read and write exchange.
As shown in Figure 2; The communal space is divided: the address window in the virtual address space of each processor is through corsspoint switch matrix Route Selection Memory Controller Hub or pci controller; Through the address window register is set, correspondingly on physical address space, be divided into PCI address space and memory address space.In implementation system; The base register and the base register address mask of address window are set; To the shared drive address space of physical address space, the 256M spatial mappings of the 2nd address window is to the shared PCI address space of physical address space with the 256M spatial mappings of section KSEG0 in the virtual address space and the 1st address window among the section KSEG1.
As shown in Figure 3; Address Route Selection step is following: processor core obtains virtual address from the program of system's operation; And this virtual address sent on the corsspoint switch matrix, corsspoint switch matrix compares according to virtual address of sending and the base register in the address window, and confirming to hit shared PCI address space still is the shared drive address space; Share the PCI address space if hit; Just the 2nd address window is sent on the pci controller,, the 1st address window is sent on the Memory Controller Hub if hit the shared drive address space.
As shown in Figure 4; Nontransparent formula pci bus bridge map addresses step is following: base register address mask and base register in the nontransparent formula pci bus bridge configuration space are provided with; With the plot of conversion in the preceding address and base register and base register address mask with after the result compare, if equal, convert the plot after the conversion to through plot conversion and control register; Side-play amount in the preceding address of conversion and the plot after the conversion are merged, formed the address after the conversion.
As shown in Figure 5, through opening function interface, open shared drive; Scanning shared drive updating mark, whether the data in the inspection shared drive are upgraded, if Data Update; Then apply for and obtain to read the mutex amount; Read the data message in the shared drive through reading function interface, after read data information finishes, release read mutex amount; Inspection scanning shared drive termination flag if termination flag is not set, is carried out shared drive Data Update inspection next time; If termination flag is set, close shared drive through closing function interface.
If there is not Data Update, then apply for and obtain to write the mutex amount, upgrade the data message in the shared drive through writing function interface, behind the end of message (EOM) that Updates Information, discharge the mutex amount of writing; Inspection scanning shared drive termination flag if termination flag is not set, is carried out shared drive Data Update inspection next time; If termination flag is set, close shared drive through closing function interface.
The embodiments of the invention system is based on the multiprocessor communication device of shared drive, and what adopt between the multiprocessor is primary and secondary structure, main processor modules and a plurality of from connecting through system's pci bus between the processor module.Main processor modules and processor, IO interface, network interface card, video card and transparent mode pci bus bridge are all arranged from processor module; IO interface in the above-mentioned principal and subordinate processor module, network interface card, video card and transparent mode pci bus bridge are connected with local pci bus respectively, and processor is connected through the internal system bus with internal memory in the above-mentioned principal and subordinate processor module; The pci bus bridge has dual mode, be respectively transparent mode and nontransparent mode; The transparent mode of pci bus bridge, bridge from the interface be transparent to the main processor modules on the main interface respectively from the processor module all devices.The pci bus bridge is a nontransparent mode; Because the main processor modules address to main interface from interface resource and address of pci bus bridge isolates each other; Be used to connect two separate processor modules, can realize carrying out address translation to main interface with between the pci bus of interface.
Claims (8)
1. the multiprocessor communication method based on shared drive is characterized in that comprising the steps:
Divide one section shared memory space or share the PCI address space at the internal memory of main processor modules; Map directly on system's pci bus through transparent mode pci bus bridge; Be mapped on the shared PCI address space or shared drive address space of processor module the shared memory space that forms one section main processor modules and can both visit again from processor module by nontransparent formula pci bus bridge; Adopt function interface that the data in the shared memory space are read and write exchange.
2. the multiprocessor communication method based on shared drive according to claim 1 is characterized in that the partition process of the communal space:
The address window of each processor in virtual address space is through corsspoint switch matrix Route Selection Memory Controller Hub or pci controller; And the address window register is set, correspondingly on physical address space, be divided into and share PCI address space and shared drive address space.
3. the multiprocessor communication method based on shared drive according to claim 1 is characterized in that nontransparent formula pci bus bridge map addresses process is following:
Base register address mask and base register in the nontransparent formula pci bus bridge configuration space are provided with; With the plot of conversion in the preceding address and base register and base register address mask with the result compare; If equate; Convert the plot after the conversion to through plot conversion and control register, the plot after the side-play amount in the preceding address of conversion and the conversion is merged, formed the address after the conversion.
4. the multiprocessor communication method based on shared drive according to claim 1 is characterized in that the reading and writing data exchange step in the shared memory space is following:
Through opening function interface, distribute shared drive, scanning shared drive updating mark; Whether the data in the inspection shared drive are upgraded; If the mutex amount is then applied for and obtained to read to Data Update, read the data message in the shared drive through reading function interface; After read data information finishes, release read mutex amount.
5. the multiprocessor communication method based on shared drive according to claim 4 is characterized in that
Inspection scanning shared drive termination flag if termination flag is not set, is carried out shared drive Data Update inspection next time.
6. the multiprocessor communication method based on shared drive according to claim 5 is characterized in that:
If there is not Data Update, then apply for and obtain to write the mutex amount, upgrade the data message in the shared drive through writing function interface, behind the end of message (EOM) that Updates Information, discharge the mutex amount of writing; Inspection scanning shared drive termination flag if termination flag is not set, is carried out shared drive Data Update inspection next time.
7. the multiprocessor communication method based on shared drive according to claim 6 is characterized in that:
If termination flag is set, close shared drive through closing function interface.
8. based on the implement device of the multiprocessor communication method of shared drive, it is characterized in that this device comprises:
Main processor modules and a plurality of from connecting through system's pci bus between the processor module; Main processor modules and processor, IO interface, network interface card, video card and transparent mode pci bus bridge are all arranged from processor module; IO interface in the above-mentioned principal and subordinate processor module, network interface card, video card and transparent mode pci bus bridge are connected with local pci bus respectively, and processor is connected through the internal system bus with internal memory in the above-mentioned principal and subordinate processor module; Main processor modules is received on system's pci bus through transparent mode PCI bridging, receives on system's pci bus through nontransparent formula PCI bridging from processor module.
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| WO2014024080A2 (en) * | 2012-08-10 | 2014-02-13 | International Business Machines Corporation | Providing service address space for diagnostics collection |
| CN103810139A (en) * | 2014-01-24 | 2014-05-21 | 浙江众合机电股份有限公司 | Data exchange method and device for multiple processors |
| CN103823638A (en) * | 2014-02-08 | 2014-05-28 | 华为技术有限公司 | Virtual equipment access method and device |
| WO2014190486A1 (en) * | 2013-05-28 | 2014-12-04 | 华为技术有限公司 | Method and system for supporting resource isolation under multi-core architecture |
| CN103731328B (en) * | 2014-01-02 | 2016-09-07 | 烽火通信科技股份有限公司 | System and method based on Linux Sharing Memory Realization home gateway data communication |
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Application publication date: 20120704 |