CN102522110B - Method and device for realizing data preloading in transmission circuit of digital audio interface - Google Patents
Method and device for realizing data preloading in transmission circuit of digital audio interface Download PDFInfo
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- CN102522110B CN102522110B CN201110389582.3A CN201110389582A CN102522110B CN 102522110 B CN102522110 B CN 102522110B CN 201110389582 A CN201110389582 A CN 201110389582A CN 102522110 B CN102522110 B CN 102522110B
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Abstract
The invention discloses a method and device for realizing data preloading in a transmission circuit of a digital audio interface. According to the method and the device for realizing data preloading in the transmission circuit of the digital audio interface, a data preloading control module is in charge of the advance preparation of data by arranging a detecting counter, an auxiliary counter and the data preloading control module in a transmission circuit of a digital audio interface through referring to the counting value of the detecting counter or the auxiliary counter, the counting value of a moment transmitting first data is also judged according to a digital audio interface protocol, and a period before the data are transmitted is determined according to the counting value and is just a moment for preparing the data; and when a synchronous clock (LRCK) arrives, the first data are shifted out on the edge of a bit clock (BCLK), and then other data are also shifted out on the edge of the bit clock bit by bit. According to such a data preloading method, the time delay brought because of logical judgment is decreased, the data transmission rate is enhanced, and the time-sequence characteristic of a circuit is structurally improved.
Description
Technical field
The present invention relates to digital audio interface transtation mission circuit field, especially relate to the method and apparatus by improve data rate by data prestrain in digital audio interface transtation mission circuit.
Background technology
Digital audio interface is through analog to digital conversion by sound pick-up outfit, analog audio data is become to digital data stream, send to system by specific agreement, or by specific agreement, digital data stream is sent to tone playing equipment by system, then audio frequency is originally played back through digital-to-analog conversion by tone playing equipment.
Digital audio interface, according to the sampling rate of voice data and quantified precision, has different transfer rates.Modal sampling rate has 8KHz, 44.1KHz, and 48KHz, 96KHz etc., the precision of data also may have 16,18,20,24,32 etc.The quality of voice data is higher, and the sampling rate of requirement is higher, and the quantified precision of requirement is also higher, and higher tonequality requires just to require the transfer rate that audio interface circuit is higher.In the time that system environments is very poor, the line between digital audio interface may produce a lot of uncertain time delays, just needs a good interface circuit of characteristic that system also can normally be worked under such environment.
Common digital audio interface is serial synchronous transmitting-receiving, i.e. data transmission or reception of clock one by one on clock edge, and the sampled data of different sound channels is alignd according to synchronous clock tissue.Common interface protocol has IIS (Integrate Interface of Sound, integrated audio interface), left-justify, Right Aligns, DSP pattern etc.Data change along as mark taking synchronous clock (LRCK), start to send data or in arriving, start to send first data at next bit clock (BCLK) when synchronous clock changes.In the situation that data demand is exported data in the time that synchronous clock (LRCK) changes at once, common design meeting data in two sub-sections, a part is by one group of decision logic switch data output port, first data to be sent after synchronizing signal (LRCK) being detected at once, is then switched to by bit clock data are exported by turn again in arriving at next bit clock (BCLK).
In digital audio interface transtation mission circuit, some interface protocol is that data transmission does not have the enough reaction time, in the time that occurring, data sync clock (LRCK) must send the first bit data simultaneously, send next bit data at next bit clock (BCLK) rising edge, by that analogy.Switching different circuit by one group of decision logic control selector switch sends respectively first and other bit data and can realize, but complicated decision logic brings very large delay can to the data of first transmission, greatly affect the temporal characteristics of integrated circuit, cannot reach certain message transmission rate.For improving the temporal characteristics of circuit, need to adopt prediction to load the way of data, prepare in advance data by prediction, then by bit clock (BCLK), total data is shifted out by turn.
As above chat, in the design of digital audio interface transtation mission circuit, the sequence problem of the first bit data is the Main Bottleneck of design, and other bit data can be with bit clock (BCLK) along aliging, but because the complexity of decision logic and agreement and design have relation, may bring a lot of uncertain time delays, so that whole design circuit characteristic is very poor.In the bad application of system environments, may cause interface circuit data transmission fault especially.
Summary of the invention
The object of this invention is to provide a kind of method and apparatus of realizing data prestrain in digital audio interface circuit, it introduces data prestrain circuit in digital audio interface circuit, preliminary date in advance, allow total data all send by turn along upper at bit clock (BCLK), solve the unbalanced problem of sequential, thereby improve the transmission speed of data.
For achieving the above object, the present invention proposes one of technical scheme and is: a kind of method that realizes data prestrain in digital audio interface transtation mission circuit, comprising:
A. detect synchronous clock and the bit clock in audio interface transtation mission circuit by detection counter, and determine the bit clock rate of digital audio interface and the count value of detection clock;
The count value of the bit clock rate that b. data prestrain control module obtains according to described detection counter and detection clock, according to the requirement of digital audio interface agreement, count value when data are sent in judgement, and determine that the one-period sending before data is the data preparatory period of preparing data;
C. data prestrain control module sends data prestrain control signal to digital sending module in the data preparatory period, by data transmission blocks, data to be sent is loaded in shift register.
D. the first bit data is sent out on bit clock edge in the time that synchronous clock arrives by shift register.
Wherein, in described data transmission blocks, there are parallel L channel data and parallel right data.
Another technical scheme that the present invention proposes is: a kind of method that realizes data prestrain in digital audio interface transtation mission circuit, comprising:
A. detect synchronous clock and the bit clock in audio interface transtation mission circuit by detection counter, and determine the bit clock rate of digital audio interface and the count value of detection clock;
B. produce synchronizing signal by detection counter to auxiliary counter, carry out according to this synchronizing signal the counting that is associated with described detection counter by auxiliary counter;
C. data prestrain control module, according to the count value of described auxiliary counter, according to the requirement of digital audio interface agreement, judges the moment of sending data, and determines that the one-period sending before data is the data preparatory period of preparing data;
D. data prestrain control module sends Loading Control signal in the data preparatory period, and data to be sent are loaded in shift register and are ready for sending.
E. the first bit data is sent out on bit clock edge in the time that synchronous clock arrives by shift register.
Wherein, described auxiliary counter is hinted obliquely at and is obtained by described detection counter.
In described data transmission blocks, there are parallel L channel data and parallel right data.
The third technical scheme that the present invention proposes is: a kind of device of realizing data prestrain in digital audio interface transtation mission circuit, comprise clock module, data transmission blocks and register, and detection counter, data prestrain control module; Wherein:
Described detection counter is for detection of the synchronous clock in described clock module and bit clock, with the bit clock rate of specified data;
Described data prestrain control module is with reference to the count value of described detection counter, controls the one-period that described data transmission blocks sends before data at described register and is ready to data to be sent.
The device of described data prestrain also comprises auxiliary counter, and the counting of described auxiliary counter is hinted obliquely at and obtained by described detection counter.
Described data prestrain control module is with reference to the count value of described auxiliary counter, controls the one-period that described data transmission blocks sends before data at described register and is ready to data to be sent.
Described auxiliary counter is for being selected from up counter, the one in down counter and other type counter.
The present invention adopts the technical scheme of auxiliary counter to reduce the area of data prediction loading decision logic, auxiliary counter is by specific synchronization mechanism, produce transtation mission circuit required counting, make transtation mission circuit carry out complex calculation and can simply judge digital audio-frequency data Loading Control signal without calling multiple totalizers.
In the data that send when digital audio interface and synchronous clock alignment time,, send the responseless time of data, and the moment that synchronous clock arrives will be driven and be sent first data by bit clock.This just needs prediction to prepare in advance data.Load for realizing prediction, first need detecting position clock skew (BCLKRATIO), this is completed by detection counter, and when each synchronous clock (LRCK) sends synchronizing signal, the output valve of detection counter is bit clock rate (BCLKRATIO).
According to the agreement of interface, refer again to the count value of counter, bit clock rate (BCLKRATIO) can be determined preliminary date moment through calculating.The counter of reference, can be detection counter, can be also auxiliary counter.For example this Counter Design, for adding 1 counter, is counted as N when synchronizing signal is sent, and the moment that data are prepared is so when being counter arrival N-1.In the time that N is 0 or 1, the prediction moment need get back to when being counted as BCLKRATIO-1 or BCLKRATIO.For reducing decision logic, design a suitable auxiliary counter, can avoid a lot of plus and minus calculations.
With Right Aligns, the data instance that data length is WLEN, if detection counter CNTD is for adding 1 counter, this counter be one from 1 counter that is added to BCLKRATIO, each synchronizing signal all can count down to BCLKRATIO when arrival, then becomes clearly 1, so circulation.Adopt data prediction to load, need subtracter " BCLKRATIO-1 " and corresponding comparer, load for the data when in BCLKRATIO=WLEN situation; Subtracter " BCLKRATIO-WLEN " and " BCLKRATIO-WLEN-1 " and corresponding comparer, for judging the difference of BCLKRATIO and WLEN, determine the position BCLKRATIO-WLEN-1 that loads data controlling signal.If adopt the method for auxiliary counter, design one and subtract 1 counter, in BCLKRATIO-2, counter becomes clearly BCLKRATIO, so only need in the value CNTA=WLEN of auxiliary counter, load data.Use like this auxiliary counter (and comparer of a subtracter), although many 1 counters have been saved 2 subtracters and 1 comparer, reduced generally area.
The present invention is because all data are all the output on clock edge of same register, and data delay is nearly all the same, i.e. the constant time lag of this fixed route from clock to pin.The first bit data sending has not had the time delay bringing due to complex combination logic, and integrated circuit characteristic is greatly improved, and transfer rate is improved, and chip conforms stronger.Simultaneously, utilize auxiliary counter prediction to load data, make digital audio interface transtation mission circuit can prepare in advance data, shifted out by turn by bit clock (BCLK) again, reduce to judge because of logic the time delay bringing, well improved message transmission rate, improved the temporal characteristics of circuit from framework, good temporal characteristics also makes more digital audio interface agreement better be supported.
The synchronization mechanism of Design assistant counter and counting dexterously, can reduce the use of totalizer, has reduced on the whole the area of circuit.
Brief description of the drawings
Fig. 1 is the module map that realizes data prestrain principle in digital audio interface transtation mission circuit of the present invention.
Fig. 2 is the module map that the present invention realizes data prestrain.
Fig. 3 is that in the embodiment of the present invention, Right Aligns DAB transmission interface utilizes auxiliary counter to realize the sequential chart of data prestrain.
Embodiment
Below in conjunction with accompanying drawing of the present invention, the technical scheme in the preferred embodiment of the present invention is carried out to clear, complete description.
As shown in Figure 1, in digital audio interface transtation mission circuit, comprise clock module, data transmission blocks, shift register and data prestrain unit, clock module produces or processes synchronous clock and bit clock, and data transmission blocks comprises parallel data L channel and parallel data R channel.Taking synchronous clock as reference, data prestrain control module produces prestrain control signal, when data are about to send, parallel L channel data or parallel right data in data transmission blocks is loaded into shift register, shift register is shifted all the time, in the time that synchronous clock (LRCK) arrives, just in time the first bit data is shifted out on bit clock (BCLK) edge, then other bit data are also shifted out by turn on bit clock edge.
As shown in Figure 2, described data prestrain unit comprises detection counter, auxiliary counter and data prestrain control module, in the time adopting auxiliary counter, the reference system of data prestrain control module is auxiliary counter, and the reference system of auxiliary counter is the detection counter synchronous by synchronous clock.Auxiliary counter designs according to digital audio interface agreement etc., produces a unified reference frame, data prestrain control module can directly be judged and produce data prestrain control signal, controls parallel left and right acoustic channels and is written into shift register.
Detection counter is a up counter, and object is to detect synchronous clock (LRCK) and the bit clock (BCLK) of digital audio interface, determines the bit clock rate (BCLKRATIO) of digital audio interface data.Sending synchronous signal at synchronous clock (LRCK) (can be rising edge, also can be negative edge) time to this counter O reset or become clearly particular value, in the time that this synchronous signal arrives again, the current count value of detection counter is exactly the bit clock rate (BCLKRATIO) that we need.According to the count value of the bit clock rate (BCLKRATIO) detecting and detection clock, just can judge the moment that draws preloading data.
Auxiliary counter can be up counter, can be also down counter or other types counter, and this need to determine according to digital audio interface agreement.This in order to reduce decision logic because the hardware consumption that brings of complicated plus and minus calculation designs.It can be hinted obliquely at and obtain according to certain logic by detection counter, also can be reference by detection counter, produce a specific synchronizing signal, taking this particular sync signal as a series of countings of initial generation, also can need in conjunction with above method according to design, both some counting was hinted obliquely at and obtained by detection counter, and also some counting is counted and obtained by own nature.
It is that predicted data loads the moment that data load prediction module, prepare in advance data, in the time that upset occurs digital audio interface synchronous clock (LRCK), interface transtation mission circuit sends data simultaneously under the driving on bit clock (BCLK) edge.Data load prediction module can only judge that detection counter obtains Loading Control signal by certain logic, but this decision logic can take many circuit areas.The introducing of auxiliary counter can be simplified decision logic, and this has also reduced the area of circuit on the whole.
Be illustrated in figure 3 one of preferred embodiment of the present invention, this embodiment is the sequential chart as an example of Right Aligns digital audio interface example.M is the position bit rate of data, detection counter be one from 1 to M 1 counter that adds, when each synchronous clock (LRCK) arrives, all count M.
Auxiliary counter is the down counter of a M to 1, makes auxiliary counter be synchronized to M at detection counter in M-2 when bit clock arrives.The generation of prestrain control signal need to, with reference to auxiliary counter, be in a bit rate subtracts data length in the value of auxiliary counter, produces a data prestrain control signal.
The present invention includes all digital audio interface agreements, under different agreement, adopt different auxiliary counters, auxiliary counter to be selected from and add 1 counter, subtract counter or the counter combination of 1 counter and other types.
Technology contents of the present invention and technical characterictic have disclosed as above; but those of ordinary skill in the art still may be based on teaching of the present invention and announcements and are done all replacement and modifications that does not deviate from spirit of the present invention; therefore; protection domain of the present invention should be not limited to the content that embodiment discloses; and should comprise various do not deviate from replacement of the present invention and modifications, and contained by present patent application claim.
Claims (5)
1. a method that realizes data prestrain in digital audio interface transtation mission circuit, is characterized in that, the method comprises:
A. detect synchronous clock and the bit clock in audio interface transtation mission circuit by detection counter, and determine the bit clock rate of digital audio interface and the count value of detection clock;
B. produce synchronizing signal by detection counter to auxiliary counter, carried out the counting being associated with described detection counter by auxiliary counter according to this synchronizing signal;
C. data prestrain control module, according to the count value of described auxiliary counter, according to the requirement of digital audio interface agreement, judges the moment of sending data, and determines that the one-period sending before data is the data preparatory period of preparing data;
D. data prestrain control module sends data prestrain control signal to digital sending module in the data preparatory period, by data transmission blocks, data to be sent is loaded in shift register and is ready for sending;
E. the first bit data is sent out on bit clock edge in the time that synchronous clock arrives by shift register.
2. method according to claim 1, is characterized in that: described auxiliary counter is hinted obliquely at and obtains by certain logic by described detection counter.
3. method according to claim 1, is characterized in that: in described data transmission blocks, have parallel L channel data and parallel right data.
4. a device of realizing data prestrain in digital audio interface transtation mission circuit, is characterized in that: comprise clock module, data transmission blocks and register, and detection counter, auxiliary counter, data prestrain control module; Wherein: described detection counter is for detection of the synchronous clock in described clock module and bit clock, with the bit clock rate of specified data; The counting of described auxiliary counter is hinted obliquely at and obtains by certain logic by described detection counter, described auxiliary counter is taking detection counter as reference, and produce synchronizing signal by detection counter, auxiliary counter taking this synchronizing signal as initial counting; Described data prestrain control module is with reference to the count value of described auxiliary counter, controls the one-period that described data transmission blocks sends before data at described register and is ready to data to be sent.
5. device according to claim 4, is characterized in that: described auxiliary counter is for being selected from up counter, the one in down counter and other type counter.
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| CN103731411B (en) * | 2012-10-16 | 2019-05-31 | 马维尔国际贸易有限公司 | The configurable serial link of high bandwidth |
| CN106936847A (en) * | 2017-04-11 | 2017-07-07 | 深圳市米尔声学科技发展有限公司 | The processing method and processor of voice data |
| CN115174305B (en) * | 2022-06-28 | 2023-11-03 | 珠海一微半导体股份有限公司 | IIS interface-based data conversion control system and chip |
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| US5671445A (en) * | 1993-07-19 | 1997-09-23 | Oki America, Inc. | Interface for transmitting graphics data to a printer from a host computer system in rasterized form |
| CN1521599A (en) * | 2003-02-12 | 2004-08-18 | ��ķɭ���ó��˾ | Method and apparatus for pre-processing in a common-format control processing input signals of, or output signals for, interfaces of different type |
| CN1716187A (en) * | 2004-06-30 | 2006-01-04 | 株式会社东芝 | Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program |
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| US7145486B1 (en) * | 2005-03-24 | 2006-12-05 | Cirrus Logic, Inc. | Circuits and methods for exchanging data through a serial port and systems using the same |
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| US5671445A (en) * | 1993-07-19 | 1997-09-23 | Oki America, Inc. | Interface for transmitting graphics data to a printer from a host computer system in rasterized form |
| CN1521599A (en) * | 2003-02-12 | 2004-08-18 | ��ķɭ���ó��˾ | Method and apparatus for pre-processing in a common-format control processing input signals of, or output signals for, interfaces of different type |
| CN1716187A (en) * | 2004-06-30 | 2006-01-04 | 株式会社东芝 | Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program |
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