CN102468835B - Differential sensing and silicon crystal perforating hole time sequence control structure of three-dimensional chip - Google Patents
Differential sensing and silicon crystal perforating hole time sequence control structure of three-dimensional chip Download PDFInfo
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- CN102468835B CN102468835B CN201010536697.6A CN201010536697A CN102468835B CN 102468835 B CN102468835 B CN 102468835B CN 201010536697 A CN201010536697 A CN 201010536697A CN 102468835 B CN102468835 B CN 102468835B
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Abstract
The invention relates a differential sensing and silicon crystal perforating hole time sequence control structure of a three-dimensional chip, comprising a first chip layer of a stack component , wherein the first chip layer includes a detection circuit and a relative high-capacity driver which is horizontally coupled to the detection circuit, a sensing circuit which is coupled to the detection circuit via a horizontal lead, a first differential signal driver which is horizontally coupled to the sensing circuit in a first chip layer, and an Nth chip layer of the stack component , wherein the Nth chip layer includes an Nth relative high-capacity driver and an Nth differential signal driver formed on the Nth chip layer, wherein the Nth relative high-capacity driver penetrates a vertical relative low-load silicon crystal perforating hole and (N-2) relative high-load silicon crystal perforating holes as virtual loads to be vertically coupled to a first relative high-capacity driver, and the Nth differential signal driver penetrates a pair of relative low-load silicon crystal perforating holes and (N-2) pairs of relative high-load silicon crystal perforating holes to be vertically coupled to the first differential signal driver.
Description
[technical field]
The present invention is about a kind of three-dimensional stack chip assembly, and special system has about a kind of differential sensing of three-dimensional chip and silicon wafer perforation time sequence control structure.
[background technology]
Recently portable electronic device, for example mobile phone and non-volatility semiconductor memory media (for example integrated circuit memory card), minification designs or manufactures, and the minimizing of newly-increased demand wish is used for the number of parts of equipment and media and dwindles its size.Therefore,, in semi-conductor industry, the encapsulation technology of integrated circuit has advanced to and has met miniaturization and the demand of following reliability.For example, the demand of miniaturization and cause the accelerated development of encapsulation technology, makes it have the similar size to semiconductor chip.Moreover then the importance of reliability in encapsulation technology is to promote the then efficiency of processing procedure, and after completing, improve machinery and electrical fiduciary level in then processing procedure.Therefore, existing considerable work is to develop packaged semiconductor efficiently.The encapsulation that meets the demand comprises: the chip size packages (CSP) with the rough package size that equals semi-conductor chip, have multiple semiconductor chips to include heavy chip package more than a single encapsulation in, and multiple packaging body storehouse and the storehouse that is incorporated into a monolithic structure dress encapsulate.
Along with the development of technology, the increase of the relative required storage volume of response memory, and the semiconductor subassembly (multiple chip assembly) of proposition storehouse kenel, it has semiconductor integrated circuit chip storehouse together.In other words, it is the storehouse kenel semiconductor subassembly that provides at least two SIC (semiconductor integrated circuit) assembly storehouses to be formed, each has specification and comprises semiconductor integrated circuit (IC) chip, wherein each SIC (semiconductor integrated circuit) assembly comprises that a conductor passes wherein, and SIC (semiconductor integrated circuit) assembly is electrically connected by conductor, and above-mentioned specification value comprises that the size of the superiors or orlop SIC (semiconductor integrated circuit) assembly is maximum or minimum.Therefore, storehouse kenel semiconductor subassembly has a plurality of chip stacks in a vertical direction.In storehouse kenel semiconductor subassembly, chip system for example sees through and is electrically connected through the connector (plugs) of chip.Therefore, selecting the storehouse memory chip of a suitable same structure is a important work.If a storehouse kenel semiconductor subassembly completes manufacture, chip can be individually by operational testing, and only normal chip can be selected and storehouse.
One provides technology connected vertically to be called silicon wafer perforation (TSV), and it has become a promising solution of three-dimensional heap stack component.In above-mentioned technology, vertically connect linear system and form through wafer, and make to be linked up between stack chip.A relevant paper can be " utilizing the three-dimensional DDR3 DRAM (Dynamic Random Access Memory) of 8 kilomegabits of silicon wafer puncturing technique " (IEEE, JOURNAL OF SOLID-STATECIRCUITS, VOL.45, NO.1, JANUARY 2010) with reference to title.In this paper, the proposition that has a silicon wafer perforation Three-Dimensional Dynamic random access memory has been the restriction that overcomes traditional modular approach.It also discloses how to design this structure and data routing.It also discloses the silicon wafer perforation connectivity inspection and the restorative procedure that comprise 3-D technology, and power noise reduction method.Silicon wafer perforation can see through simple mode and form after dispatching from the factory, and therefore integrates without separately add special processing procedure during normal processing procedure.Chip identification system normally distributes.
In data communication system, it is typically the independent receiving unit that utilizes a transmission assembly operating under first frequency and to operate under second frequency.Typically, transmission assembly and receiving unit have a frequency velocity contrast.The data that this frequency velocity contrast causes recipient to see coming in than expection sooner or slower, be called " timing off-set " herein.For packet basis communication system, if during the possible timing off-set maximum during package is less than a symbol, frequency velocity contrast can be left in the basket.The U.S. the 7th, 003,056 patent discloses a kind of symbol sequential and follows the trail of and method, and it is to utilize sequential to follow the trail of the timing off-set coming due to the difference on the frequency of transmission frequency and receive frequency with calibration.Follow the trail of by sequential, the correlation of three serial samplings can utilize reception signal to calculate with replying symbol, then calculates its summation.In addition, static random stored memory is widely used in application that speed has importance, and for example high-speed cache is to be typically placed in the processor or the central processing unit that are bordering on personal computer most.But the sequential of its internal circuit may seriously affect speed and the efficiency of static random stored memory.For example, between bit line charge period, comprise appreciable read/write cycles, and sensing amplifier use is showing for the overall power consumption contribution of static random stored memory.In static random stored memory design in early days, read/write cycles system is based on an outside pulse signal producing.Another known techniques is exposed in the U.S. the 7th, and in 003,056 patent, it comprises that self-timing circuit is to reduce the write cycle of semiconductor internal memory.One virtual memory structure cell has identical sequential demand using as function structure cell, and the relevant preferred circuit of logical add to memory subassembly that write.Virtual write structure cell receive identical control signal in order to data writing the function structure cell to this internal memory, and send one after finishing and complete signal when writing access, cause termination write cycle.This circuit and method allow time write cycle to be reduced to minimum effective value, are independent of the read cycle time.This potential integrated operation speed that has increased memory subassembly.
The differential sensing and the silicon wafer that the invention provides a kind of three-dimensional heap stack component are bored a hole sequential control to improve loading problem, as shown in figure mono-.The time delay being caused by loading problem is even worse in more chip layer.Therefore, the invention provides the three-dimensional chip sensing of a novelty and the method for sequential control to address this problem.
[summary of the invention]
One of the present invention viewpoint is to provide a kind of differential sensing of three dimensional integrated circuits and method and the structure of silicon wafer perforation sequential control.
The differential sensing of three dimensional integrated circuits and silicon wafer perforation time sequence control structure, comprise a relatively high capable drives (impact damper), one dummy load couples relatively high capable drives (impact damper) and dodges control signal to transmit a sequential, and a testing circuit couples dummy load.One differential signal produces structure and couples a relatively low capable drives (impact damper) to produce a differential signal.One sensing circuit couples differential signal and produces structure.In the time that an active signal reaches to a trigger point, testing circuit starts sensing circuit.
Differential signal produces structure and comprises that a pair of high capacity structure couples a relatively low capable drives, and a reverser is disposed at this between one of relative high capacity structure and relative low capable drives.This comprises a pair of silicon wafer perforation to relative high capacity structure.Dummy load comprises a silicon wafer perforation.
The transmission speed of relatively high capable drives is greater than the transmission speed of relatively low capable drives.In one embodiment, the transmission speed of relatively high capable drives is the doubly transmission speed of relatively low capable drives of x.Sensing circuit comprises a sensing amplifier, a comparer or an operational amplifier.
Under the framework of above-mentioned three-dimensional viewpoint, one has differential sensing and the silicon wafer perforation time sequence control structure of the heap stack component of plural layer, comprise: the first chip layer of a pile stack component, comprises that a testing circuit high capable drives level relative to couples testing circuit.One sensing circuit, couples testing circuit by a horizontal wire.One first differential signal driver, in the first chip layer, level couples sensing circuit.The N chip layer of a pile stack component, comprise that the relatively high capable drives of a N and a N differential signal driver are formed on N chip layer, N is greater than 1 natural number, wherein the relatively high capable drives of N system see through that vertically opposite low load silicon wafer perforation high capacity silicon wafer relative to (N-2) bored a hole as dummy load and the vertical first-phase that couples to high capable drives, relatively low load silicon wafer perforation high capacity silicon wafer perforation relative to (N-2) system is from N chip layer to the first chip layer and through heap stack component, wherein relatively low load silicon wafer perforation high capacity silicon wafer perforation relative to (N-2) is formed in a shared structure, wherein N differential signal driver system bores a hole and the vertical first differential signal driver that couples to relative high capacity silicon wafer with (N-2) through a pair of relatively low load silicon wafer perforation, this is from N layer to ground floor and through heap stack component to relatively low load silicon wafer perforation with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation, each relatively low load silicon wafer perforation is to be formed between first and second chip layer, each relative high capacity silicon wafer perforation is to be formed between arbitrary adjacent two chip layer of heap stack component, by this in the time that an active signal reaches to a trigger point, testing circuit starts sensing circuit.
[brief description of the drawings]
Said modules, and further feature of the present invention and advantage, by read hold within embodiment and graphic after, will be more obvious:
Fig. 1 demonstration is asked figure according to the load of known techniques.
Fig. 2 shows the differential sensing of the three-dimensional chip according to the present invention and the functional block diagram of silicon wafer perforation time sequence control structure.
Fig. 3 shows the differential sensing of the three-dimensional chip according to the present invention and the functional block diagram of silicon wafer perforation time sequence control structure.
Fig. 4 shows that the differential sensing of the three-dimensional chip according to the present invention and the three-dimensional plot of silicon wafer perforation time sequence control structure indicate intention.
In figure:
100,300 drivers or impact damper
101 first high capacity structures
200,400 reversers
210a the second high capacity structure (silicon wafer perforation)
210b third high support structures (silicon wafer perforation)
220,420 sensing circuits
310 virtual silicon wafer perforation (dummy load)
315 testing circuits
The relative low level driver of 405a, 405b (impact damper)
410a, the perforation of 410b silicon wafer
The relatively high capable drives of 300L1
C1 wire
The relatively high capable drives of 300LN N
422L1 the first differential signal driver
422LN N differential signal driver
[embodiment]
The present invention is specified in down its preferred embodiment of cooperation and the diagram of enclosing.Should the person of understanding be that preferred embodiments all in the present invention is only the use of illustration, be not in order to restriction.Therefore the preferred embodiment in literary composition, the present invention also can be widely used in other embodiment.And the present invention is not limited to any embodiment, should be with the claim of enclosing and equivalent fields thereof and determine.
The differential sensing and the silicon wafer perforation time sequence control structure that present invention is directed to three-dimensional chip, it can be introduced in embedded volatility or non-voltile memory.In a preferred embodiment, as shown in Figure 2, the present invention discloses a differential sensing structure, and it comprises a driver or impact damper 100, couples one first high capacity structure 101.One signal input couples the other end of driver or impact damper 100, and a signal output electric property connects the first high capacity structure, and it can see through silicon wafer perforation 101 and form.This structure more comprises one second high capacity structure (silicon wafer perforation) 210a and third high support structures (silicon wafer perforation) 210b, and the two considers can be configured in parallel structure according to design above-mentioned the second silicon wafer perforation 210a and the 3rd silicon wafer perforation 210b.Can also utilize other structure configuration.Signal input couples the second silicon wafer perforation 210a, and a reverser 200 is disposed between signal input and the 3rd silicon wafer perforation 210b.Next, a sensing circuit 220 couples respectively the second silicon wafer perforation 210a and the 3rd silicon wafer perforation 210b.Signal output couples the other end of sensing circuit 220.In the differential sensing structure of Fig. 2, also show respectively VDD sequential chart.For the first silicon wafer perforation 101, its trigger point (trigger point) is the half of VDD, if trigger point horizontal-extending to reach the A point of VDD sequential chart, is time shaft and point of crossing from the vertical extension line of A point readout time.Similarly, for the second silicon wafer perforation 210a and the 3rd silicon wafer perforation 210b, its sensing boundary is compared with higher than trigger point, that is higher than 1/2nd VDD.Therefore, read on VDD sequential line, it will be between signal line and VDD sequential line.
With reference to figure 3, it shows one of the present invention preferred embodiment.It shows the silicon wafer perforation sequential control of different sensings, and this structure comprises that a relative high levels driver or impact damper 300 couple a virtual silicon wafer with high capacity (dummy load) 310 of boring a hole.One sequential sudden strain of a muscle control signal (timing strobe signal) couples the other end of driver or impact damper 300, and a testing circuit 315 is electrically connected virtual silicon wafer perforation (dummy load) 310.This differential signal structure comprises a pair of high capacity structure, in an example, this can be formed by a pair of silicon wafer perforation 410a and silicon wafer perforation 410b high capacity structure, and this sees through relative low level driver (impact damper) 405a and 405b respectively and couple signal input with silicon wafer perforation 410b silicon wafer perforation 410a.It should be noted that a reverser 400 is disposed between signal input and relative low level driver (impact damper) 405b.Next, a sensing circuit 420 couple respectively this to high capacity structure the two.Signal output couples the other end of sensing circuit 420.Aforementioned testing circuit 315 couples sensing circuit 420.Preferably, sequential sudden strain of a muscle control signal is almost identical with signal input.In a preferred embodiment, high levels driver (impact damper) 300 has several times of efficiency in relative low level driver (impact damper) 405a or 405b relatively.
Please refer to Fig. 3, it then illustrates the sequential control of silicon wafer perforation differential sensing.Initial step is that input timing dodges control signal to relative high levels driver (impact damper).True signal inputs to relative low level driver (impact damper) 405a and 405b.Signal through reverser 400 will oppositely also postpone from initial input signal, and reverse signal waveform can be found out from the upper right portion of Fig. 3.Therefore, via reverser 400, the signal of arrival high capacity structure 410b will be reversed.On the contrary, the signal that does not arrive another high capacity structure 410a through reverser 400 still remains identical.Now sensing circuit 420 is normally to cut out.Because load is heavy, therefore transmitted by differential signal.When the difference of differential signal is greater than 100mV (0.1 volt), next open sensing circuit 420, therefore determine that digital state is 1 or 0.
The poor system of 100mV (0.1 volt) is by circuit decision, and it has dummy load 310 and couples testing circuit 315.VDD sequential chart can with reference to second with the diagram of Fig. 3.This diagram is meaning signal through dummy load 310.This to high capacity structure 410a and 410b the output display in VDD sequential chart in the right of Fig. 2 and Fig. 3.One virtual signal is by a well-known active signal that dummy load 310 copies to transmit, and the driver 300 of number (x) times ability is introduced to dummy load 310.Suppose that VDD is 1.8 volts, the half that trigger point is VDD, 0.9 volt.As a result, when the difference of differential signal is greater than 100mV (0.1 volt), the signal of dummy load reaches to trigger point, and therefore the value of x is 9.Its transmission speed that is meaning dummy load 310 is larger to differential signal structure than this.Similarly, if VDD is 1 volt, x value is 5.
When active signal, in the step 2 of figure tri-, reach to trigger point, testing circuit 315 should be opened sensing circuit 420 as early as possible.In a preferred embodiment, testing circuit 315 is to form by least one reverser, to detect generation surging, in the step 3 of figure tri-.Most important one is that reverser need accord with should this sensing sequential.Sensing circuit 420 can be a sensing amplifier or a comparer or an operational amplifier.Finally, signal is exported from sensing circuit, in the step 4 of figure tri-.Loading problem can be easily overcome by silicon wafer perforation sequential control and differential sensing structure.
Fig. 4 shows the present invention's three-dimensional structure, and three-dimensional heap stack component comprises a plurality of stack chip layers, and it comprises that an other chip (not icon) is positioned at each chip layer.Within first chip layer (ground floor) of three-dimensional heap stack component comprises that a testing circuit 315 is positioned at a presumptive area, a relatively high capable drives 300L1 coupled in parallel testing circuit 315.One sensing circuit 420 is disposed at one of the first chip layer presumptive area, and couples testing circuit 315 by a horizontal wire C1.One differential signal driver 422L1 level couples sensing circuit 420.The structure of other chip layer of heap stack component is except there is no testing circuit 315 and sensing circuit 420, similar with the first chip layer.The N chip layer (N layer) of three-dimensional heap stack component also comprises that the relatively high capable drives 300LN of a N is positioned on the appointed area of N layer chip layer, and a N differential signal driver 422LN is also disposed on N chip layer; N is greater than 1 natural number.The relatively high capable drives 300LN of N system see through that vertically opposite low load silicon wafer perforation high capacity silicon wafer relative to (N-2) bored a hole and the vertical first-phase that couples to high capable drives 300L1, shown in its TSVx by Fig. 4 (N-2), all relatively low load silicon wafer perforation high capacity silicon wafer perforation relative to (N-2) systems are from the upper heap stack component that passes the end of to, and wherein relatively low load silicon wafer perforation high capacity silicon wafer perforation relative to (N-2) is formed in a shared structure.Similarly, N differential signal driver 422LN system bores a hole and the vertical first differential signal driver 422L1 that couples to relative high capacity silicon wafer with (N-2) through a pair of relatively low load silicon wafer perforation, and all relatively low load silicon wafer perforation are from n layer to ground floor and through piling stack component with (N-2) to relative high capacity silicon wafer perforation.It should be noted that each relatively low load silicon wafer perforation is to be formed between first and second chip layer.(N-2) relatively high capacity silicon wafer perforation system is formed at, between first and second chip layer, between arbitrary adjacent two chip layer of heap stack component.Its mechanism with method of operating be illustrated in the 3rd with Fig. 4 in.Therefore, omit its unnecessary narration.
One embodiment is one of the present invention example or example.Be described in it " embodiment " in instructions, " some embodiment " or " other embodiment " mean describe and one of be linked in this embodiment in the involved minimum embodiment of specific characteristic, structure or characteristic, but not all embodiment are all essential.The narration of the difference such as " embodiment " or " some embodiment " means and nonessential this some embodiment that mention.It should be noted that in the specific embodiment of narrating above about the present invention, different characteristic sometimes can be gathered in a single embodiment, graphic or narration and is in order to simplified illustration and helps the understanding to one or more different aspect of the present invention.But this exposure method should not be used to the invention category that reflection is asked, thereby the feature in described example is added in each claim.Otherwise, can be less than all features in the above-mentioned single embodiment disclosing in following the present invention's that claim reflects viewpoint.Therefore, described embodiment is contained in claim system, and each claim itself all can be considered the independent embodiment of one of the present invention.
Claims (8)
1. differential sensing and a silicon wafer perforation time sequence control structure with the heap stack component of plural layer, is characterized in that comprising:
The first chip layer of one this heap stack component, comprises that a time sequence detecting circuit high capable drives relative to couples this time sequence detecting circuit in identical chips layer level;
One sensing circuit couples this time sequence detecting circuit by a horizontal wire in this first chip layer;
One first differential signal driver, in this first chip layer, level couples this sensing circuit; And
The N chip layer of one this heap stack component, comprise that the relatively high capable drives of a N and a N differential signal driver are formed on this N chip layer, this N is greater than 1 natural number, wherein the relatively high capable drives of this N system see through that vertically opposite low load silicon wafer perforation high capacity silicon wafer relative to (N-2) bored a hole as dummy load and vertical this first-phase that couples to high capable drives, this relatively low load silicon wafer perforation is from this N chip layer to this first chip layer and through this heap stack component with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation, wherein this relatively low load silicon wafer is bored a hole and should (N-2) relative high capacity silicon wafer perforation be formed in a shared structure, wherein this N differential signal driver system bores a hole and vertical this first differential signal driver that couples to relative high capacity silicon wafer with (N-2) through a pair of relatively low load silicon wafer perforation, this is from N layer to this first chip layer and through this heap stack component to relatively low load silicon wafer perforation with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation, each this relatively low load silicon wafer perforation is to be formed between this first and second chip layer, each this relative high capacity silicon wafer perforation is to be formed between arbitrary adjacent two chip layer of this heap stack component, by this in the time that an active signal reaches to a trigger point, this testing circuit starts this sensing circuit,
One of this relatively low load silicon wafer perforation high capacity silicon wafer perforation relative to this (N-2) couples a sequential and dodges control signal, and this is bored a hole to relatively low load silicon wafer and should (N-2) couple an input signal to relative high capacity silicon wafer perforation.
2. there is as claimed in claim 1 differential sensing and the silicon wafer perforation time sequence control structure of the heap stack component of plural layer, it is characterized in that more comprising relatively low capable drives and a reverser, this reverser is disposed at N between one of relative high capacity silicon wafer perforation low capable drives relative to this, the transmission speed of this relatively high capable drives is greater than the transmission speed of this relatively low capable drives, the transmission speed of this relatively high capable drives is the doubly transmission speed of relatively low capable drives of x, and this x is doubly greater than one depending on sensing boundary and the x of this sensing circuit.
3. differential sensing and the silicon wafer perforation time sequence control structure as claimed in claim 1 with the heap stack component of plural layer, is characterized in that this time sequence detecting circuit comprises at least one reverser.
4. differential sensing and the silicon wafer perforation time sequence control structure as claimed in claim 1 with the heap stack component of plural layer, is characterized in that this sensing circuit comprises a sensing amplifier, a comparer or an operational amplifier.
5. differential sensing and a silicon wafer perforation time sequence control structure with the heap stack component of plural layer, is characterized in that comprising:
The first chip layer of one this heap stack component, comprises that a time sequence detecting circuit high ability buffer level relative to couples this time sequence detecting circuit;
One sensing circuit couples this time sequence detecting circuit by a horizontal wire in this first chip layer;
One first differential signal impact damper, level couples this sensing circuit; And
The N chip layer of one this heap stack component, comprise that the relatively high ability impact damper of a N and a N differential signal impact damper are formed on this N chip layer, this N is greater than 1 natural number, wherein the relatively high ability impact damper of this N system see through that relatively low load silicon wafer perforation high capacity silicon wafer relative to (N-2) bored a hole as dummy load and vertical this first-phase that couples to high ability impact damper, this relatively low load silicon wafer perforation is from this N chip layer to this first chip layer and through this heap stack component with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation, wherein this relatively low load silicon wafer is bored a hole and should (N-2) relative high capacity silicon wafer perforation be formed in a shared structure, wherein this N differential signal impact damper system bores a hole and vertical this first differential signal impact damper that couples to relative high capacity silicon wafer with (N-2) through a pair of relatively low load silicon wafer perforation, this is from N layer to this first chip layer and through this heap stack component to relatively low load silicon wafer perforation with being somebody's turn to do (N-2) relative high capacity silicon wafer perforation, each this relatively low load silicon wafer perforation is to be formed between this first and second chip layer, each this relative high capacity silicon wafer perforation is to be formed between arbitrary adjacent two chip layer of this heap stack component, by this in the time that an active signal reaches to a trigger point, this testing circuit starts this sensing circuit,
One of this relatively low load silicon wafer perforation high capacity silicon wafer perforation relative to this (N-2) couples a sequential and dodges control signal, and this is bored a hole to relatively low load silicon wafer and should (N-2) couple an input signal to relative high capacity silicon wafer perforation.
6. there is as claimed in claim 5 differential sensing and the silicon wafer perforation time sequence control structure of the heap stack component of plural layer, it is characterized in that more comprising relatively low ability impact damper and a reverser, this reverser is disposed at N between one of relative high capacity silicon wafer perforation low ability impact damper relative to this, the transmission speed of this relatively high ability impact damper is greater than the transmission speed of this relatively low ability impact damper, and the transmission speed of this relatively high ability impact damper is the doubly transmission speed of this relatively low ability impact damper of x.
7. differential sensing and the silicon wafer perforation time sequence control structure as claimed in claim 5 with the heap stack component of plural layer, is characterized in that this testing circuit comprises at least one reverser.
8. differential sensing and the silicon wafer perforation time sequence control structure as claimed in claim 5 with the heap stack component of plural layer, is characterized in that this sensing circuit comprises a sensing amplifier, a comparer or an operational amplifier.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767699A (en) * | 1996-05-28 | 1998-06-16 | Sun Microsystems, Inc. | Fully complementary differential output driver for high speed digital communications |
| CN1637938A (en) * | 2003-12-29 | 2005-07-13 | 海力士半导体有限公司 | Semiconductor memory device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767699A (en) * | 1996-05-28 | 1998-06-16 | Sun Microsystems, Inc. | Fully complementary differential output driver for high speed digital communications |
| CN1637938A (en) * | 2003-12-29 | 2005-07-13 | 海力士半导体有限公司 | Semiconductor memory device |
Non-Patent Citations (2)
| Title |
|---|
| 《8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology》;Uksong Kang et al;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20100131;第45卷(第1期);第111页至第117页以及附图1至12 * |
| Uksong Kang et al.《8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology》.《IEEE JOURNAL OF SOLID-STATE CIRCUITS》.2010,第45卷(第1期),第111页至第117页以及附图1至12. |
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