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Publication numberCN102468835 A
Publication typeApplication
Application numberCN 201010536697
Publication date23 May 2012
Filing date5 Nov 2010
Priority date5 Nov 2010
Also published asCN102468835B
Publication number201010536697.6, CN 102468835 A, CN 102468835A, CN 201010536697, CN-A-102468835, CN102468835 A, CN102468835A, CN201010536697, CN201010536697.6
Inventors吴威震, 张孟凡, 陈炎辉
Applicant张孟凡
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Differential sensing and silicon crystal perforating hole time sequence control structure of three-dimensional chip
CN 102468835 A
Abstract
The invention relates a differential sensing and silicon crystal perforating hole time sequence control structure of a three-dimensional chip, comprising a first chip layer of a stack component , wherein the first chip layer includes a detection circuit and a relative high-capacity driver which is horizontally coupled to the detection circuit, a sensing circuit which is coupled to the detection circuit via a horizontal lead, a first differential signal driver which is horizontally coupled to the sensing circuit in a first chip layer, and an Nth chip layer of the stack component , wherein the Nth chip layer includes an Nth relative high-capacity driver and an Nth differential signal driver formed on the Nth chip layer, wherein the Nth relative high-capacity driver penetrates a vertical relative low-load silicon crystal perforating hole and (N-2) relative high-load silicon crystal perforating holes as virtual loads to be vertically coupled to a first relative high-capacity driver, and the Nth differential signal driver penetrates a pair of relative low-load silicon crystal perforating holes and (N-2) pairs of relative high-load silicon crystal perforating holes to be vertically coupled to the first differential signal driver.
Claims(10)  translated from Chinese
1. 一种具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构,其特征在于包括:一该堆栈组件之第一芯片层,包括一时序检测电路与一相对高能力驱动器于相同芯片层水平耦接该时序检测电路;一感测电路,藉由一水平导线于该第一芯片层中耦接该时序检测电路;一第一差动讯号驱动器,于该第一芯片层中水平耦接该感测电路;以及一该堆栈组件之第N芯片层,包括一第N相对高能力驱动器与一第N差动讯号驱动器形成于该第N芯片层之上,该N为大于1的自然数,其中该第N相对高能力驱动器系透过一垂直相对低负载硅晶穿孔与(N-幻相对高负载硅晶穿孔作为虚拟负载而垂直耦接该第一相对高能力驱动器,该相对低负载硅晶穿孔与该(N-2)相对高负载硅晶穿孔系从该第N芯片层至该第一芯片层而穿过该堆栈组件,其中该相对低负载硅晶穿孔与该(N-2)相对高负载硅晶穿孔形成于一共享结构中,其中该第N差动讯号驱动器系透过一对相对低负载硅晶穿孔与(N-2)对相对高负载硅晶穿孔而垂直耦接该第一差动讯号驱动器,该对相对低负载硅晶穿孔与该(N-幻相对高负载硅晶穿孔系从第N层至第一层而穿过该堆栈组件,每一该相对低负载硅晶穿孔系形成于该第一与第二芯片层之间,每一该相对高负载硅晶穿孔系形成于该堆栈组件之任一相邻二芯片层之间,藉此当一主动讯号达至一触发点时,该检测电路启动该感测电路。 A dynamic test with a difference of a plurality of layers of the stack components and perforated silicon timing control structure, comprising: a first chip layer of the stack components, including a timing detection circuit and a relatively high capacity drives in the same layer chip level detection circuit coupled to the timing; a sensing circuit, by a horizontal wire to the first chip layer coupled to the timing detection circuit; a first differential signal drive level to the first chip layer coupled to the sensing circuit; and an N-chip layer of the stack components, including a first N relatively high capacity drive with an N-drive differential signal is formed over the first layer of N chip, the N is greater than 1 natural number, in which the first N relatively high capacity drive system through a relatively low vertical load perforated silicon and (N- Magic relatively high load perforated silicon as a virtual vertical load coupled to the first relatively high capacity drive, which is relatively low Load perforated silicon and the (N-2) relatively high load perforated silicon-based chip from the N-th layer to the first chip layer through the stack assembly, in which the relatively low load perforated silicon and the (N- 2) a relatively high load perforated silicon formed in a shared arrangement, in which the first N differential signal line drive through a pair of opposing low load perforated silicon and (N-2) to a relatively high load perforated silicon and vertical coupling then the first differential signal drive, the relatively low load perforated silicon and the (N- Magic relatively high load system from perforated silicon N layer to the first layer through the stack components, each of which is relatively low Load silicon perforation line formed between the first and second chip layer, each of which is relatively high load perforated silicon-based form to any component of this stack between the two chips in an adjacent layer, whereby when an active signal up to a trigger point, the detection circuit starts the sensing circuit.
2.如权利要求1所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于更包括一相对低能力驱动器与一反向器,该反向器配置于该N对相对高负载硅晶穿孔之一与该相对低能力驱动器之间,该相对高能力驱动器之传输速度大于该相对低能力驱动器之传输速度,该相对高能力驱动器之传输速度为χ倍相对低能力驱动器之传输速度,该χ端视该感测电路的感测界限且χ大于一。 2. The difference between a dynamic measurement of the stack assembly having a plurality of perforations silicon layer and a timing control structure as claimed in claim further characterized by comprising a relatively low capacity and a drive inverter, the inverter configured to the N between one perforated silicon relatively high load and the relatively low capacity of the drive, the relatively high capacity drive of the transfer speed is greater than the relatively low ability to drive the transmission speed, the relatively high capacity drive of the transmission speed of χ times relatively low the ability to drive the transmission speed, the χ end view of the sensing circuit to sense the limits and χ greater than one.
3.如权利要求1所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于该时序检测电路包括至少一反向器。 1. The claim has poor dynamic measurements of a plurality of layers of the stack components and perforated silicon timing control structure, characterized in that the timing detection circuit includes at least one inverter.
4.如权利要求1所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于该感测电路包括一感测放大器、一比较器或一操作放大器。 4. The difference between a dynamic measurement of the stack assembly having a plurality of layers of silicon and perforation timing control structure as claimed in claim wherein the sensing circuit comprises a sense amplifier, a comparator or an operational amplifier.
5.如权利要求1所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于该相对低负载硅晶穿孔之一与该(N-2)相对高负载硅晶穿孔耦接一时序闪控讯号,该对相对低负载硅晶穿孔与该(N-2)对相对高负载硅晶穿孔耦接一输入讯号。 5. as claimed in claim 1 having a difference of dynamic measurements of a plurality of layers of the stack components and perforated silicon timing control structure, wherein one silicon perforation of the relatively low load and the (N-2) relatively high load silicon Crystal perforation is coupled to a timing strobe signal, the relatively low load perforated silicon and the (N-2) to a relatively high load perforated silicon coupled to an input signal.
6. 一种具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构,其特征在于包括:一该堆栈组件之第一芯片层,包括一时序检测电路与一相对高能力缓冲器水平耦接该检测电路;一感测电路,藉由一水平导线于该第一芯片层中耦接该检测电路;一第一差动讯号缓冲器,水平耦接该感测电路;以及一该堆栈组件之第N芯片层,包括一第N相对高能力缓冲器与一第N差动讯号缓冲器形成于该第N芯片层之上,该N为大于1的自然数,其中该第N相对高能力缓冲器系透过一相对低负载硅晶穿孔与(N-幻相对高负载硅晶穿孔作为虚拟负载而垂直耦接该第一相对高能力缓冲器,该相对低负载硅晶穿孔与该(N-2)相对高负载硅晶穿孔系从该第N芯片层至该第一芯片层而穿过该堆栈组件,其中该相对低负载硅晶穿孔与该(N-幻相对高负载硅晶穿孔形成于一共享结构中,其中该第N差动讯号缓冲器系透过一对相对低负载硅晶穿孔与(N-幻对相对高负载硅晶穿孔而垂直耦接该第一差动讯号缓冲器,该对相对低负载硅晶穿孔与该(N-幻相对高负载硅晶穿孔系从第N层至该第一层而穿过该堆栈组件,每一该相对低负载硅晶穿孔系形成于该第一与第二芯片层之间,每一该相对高负载硅晶穿孔系形成于该堆栈组件之任一相邻二芯片层之间,藉此当一主动讯号达至一触发点时,该检测电路启动该感测电路。 A test having poor dynamic stack assembly of a plurality of layers of silicon and perforation timing control structure, comprising: a first layer of a chip of the stack assembly, comprising a timing detection circuit and a relatively high level of capacity buffer coupled to the detection circuit; a sensing circuit, by a horizontal wire to the first chip layer coupled to the detection circuit; a first differential signal buffer, coupled to the level sensing circuit; and one of the stack The first chip layer assembly of N, N includes a first buffer and a relatively high ability of the N-th differential signal buffer formed on said first layer of N chips, where N is the natural number greater than 1, wherein the relatively high capacity of the first N buffer system through a relatively low load perforated silicon and (N- Magic relatively high load perforated silicon as a virtual vertical load coupled to the first relatively high capacity buffer, the relatively low load perforated silicon and the (N -2) relatively high load perforated silicon-based chip from the N-th layer to the first chip layer through the stack assembly, in which the relatively low load perforated silicon and the (N- Magic relatively high load perforated silicon form in a shared arrangement, in which the first N differential signal buffer system through a pair of opposed perforated silicon with low load (N- Magic to a relatively high load perforated silicon vertical coupled to the first differential signal buffer The relatively low load perforated silicon and the (N- Magic relatively high load system from perforated silicon N layer to the first layer through the stack components, each of which is relatively low load perforated silicon is formed over between the first and second chip layer, each of which is relatively high load between any of the components of the stack to a second layer adjacent to perforated silicon chip-based form, whereby when an active signal up to a trigger point, The detection circuit starts the sensing circuit.
7.如权利要求6所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于更包括一相对低能力缓冲器与一反向器,该反向器配置于该N对相对高负载硅晶穿孔之一与该相对低能力缓冲器之间,该相对高能力缓冲器之传输速度大于该相对低能力缓冲器之传输速度,该相对高能力缓冲器之传输速度为χ倍该相对低能力缓冲器之传输速度。 7. as claimed in claim 6, wherein the difference between the dynamic measurement of the stack assembly having a plurality of layers of silicon and perforation timing control structure, characterized by further comprising a buffer with a relatively low capacity inverter, the inverter is disposed in The N between one perforated silicon relatively high load capacity and the relatively low buffer, the transmission speed is relatively high buffer capacity is greater than the transmission speed is relatively low capacity buffer of the transmission speed is relatively high capacity buffer of to χ times the transmission speed is relatively low capacity buffer of.
8.如权利要求6所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于该检测电路包括至少一反向器。 8. claim 6, wherein the difference between the dynamic measuring stack assembly having a plurality of layers of silicon and perforation timing control structure, characterized in that the detecting circuit comprises at least one inverter.
9.如权利要求6所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构, 其特征在于该感测电路包括一感测放大器、一比较器或一操作放大器。 9. claim 6, wherein it has a poor dynamic measurement of a plurality of layers of the stack components and perforated silicon timing control structure, wherein the sensing circuit includes a sense amplifier, a comparator or an operational amplifier.
10.如权利要求6所述之具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构,其特征在于该相对低负载硅晶穿孔之一与该(N-2)相对高负载硅晶穿孔耦接一时序闪控讯号,该对相对低负载硅晶穿孔与该(N-2)对相对高负载硅晶穿孔耦接一输入讯号。 10. claim 6, wherein it has a poor dynamic measurement of a plurality of layers of the stack components and perforated silicon timing control structure, wherein one of the relatively low load perforated silicon and the (N-2) relatively high load silicon Crystal perforation is coupled to a timing strobe signal, the relatively low load perforated silicon and the (N-2) to a relatively high load perforated silicon coupled to an input signal.
Description  translated from Chinese

三维芯片之差动感测及硅晶穿孔时序控制结构 Dynamic measurement of the difference between three-dimensional and perforated silicon chip timing control structure

【技术领域】 TECHNICAL FIELD

[0001] 本发明系关于一种三维堆栈芯片组件,特别系有关于一种三维芯片之差动感测及硅晶穿孔时序控制结构。 [0001] The present invention relates to a three-dimensional stack chip components, especially on poor tied with a three-dimensional dynamic measurement of and perforated silicon chip timing control structure.

【背景技术】 BACKGROUND OF THE INVENTION

[0002] 近来可携式电子设备,例如行动电话与非挥发性半导体记忆媒体(例如集成电路记忆卡),已缩小尺寸来设计或制造,并且新增的需求欲减少用于设备与媒体中的零件数目并缩小其大小。 [0002] Recently, portable electronic devices, such as mobile phones and the non-volatile semiconductor storage medium (e.g., IC card), has been reduced to the size of the design or manufacture, and the desire to reduce the need for new equipment and the media the number of parts and reduce its size. 因此,在半导体工业中,集成电路之封装技术已经进展至符合小型化与接着可靠性的需求。 Thus, in the semiconductor industry, integrated circuit packaging technology has progressed to meet the demand for miniaturization and reliability followed. 举例而言,小型化的需求而导致封装技术的加速发展,使其具有与一半导体芯片的相似尺寸。 For example, the demand for miniaturization and lead to accelerated development of packaging technology, making it similar size having a semiconductor chip. 再者,接着可靠性于封装技术上的重要性在于可以提升接着制程的效率, 以及于接着制程完成之后提高机械与电性的可靠度。 Moreover, then the importance of reliability in packaging technology that can improve the efficiency of the process followed, and then after the process is completed at improving the mechanical and electrical reliability. 因此,已有相当多的工作在于发展有效率地封装半导体芯片。 Therefore, there are quite a lot of work is to develop efficient packaged semiconductor chip. 符合上述需求之封装包括:具有约略等于半导体芯片的封装大小之芯片尺寸封装(CSP),有多重半导体芯片纳入一单一封装之多重芯片封装,以及多重封装体堆栈及结合于一单片构装之堆栈封装。 Compliance with these requirements of the package includes: a semiconductor chip having a roughly equal to the size of the package of the chip size package (CSP), has multiple semiconductor chips included in a single package of multi-chip package, as well as multi-package stack and combine in a monolithic structure mounted it Stack package.

[0003] 随着技术的发展,响应内存与其相关的所需储存容量的增加,而提出堆栈型态的半导体组件(多重芯片组件),其具有半导体集成电路芯片堆栈一起。 [0003] With the development of technology, the response associated with increased memory storage capacity required, and proposed a semiconductor component stack patterns (multi-chip module), which has a semiconductor integrated circuit chip stack together. 换言之,其系提供至少二个半导体集成电路组件堆栈所形成之堆栈型态半导体组件,每一个具有规格并包括一半导体集成电路芯片,其中每一个半导体集成电路组件包括一导体穿过其中,且半导体集成电路组件藉由导体电性连接,而上述规格值包括最上层或最下层半导体集成电路组件的大小是最大的或最小的。 In other words, the system provides a stack assembly formed of a semiconductor patterns for at least two of the semiconductor integrated circuit assembly stack, each having a size and includes a semiconductor integrated circuit chip, wherein each of the semiconductor integrated circuit assembly comprises a conductor therethrough, and a semiconductor IC package electrically connected by a conductor, and said specification values are uppermost or lowermost semiconductor integrated circuit package size is the largest or smallest. 因此,堆栈型态半导体组件具有复数个芯片堆栈于一垂直方向。 Therefore, the stack patterns semiconductor assembly having a plurality of chip stack in a vertical direction. 在堆栈型态半导体组件中,芯片系透过例如穿过芯片的插塞(Plugs)而电性连接在一起。 Stack patterns in semiconductor components, such as chip-based connected together through the chip through plug (Plugs) and electrically. 因此,选择适当的一个相同结构之堆栈内存芯片是一份重要的工作。 Therefore, select the appropriate one and the same structure of the stack memory chip is an important job. 若一个堆栈型态半导体组件完成制造,芯片可以个别地被操作测试,使得仅仅正常的芯片能够被挑选出并堆栈。 If a semiconductor component stack patterns complete fabrication, chips can be operated individually tested so that only the normal chip can be picked out and stack.

[0004] 一种提供垂直连接的技术称为硅晶穿孔(TSV),其已经成为三维堆栈组件的一个有前景的解决方案。 [0004] A method of providing a vertical connection technique called silicon perforation (TSV), which has become a three-dimensional stack assembly promising solutions. 上述技术中,垂直连接线系穿过晶圆而形成,而使堆栈芯片之间得以沟通。 The above technique, the vertical connection line is formed across the wafer, leaving to communication between the chip stack. 一个相关的论文可以参考标题为“利用硅晶穿孔技术之8千兆位三维DDR3动态随机存取内存”(IEEE,JOURNAL OF SOLID-STATECIRCUITS,VOL. 45, NO. 1,JANUARY 2010)。 A related paper can reference titled "Use of perforated silicon technology of three-dimensional 8-gigabit DDR3 dynamic random access memory" (IEEE, JOURNAL OF SOLID-STATECIRCUITS, VOL. 45, NO. 1, JANUARY 2010). 在此篇论文中,具有硅晶穿孔三维动态随机存取内存之提出系为了克服传统的模块方法的限制。 In Cipian paper having perforated silicon dimensional dynamic random access memory of the system proposed in order to overcome the limitations of traditional modular approach. 其亦揭露如何设计该结构与数据路径。 It also revealed how the design of the structure and the data path. 其也揭露包括三维技术之硅晶穿孔连接性检查与修复方法,以及功率噪声降低方法。 It also revealed the three-dimensional technology includes silicon perforation connectivity check and repair methods, as well as power noise reduction methods. 硅晶穿孔可以透过简单的方式于出厂之后形成,因此无需于正常的制程期间另加特别的制程整合。 Perforated silicon can be through a simple way to form after the factory, it is not necessary during the normal manufacturing process plus a special process integration. 芯片识别系通常地分配。 Chip identification system is usually allocated.

[0005] 在数据沟通系统中,典型地系利用一于第一频率下操作的传输组件以及一于第二频率下操作的独立接收组件。 [0005] In data communication systems, typically using a system to transport components operating at a first frequency and a receiving unit in the second frequency independent operation. 通常而言,传输组件与接收组件具有一频率速度差。 Typically, the transmission component and the receiving component has a clock speed difference. 此频率速度差导致接收者看到进来的数据比预期的更快或更慢,此处称为“时序偏移”。 This difference in clock speed led to the recipient to see the incoming data faster than expected or slower, referred to herein as "timing offset." 对于封包基础沟通系统而言,若封包期间的可能时序偏移最大量小于一符号期间,则频率速度差可以被忽略。 For packet based communication system, if possible timing offset is less than the maximum amount of packets during a symbol period, the clock speed difference can be ignored. 美国第7,003, 056专利揭露一种符号时序追踪及方法,其系利用时序追踪以较正由于传输频率与接收频率之频率差而来的时序偏移。 America's first 7,003, 056 patent discloses a method of tracking and symbol timing, which takes advantage of the timing tracking in a more positive due to the frequency of the transmission frequency and the reception frequency difference from the timing offset. 藉由时序追踪,三个连续取样的相关值可以利用接收讯号与回复符号而计算,然后计算其总和。 By timing tracking, continuous sampling of three related values can be used to receive the signal and restore symbols and calculations, and then calculate the sum. 此外,静态随机存储内存广泛地用于速度具有重要性的应用中,例如高速缓存典型地系置于最近于个人计算机中的处理器或中央处理器。 In addition, static random access memory widely used in the speed of the importance of having the application, for example, the cache line is typically placed recently in the personal computer processor or central processor. 然而,其内部电路的时序可能严重地影响了静态随机存储内存的速度与效率。 However, the timing of the internal circuit can seriously affect the speed and efficiency of static random access memory. 举例而言,位线充电期间包括相当可观的读/写周期,并且感测放大器使用对于静态随机存储内存的整体功率消耗贡献是显着的。 For example, during the bit line charge includes considerable read / write cycles, and the sense amplifier to the overall power consumption of static random access memory contribution is significant. 在早期的静态随机存储内存设计中,读/写周期系基于一外部产生的脉冲讯号。 In the early static random access memory design, the read / write cycle is based on an external pulse signal is generated. 另一习知技术揭露于美国第7,003, 056专利中,其包括自定时电路以降低一半导体内存的写入周期。 Another conventional techniques are disclosed in the first US 7,003, 056 patent, which includes self-timed circuitry to reduce the write cycle a semiconductor memory. 一虚拟内存晶胞具有相同时序需求以作为功能晶胞,且相关的写入逻辑加至内存组件之标准电路。 A virtual memory cell having the same timing requirements as a function of cell and associated programming logic applied to the standard components of the memory circuit. 虚拟写入晶胞接收相同控制讯号用以写入数据至该内存的功能晶胞,且当写入存取结束之后发出一完成讯号,致使写入周期终结。 Virtual write cell receiving the same control signal to write data to the memory cell function, and when the write access is completed after issuing a complete signal, resulting in the end of the write cycle. 此电路与方法允许写入周期时间降低至最小有效值,独立于读取周期时间。 This circuit allows the write cycle time is reduced to the minimum valid, independent of the read cycle time. 这潜在增加了内存组件的整体操作速度。 This potential increase in the overall operating speed of the memory components.

[0006] 本发明提供一种三维堆栈组件之差动感测及硅晶穿孔时序控制以改善负载问题, 如图一所示。 [0006] The present invention provides a three-dimensional stack difference in dynamic testing and assembly of perforated silicon timing control to improve load problem, as shown in Figure 1. 由负载问题所导致的时间延迟于较多芯片层是更糟的。 Problems caused by the load time delay in the chip layer is more worse. 因此,本发明提供一新颖的三维芯片感测及时序控制之方法以解决该问题。 Accordingly, the present invention provides a novel method of three-dimensional chip timing control of the sensing to resolve the issue.

【发明内容】 SUMMARY OF THE INVENTION

[0007] 本发明之一观点在于提供一种三维集成电路之差动感测及硅晶穿孔时序控制之方法与结构。 [0007] One of the present invention is to provide a point of difference in the dynamic test of a three-dimensional integrated circuit and method for control of perforated silicon timing and structure.

[0008] 三维集成电路之差动感测及硅晶穿孔时序控制结构,包括一相对高能力驱动器(缓冲器),一虚拟负载耦接相对高能力驱动器(缓冲器)以传递一时序闪控讯号,一检测电路耦接虚拟负载。 [0008] The difference between the dynamic measurement of three-dimensional integrated circuits and silicon perforation timing control structure, including a relatively high drive capability (buffer), a dummy load coupled to drive a relatively high capacity (buffer) to transmit a strobe signal timing, a detector circuit is coupled to the dummy load. 一差动讯号产生结构耦接一相对低能力驱动器(缓冲器)以产生一差动讯号。 A differential signal generating structure is coupled to a relatively low capacity drives (buffer) to produce a differential signal. 一感测电路耦接差动讯号产生结构。 A sensing circuit coupled to the differential signal generation structure. 当一主动讯号达至一触发点时,检测电路启动感测电路。 When an active signal up to a trigger point, the detection circuit starts sensing circuit.

[0009] 差动讯号产生结构包括一对高负载结构耦接一相对低能力驱动器,一反向器配置于该对相对高负载结构之一与相对低能力驱动器之间。 [0009] The differential signal generating structure comprises a pair of high-load structure coupled to a relatively low drive capacity, one inverter disposed between one of the pair of relatively high and relatively low capacity load structure drives. 该对相对高负载结构包括一对硅晶穿孔。 The relatively high load structure comprises a pair of perforated silicon. 虚拟负载包括一硅晶穿孔。 Virtual load comprises a perforated silicon.

[0010] 相对高能力驱动器之传输速度大于相对低能力驱动器之传输速度。 [0010] The relatively high capacity drive is faster than the ability to drive the relatively low transmission speeds. 在一实施例中,相对高能力驱动器之传输速度为X倍相对低能力驱动器之传输速度。 In one embodiment, a relatively high capacity drives X times the transmission speed is relatively low drive capability of the transmission speed. 感测电路包括一感测放大器、一比较器或一操作放大器。 Sensing circuit includes a sense amplifier, a comparator or an operational amplifier.

[0011] 在上述三维观点之架构下,一种具有复数层之堆栈组件之差动感测及硅晶穿孔时序控制结构,包括:一堆栈组件之第一芯片层,包括一检测电路与一相对高能力驱动器水平耦接检测电路。 [0011] In the framework of the three-dimensional view, one has poor dynamic measurement and perforated silicon timing control structure of a plurality of layers of the stack assembly comprising: a first layer of a stack assembly of chips, including a detection circuit and a relatively high coupled with the ability to drive level detection circuit. 一感测电路,藉由一水平导线耦接检测电路。 A sensing circuit, coupled by a horizontal wire detection circuit. 一第一差动讯号驱动器,于第一芯片层中水平耦接感测电路。 A first differential drive signal, the first layer of the chip level sensing circuit is coupled. 一堆栈组件之第N芯片层,包括一第N相对高能力驱动器与一第N差动讯号驱动器形成于第N芯片层之上,N为大于1的自然数,其中第N相对高能力驱动器系透过一垂直相对低负载硅晶穿孔与(N-2)相对高负载硅晶穿孔作为虚拟负载而垂直耦接第一相对高能力驱动器,相对低负载硅晶穿孔与(N-幻相对高负载硅晶穿孔系从第N芯片层至第一芯片层而穿过堆栈组件,其中相对低负载硅晶穿孔与(N-2)相对高负载硅晶穿孔形成于一共享结构中,其中第N差动讯号驱动器系透过一对相对低负载硅晶穿孔与(N-幻对相对高负载硅晶穿孔而垂直耦接第一差动讯号驱动器,该对相对低负载硅晶穿孔与该(N-幻相对高负载硅晶穿孔系从第N层至第一层而穿过堆栈组件,每一相对低负载硅晶穿孔系形成于第一与第二芯片层之间,每一相对高负载硅晶穿孔系形成于堆栈组件之任一相邻二芯片层之间,藉此当一主动讯号达至一触发点时,检测电路启动感测电路。 N-chip layer of a stack assembly of, comprising a N-relatively high capacity drive with an N-th differential signal driver is formed on the N-th chip layer, N is natural number greater than 1, wherein the N-relatively high capacity drive system through had a relatively low vertical load perforated silicon and (N-2) relatively high load perforated silicon as a virtual load is coupled to the first vertical relatively high capacity drive, relatively low load perforated silicon and (N- Magic relatively high load silicon crystal punch line from the first chip N chip layer to layer through the stack assembly in which the relatively low load perforated silicon and (N-2) relatively high load perforated silicon formed in a shared arrangement, the first of which N differential Signal line drive through a pair of opposed perforated silicon with low load (N- Magic to a relatively high load perforated silicon vertical coupled differential signal first drive, the relatively low load perforated silicon and the (N- Magic relatively high load system from perforated silicon N layer to the first layer through the stack components, each relatively low load silicon perforation line formed between the first and second chip layer, each of relatively high load perforated silicon Department of formation of any stack components in an adjacent layer between the two chips, whereby when an active signal up to a trigger point, the detection circuit starts sensing circuit.

【附图说明】 BRIEF DESCRIPTION

[0012] 上述组件,以及本发明其它特征与优点,藉由阅读实施方式之内容及其图式后,将更为明显: [0012] The above-mentioned components, as well as other features and advantages of the present invention, by way of reading the content and implementation of the drawings, it will be more obvious:

[0013] 图1显示根据习知技术之负载问图。 [0013] FIG. 1 shows the conventional technology based on load asked FIG.

[0014] 图2显示根据本发明之三维芯片之差动感测及硅晶穿孔时序控制结构之功能方块图。 [0014] Figure 2 shows a functional difference between the measured dynamic three-dimensional chip of the present invention and perforated silicon timing control structure of the block diagram.

[0015] 图3显示根据本发明之三维芯片之差动感测及硅晶穿孔时序控制结构之功能方块图。 [0015] Figure 3 shows a functional difference between the measured dynamic three-dimensional chip of the present invention and perforated silicon timing control structure of the block diagram.

[0016] 图4显示根据本发明之三维芯片之差动感测及硅晶穿孔时序控制结构之三维图标示意图。 [0016] FIG. 4 shows a schematic diagram of a three-dimensional icons difference measurement dynamic three-dimensional chip of the present invention and perforated silicon timing control structures.

[0017] 图中: [0017] in which:

[0018] 100、300驱动器或缓冲器 [0018] 100, 300 drive or buffer

[0019] 101第一高负载结构 [0019] 101 of the first high-load structure

[0020] 200、400 反向器 [0020] 200,400 reverser

[0021] 210a第二高负载结构(硅晶穿孔) [0021] 210a of the second high-load structure (perforated silicon)

[0022] 210b第三高负载结构(硅晶穿孔) [0022] 210b third highest load structure (perforated silicon)

[0023] 220、420 感测电路 [0023] The sensing circuit 220, 420

[0024] 310虚拟硅晶穿孔(虚拟负载) [0024] 310 virtual perforated silicon (dummy load)

[0025] 315检测电路 [0025] detection circuit 315

[0026] 405a、405b相对低位准驱动器(缓冲器) [0026] 405a, 405b relatively low quasi-drive (buffer)

[0027] 410a、410b 硅晶穿孔 [0027] 410a, 410b perforated silicon

[0028] 300L1相对高能力驱动器 [0028] 300L1 relatively high capacity drives

[0029] Cl 导线 [0029] Cl wire

[0030] 300LN第N相对高能力驱动器 [0030] 300LN first N relatively high capacity drives

[0031] 422L1第一差动讯号驱动器 [0031] 422L1 first differential signal drive

[0032] 422LN第N差动讯号驱动器 [0032] 422LN N-differential signal drive

【具体实施方式】 [DETAILED DESCRIPTION]

[0033] 本发明将配合其较佳实施例与随附之图示详述于下。 [0033] The present invention with its preferred embodiment and the accompanying illustrated embodiment described in detail below. 应可理解者为本发明中所有之较佳实施例仅为例示之用,并非用以限制。 It should be appreciated by all of the present invention illustrating the preferred embodiments only and is not intended to limit. 因此除文中之较佳实施例外,本发明亦可广泛地应用在其它实施例中。 Therefore, unless an exception in the preferred embodiment, the present invention can also be widely used in other embodiments. 且本发明并不受限于任何实施例,应以随附之权利要求及其同等领域而定。 And the present invention is not limited to any embodiment, should the accompanying claims and their equivalents in the field may be.

[0034] 本发明系有关于三维芯片之差动感测及硅晶穿孔时序控制结构,其可以引进于嵌入式挥发性或非挥发性内存。 [0034] The present invention is about the difference between dynamic measurement and perforated silicon chip timing control of the three-dimensional structure, which can be introduced in the embedded volatile or non-volatile memory. 在一较佳实施例中,如图2所示,本发明揭露一差动感测结构,其包括一驱动器或缓冲器100,耦接一第一高负载结构101。 In a preferred embodiment, shown in Figure 2, the present invention discloses a poor dynamic test structure, which includes a drive or buffer 100, is coupled to a first high-load structure 101. 一讯号输入耦接驱动器或缓冲器100之另一端,一讯号输出电性连接第一高负载结构,其可透过硅晶穿孔101 而形成。 A signal input coupled to the drive or the other end of the buffer 100, a signal output electrically connected to the first high-load structure through perforated silicon 101 may be formed. 本结构更包括一第二高负载结构(硅晶穿孔)210a与第三高负载结构(硅晶穿孔)210b,上述第二硅晶穿孔210a与第三硅晶穿孔210b 二者依设计考虑可以为平行配置结构。 The structure further includes a second high-load structure (perforated silicon) 210a and the third highest load structure (perforated silicon) 210b, 210a and the second and third silicon perforation 210b two perforated silicon design considerations may be held liable under arranged in parallel structure. 亦可以利用其它结构配置。 You can also use other structural arrangement. 讯号输入耦接第二硅晶穿孔210a,而一反向器200配置于讯号输入与第三硅晶穿孔210b之间。 Signal input coupled to the second silicon perforations 210a, and an inverter 200 is disposed on the input signal between the third silicon perforation 210b. 接下来,一感测电路220分别耦接第二硅晶穿孔210a 与第三硅晶穿孔210b。 Next, a sensing circuit 220 are coupled to a second perforated silicon 210a and third silicon perforation 210b. 讯号输出耦接感测电路220之另一端。 Signal output coupled to the other end of the sense of the sensing circuit 220. 图2之差动感测结构中亦分别显示VDD时序图。 The difference between the measured dynamic structure of Figure 2 also are shown in the timing chart VDD. 对于第一硅晶穿孔101而言,其触发点(trigger point)在于VDD的一半,若触发点水平延伸以达到VDD时序图的A点,则读出时间即为时间轴与从A点垂直延伸线之交叉点。 For the first perforated silicon 101, its trigger points (trigger point) in that half VDD, if the trigger point horizontally extending to achieve timing chart VDD A point, the read-out time is the time axis and extending perpendicular from point A line of intersection. 类似地,对于第二硅晶穿孔210a与第三硅晶穿孔210b而言,其感测界限较高于触发点,亦即高于二分之一VDD。 Similarly, for the second perforated silicon 210a and 210b third silicon perforation, its sensing limit to the trigger point higher, that is higher than the half VDD. 因此,读出将于VDD时序线之上,其将于讯号线与VDD 时序线之间。 Thus, the read timing line will be above VDD, it will signal line between the timing line and VDD.

[0035] 参考图3,其显示本发明之一较佳实施例。 [0035] Referring to Figure 3, which shows one preferred embodiment of the present invention. 其显示不同感测之硅晶穿孔时序控制, 本结构包括一相对高位准驱动器或缓冲器300耦接一具有高负载之虚拟硅晶穿孔(虚拟负载)310。 It shows the different sense of perforated silicon measuring timing control, this structure includes a relatively high quasi-drive or a buffer 300 is coupled with a virtual high load of perforated silicon (dummy load) 310. 一时序闪控讯号(timing strobe signal)耦接驱动器或缓冲器300之另一端,一检测电路315电性连接虚拟硅晶穿孔(虚拟负载)310。 A timing strobe signal (timing strobe signal) is coupled to the drive or the other end of the buffer 300, a detection circuit 315 is electrically connected to the virtual perforated silicon (dummy load) 310. 此差动讯号结构包括一对高负载结构,在一例子中,此对高负载结构可以由一对硅晶穿孔410a与硅晶穿孔410b所形成,该对硅晶穿孔410a与硅晶穿孔410b分别透过相对低位准驱动器(缓冲器)40与40而耦接讯号输入。 This differential signal structure includes a pair of high-load structure, in a case, this high-load structure can 410a and 410b perforated silicon formed by a pair of perforated silicon, the silicon crystal punch 410a and 410b respectively perforated silicon Associate drive through relatively low (buffer) 40 and 40 be coupled input signals. 值得注意的是,一反向器400配置于讯号输入与相对低位准驱动器(缓冲器)40之间。 It is worth noting that an inverter 400 is configured to signal input with a relatively low drive between quasi 40 (buffer). 接下来,一感测电路420分别耦接该对高负载结构二者。 Next, a sensing circuit 420 are coupled to the high-load structure for both. 讯号输出耦接感测电路420之另一端。 Signal output coupled to the other end of the sense of the sensing circuit 420. 前述检测电路315耦接感测电路420。 The detecting circuit 315 is coupled to the sensing circuit 420. 较佳的是,时序闪控讯号几乎与讯号输入相同。 Preferably, the timing of the strobe signal input signal is almost the same. 在一较佳实施例中,相对高位准驱动器(缓冲器)300具有数倍效能于相对低位准驱动器(缓冲器)405a或40。 In a preferred embodiment, the relatively high level of quasi-drive (buffer) 300 has a relatively low multiple of efficacy in quasi-drive (buffer) 405a or 40.

[0036] 请参考图3,其接着图示硅晶穿孔差动感测之时序控制。 [0036] Referring to Figure 3, which is then shown perforated silicon dynamic measurement of the difference between the timing control. 起始步骤在于输入时序闪控讯号至相对高位准驱动器(缓冲器)。 The initial step is to enter strobe timing signal to the relatively high quasi-drive (buffer). 真实讯号输入至相对低位准驱动器(缓冲器)405a 与40恥。 Real signal input to a relatively low quasi-drive (buffer) 405a and 40 shame. 经过反向器400之讯号将从初始输入讯号反向并延迟,反向讯号波形可以从图3 之右上部分看出来。 After the signal from the inverter 400 of the initial input signal reverse and delay and reverse the signal waveform can be seen from the upper right portion of FIG. 因此,经由反向器400而到达高负载结构410b之讯号将被反向。 Thus, via inverter 400 and reaches the high load structure of signal 410b will be reversed. 相反地,没有经过反向器400而到达另一高负载结构410a之讯号仍维持相同。 Conversely, without the inverter 400 and 410a to the other structure of the high load signal remains the same. 此时感测电路420系正常关闭。 At this sensing system circuit 420 normally closed. 由于负载是重的,因此由差动讯号传递。 Because the load is heavy, so the signal transmitted by the differential. 当差动讯号之差大于IOOmV(0.1 伏特),接下来开启感测电路420,因此决定数字状态为1或0。 When the difference between the differential signal is greater than IOOmV (0.1 volts), then open the sensing circuit 420, the state decided to digital 1 or 0.

[0037] IOOmV (0. 1伏特)的差系藉由电路决定,其具有虚拟负载310耦接检测电路315。 [0037] IOOmV (0. 1 volt) circuit determines the difference between the system by having a dummy load 310 coupled to the detection circuit 315. VDD时序图可以参考第二与图3之图示。 VDD can refer to the timing diagram shown in Figure 3 of a second. 该图示意谓着讯号穿过虚拟负载310。 This figure means that the signal passes through the dummy load 310. 该对高负载结构410a与410b于VDD时序图中的输出显示于图2与图3之右边。 The output of the high-load structure 410a and 410b in VDD timing diagram is shown in the right side of Figure 2 and Figure 3. 一虚拟讯号由虚拟负载310所复制以传递一众所周知的主动讯号,一数(χ)倍能力的驱动器300引进至虚拟负载310。 A virtual signal from the dummy load 310 to deliver a well-known copy of the active signals, a number (χ) times the capacity of the drive to introduce 300 to 310 virtual load. 假定VDD为1.8伏特,则触发点为VDD的一半,即0.9伏特。 VDD assumed as 1.8 volts, the trigger point for the half VDD, that is 0.9 volts. 结果,当差动讯号之差大于IOOmV(0. 1伏特),虚拟负载的讯号达至触发点,因此χ的值为9。 As a result, when the difference is greater than the differential signal IOOmV (0. 1 volt), signal dummy load up to the trigger point, and therefore χ value of 9. 其意谓着虚拟负载310的传输速度比该对差动讯号结构更大。 Which means that the transmission speed of 310 virtual load greater than that of the differential signal structure. 类似地,若VDD为1伏特,则χ值为5。 Similarly, if the VDD is 1 volt, the χ value of 5.

[0038] 当主动讯号,于图三之步骤二中,达至触发点,检测电路315应尽可能早地打开感测电路420。 [0038] When the active signal, in step Figure III bis, up to the trigger point, the detection circuit 315 should be opened as soon as possible sensing circuit 420. 在一较佳实施例中,检测电路315系藉由至少一反向器形成,以检测产生突波, In a preferred embodiment, the detection circuit 315 lines is formed by at least one inverter to produce surge detection,

7于图三之步骤三中。 7 steps in Figure III of III. 最重要之一者系反向器需符应此感测时序。 One of the most important symbols required by the Department of the inverter should this sensing timing. 感测电路420可以为一感测放大器或一比较器或一操作放大器。 Sensing circuit 420 may be a sense amplifier or a comparator or an operational amplifier. 最后,讯号从感测电路输出,于图三之步骤四中。 Finally, the output signal from the sensing circuit, step three is to the four in FIG. 负载问题可以容易地藉由硅晶穿孔时序控制与差动感测结构而得到克服。 Load problem can easily be perforated silicon timing control and measure the difference between the dynamic structures be overcome.

[0039] 图4显示本发明之三维结构,三维堆栈组件包括复数个堆栈芯片层,其包括一个别芯片(未图标)位于每一芯片层。 [0039] Figure 4 shows a three-dimensional structure of the present invention, the stack assembly includes a plurality of three-dimensional chip stack layer, comprising one another chip (not shown) located at each layer of the chip. 三维堆栈组件之第一芯片层(第一层)包括一检测电路315位于一预定区域之内,一相对高能力驱动器300L1平行耦接检测电路315。 A first layer of a three-dimensional chip stack of components (a first layer) comprising a detector circuit 315 is located within a predetermined area, a relatively high capacity drives 300L1 detection circuit 315 is coupled in parallel. 一感测电路420配置于第一芯片层之一预定区域,并藉由一水平导线Cl耦接检测电路315。 A sensing circuit 420 is disposed in a predetermined area of one of the first chip layer, and by a horizontal wire detection circuit 315 is coupled Cl. 一差动讯号驱动器422L1水平耦接感测电路420。 422L1 level of a differential signal drive coupled to the sensing circuit 420. 堆栈组件之其它芯片层之结构,除了没有检测电路315与感测电路420之外,与第一芯片层类似。 Other structural components of the chip stack layer, in addition to not detecting circuit 315 and outside of the sensing circuit 420, similar to the first chip layer. 三维堆栈组件之第N芯片层(第N 层)也包括一第N相对高能力驱动器300LN位于第N层芯片层之指定区域上,一第N差动讯号驱动器422LN亦配置于第N芯片层之上;N为大于1的自然数。 N-chip layer (layer N) three-dimensional stack assembly of including an N-relatively high capacity drive 300LN located on designated areas first N-layer chip layer, an N-th differential signal drive 422LN also disposed in the N-th chip layer on; N natural number greater than 1. 第N相对高能力驱动器300LN系透过一垂直相对低负载硅晶穿孔与(N-幻相对高负载硅晶穿孔而垂直耦接第一相对高能力驱动器300L1,其由图4之TSVx(N-2)所示,所有的相对低负载硅晶穿孔与(N-2) 相对高负载硅晶穿孔系从上至底而穿过堆栈组件,其中相对低负载硅晶穿孔与(N-2)相对高负载硅晶穿孔形成于一共享结构中。类似地,第N差动讯号驱动器422LN系透过一对相对低负载硅晶穿孔与(N-幻对相对高负载硅晶穿孔而垂直耦接第一差动讯号驱动器422L1, 所有的相对低负载硅晶穿孔与(N-2)对相对高负载硅晶穿孔系从第η层至第一层而穿过堆栈组件。值得注意的是,每一相对低负载硅晶穿孔系形成于第一与第二芯片层之间。(Ν-2) 相对高负载硅晶穿孔系形成于,除了第一与第二芯片层之间之外,堆栈组件之任一相邻二芯片层之间。其机制与操作方法已经说明于第三与图4中。因此,省略其的多余的叙述。 The first N 300LN relatively high capacity drive system through a relatively low vertical load perforated silicon and (N- Magic relatively high load perforated silicon vertical coupled first relatively high capacity drives 300L1, which consists of TSVx 4 (N- 2), all of relatively low load perforated silicon and (N-2) relatively high load perforated silicon system from top to bottom and across the stack assembly in which the relatively low load perforated silicon and (N-2) relative High load perforated silicon formed in a shared structure. Similarly, the N differential signal line drive 422LN through a pair of opposed perforated silicon with low load (N- Magic to a relatively high load perforated silicon and vertical coupling section a differential signal drive 422L1, all relatively low load perforated silicon and (N-2) to a relatively high load perforated silicon system from η layer to the first layer through the stack components. It is worth noting that each relatively low load perforated silicon system formed between the first and second chip layer. (Ν-2) relatively high load perforated silicon were formed in addition to the chip between the first and second layers of the stack assembly chip between any two adjacent layers. The mechanism and method of operation has been described in the third and Figure 4. Thus, the redundant description thereof is omitted.

[0040] 一实施例系为本发明之一实例或范例。 [0040] one embodiment of the present invention system instance or example. 叙述于说明书中之「一实施例」、「一些实施例」或「其它实施例」系指所描述联结于此实施例中之一特殊特征、结构或特性被包含最少一些实施例中,但并非对所有实施例而言皆为必需。 Described in the specification, the "one embodiment," "some embodiments" or "other embodiments" means the embodiments described herein, one particular coupling feature, structure, or characteristic is included least some embodiments, but not All embodiments are all essential terms. 「一实施例」或「一些实施例」等不同叙述系指并非必须提及这一些实施例。 "One embodiment" or "some embodiments" means a different narrative is not to be mentioned here are some examples. 值得注意的是,于前文叙述关于本发明之特定实施例中,不同特征有时可集合于一单一实施例、图式或叙述中系用以简化说明并助于对本发明一或多种不同方面之理解。 It is worth noting that, in the foregoing account of the specific embodiment of the present invention, various features may be set to a single embodiment, line drawings or narrative to simplify and help illustrate different aspects of one or more of the present invention understand. 然而,此揭露方法不应被用以反映所请求之发明范畴,因而将所述范例中之特征加入每一权利要求中。 However, this method should not be used to expose the scope of the invention to reflect the request, so that the characteristics of the sample added to each of the claims. 反之,于下述之权利要求所反映本发明之观点会少于上述所揭露之单一实施例中的所有特征。 On the contrary, as reflected in the following aspects of the present invention of the claim would be less than a single embodiment disclosed above of all the features. 因此,权利要求系涵盖所述之实施例,且每一权利要求本身皆可视为本发明之一独立实施例。 Therefore, the embodiment of the system to cover claims and each claim the right itself can be considered as one embodiment of the present invention is independent.

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Classifications
International ClassificationH03K17/28
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