CN102446881A - Universal packaging substrate and packaging method thereof - Google Patents
Universal packaging substrate and packaging method thereof Download PDFInfo
- Publication number
- CN102446881A CN102446881A CN2011104125252A CN201110412525A CN102446881A CN 102446881 A CN102446881 A CN 102446881A CN 2011104125252 A CN2011104125252 A CN 2011104125252A CN 201110412525 A CN201110412525 A CN 201110412525A CN 102446881 A CN102446881 A CN 102446881A
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- CN
- China
- Prior art keywords
- substrate
- wiring
- routing
- packaging substrate
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention aims at a defect that wiring patterns of a substrate in the prior art cannot be performed with later regulation and modification after finishing manufacturing to affect an application range of the substrate, and provides an universal packaging substrate which is capable of overcoming the defect. The universal packaging substrate provided by the invention comprises a first substrate, a plurality of welding plates positioned on the lower surface of the first substrate, and a plurality of wiring units positioned on the upper surface of the first substrate; the wiring units are electrically connected with the welding plates with through holes respectively; and each wiring unit comprises a plurality of wiring patterns; and the electrical connection relationship among the wiring patterns is changed according to the needed electrical connection relationship.
Description
Technical field
Designing semiconductor encapsulation field of the present invention relates in particular to a kind of universal packaging substrate and method for packing thereof.
Background technology
Present semiconductor packaging mainly adopts High Density Packaging Technology such as welded ball array, wafer-level package.The customization substrate to certain chip that is adopted in these technology perhaps all processes at one time to the general substrate of some money chips; Be that wiring figure on the substrate can not carry out the adjustment or the modification in later stage after preparation is accomplished; And this can make the range of application of substrate receive the restriction that soldering finger part distributes on the substrate, has also reduced the application flexibility of universal packaging substrate.
Summary of the invention
Thereby the present invention is directed to wiring figure on the substrate of the prior art can not carry out the later stage adjustment and revise the range of application that influences substrate after completing defective, a kind of universal packaging substrate that can overcome above-mentioned defective is provided.
The present invention provides a kind of universal packaging substrate; This universal packaging substrate comprises first substrate, be positioned at a plurality of pads on the lower surface of said first substrate and be positioned at a plurality of routing cells on the upper surface of said first substrate; Said a plurality of routing cell and said a plurality of pad are electrically connected through through hole respectively; Each said routing cell all comprises a plurality of wiring figures, and the electrical connection between said a plurality of wiring figures can be changed according to required electrical connection.
The present invention also provides a kind of method that adopts above-mentioned universal packaging substrate that chip is encapsulated, and this method comprises:
With at least one chip attach to the upper surface of said first substrate;
Mode through routing is electrically connected to said at least one bonding pads on the corresponding said wiring figure;
Revise the electrical connection between the said wiring figure according to required electrical connection;
Said at least one chip is carried out plastic packaging;
On the lower surface of said first substrate, plant ball drawing with the signal of telecommunication of realizing said at least one chip.
Owing to all comprise a plurality of wiring figures in each routing cell according to universal packaging substrate of the present invention; And the electrical connection between said a plurality of wiring figure can be changed according to required electrical connection; So universal packaging substrate according to the present invention can also carry out the adjustment or the modification in later stage after having made wiring figure; Thereby make the constraint that does not receive the distribution of soldering finger part on the substrate according to the range of application of universal packaging substrate of the present invention, increased application flexibility according to universal packaging substrate of the present invention and method for packing thereof.
Description of drawings
Fig. 1 is the vertical view according to universal packaging substrate of the present invention;
Fig. 2 is the vertical view according to the routing cell in the universal packaging substrate of the present invention;
Fig. 3 is another vertical view according to the routing cell in the universal packaging substrate of the present invention;
Fig. 4 is the another vertical view according to the routing cell in the universal packaging substrate of the present invention;
Fig. 5 adopts the sectional view that carries out the welded ball array encapsulation according to universal packaging substrate of the present invention;
Fig. 6 adopts the sectional view that carries out the multi-chip module encapsulation according to universal packaging substrate of the present invention;
Fig. 7 is the flow chart according to method for packing of the present invention.
Embodiment
Describe in detail according to universal packaging substrate of the present invention and method for packing thereof below in conjunction with accompanying drawing.
Fig. 1 shows the vertical view according to universal packaging substrate of the present invention.Wherein, Universal packaging substrate according to the present invention comprises first substrate, be positioned at a plurality of pads on said first the lower surface and be positioned at a plurality of routing cells 10 on the upper surface of said first substrate; Said a plurality of routing cell 10 is electrically connected through through hole respectively with said a plurality of pads; Each said routing cell 10 all comprises a plurality of wiring figures 101, and the electrical connection between said a plurality of wiring figures 101 can be changed according to required electrical connection.
Fig. 2 shows the zoomed-in view of routing cell 10; Wherein, Routing cell 10 comprises a plurality of wiring figures 101, and through line 102 interconnection, 10 of routing cells are connected to the pad on the lower surface that is positioned at universal packaging substrate through through hole 103 between each wiring figure 101.In routing cell shown in Figure 2; Part wiring figure 101 is interconnected; Other a part of wiring figure 101 then is free of attachment to other wiring figures 101; Like this; Will be according to universal packaging substrate of the present invention and the Chip Packaging that designs together the time, can through etch away processing during according to universal packaging substrate of the present invention formed line 102 and/or through routing, scolding tin apply, mode such as silver slurry printing links together corresponding wiring line figure 101 to carry out wiring operations again according to the chip that is designed, and promptly carries out later stage adjustment and modification to accomplish final encapsulation.
Certainly; The included routing cell 10 of universal packaging substrate according to the present invention also can be as shown in Figure 3; Be that each wiring figure 101 in each routing cell 10 in the universal packaging substrate all opens circuit each other, as shown in Figure 3, routing cell 10 includes only wiring figure 101 and through hole 103.Like this; In the time will encapsulating according to universal packaging substrate of the present invention and the chip that designs; Can link together through the wiring figure 101 that modes such as routing, scolding tin coating, the printing of silver slurry will connect; Thereby realize wiring again, promptly carry out later stage modify accomplishing final encapsulation, thereby increased application flexibility and range of application according to universal packaging substrate of the present invention.
The included routing cell 10 of universal packaging substrate according to the present invention also can be as shown in Figure 4, and promptly all wiring figures 101 in each routing cell 10 in the universal packaging substrate all are electrically connected through line 102 each other.Like this, in the time will encapsulating, can remove part line 102 carrying out later stage modify and adjustment through methods such as etchings, thereby accomplish final encapsulation according to universal packaging substrate of the present invention and the chip that designs.
Certainly; Those skilled in the art should be understood that; The combination in any that can comprise Fig. 2, Fig. 3 and routing cell 10 shown in Figure 4 according to universal packaging substrate of the present invention; For example, the included routing cell 10 of universal packaging substrate according to the present invention can be following situation: the wiring figure 101 in the part routing cell 10 all opens circuit (as shown in Figure 3) each other, the wiring figure 101 in another part routing cell 10 all is electrically connected to each other (as shown in Figure 4) and remaining routing cell 10 in wiring figure 101 part be electrically connected to each other (as shown in Figure 2) all.In addition, the position and the quantity of the shape of the wiring figure 101 in each routing cell 10, the shape of line 102 and through hole 103 are not limited to situation shown in the drawings, and any other form all is feasible.
Because according to the routing cell 10 that distributing in array entirely on the upper surface of universal packaging substrate of the present invention; So not only can realize the encapsulation (shown in the sectional view of Fig. 5) of single chip according to universal packaging substrate of the present invention, can also or pile up a plurality of chips and realize multi-chip module (MCM) encapsulation (shown in the sectional view of Fig. 6) through tiling on a substrate through selecting the suitable soldering finger part of periphery to carry out rewiring.Wherein, the packed chip of indicating of the label 20 among Fig. 5, label 104 expression routings connect, and label 103 expressions are according to universal packaging substrate of the present invention, and label 106 expression soldered balls are identical among the meaning of label and Fig. 5 among Fig. 6.
Describe the flow chart according to method for packing of the present invention below in conjunction with Fig. 7, this method for packing adopts according to universal packaging substrate of the present invention and realizes.This method comprises:
S71, with at least one chip attach to the upper surface of first substrate of said universal packaging substrate.
Wherein, said at least one chip can paste on the upper surface of first substrate through silver slurry or other binding agents.And, when number of chips greater than 1 the time, these a plurality of chips can be stacked together, also can all paste on the upper surface of first substrate (that is, not having range upon range of situation to occur) according to actual conditions.
S72, the mode through routing are electrically connected to said at least one bonding pads on the corresponding said wiring figure 101.
Wherein, Said at least one bonding pads can be through beating gold thread, beat copper cash and one or more modes of beating in the aluminum steel are connected on the corresponding wiring line figure 101 of said universal packaging substrate, and the mode of routing can be forward routing and/or reverse routing.
S73, revise the electrical connection between the said wiring figure 101 according to required electrical connection;
S74, said at least one chip is carried out plastic packaging;
S75, on the lower surface of said first substrate, plant ball drawing with the signal of telecommunication of realizing said at least one chip.
Below only combine preferred implementation of the present invention that the present invention is described in detail, but one skilled in the art will appreciate that under the situation that does not deviate from spirit and scope of the invention, can carry out various distortion and modification the present invention.
Claims (9)
1. universal packaging substrate; This universal packaging substrate comprises first substrate, be positioned at a plurality of pads on the lower surface of said first substrate and be positioned at a plurality of routing cells on the upper surface of said first substrate; Said a plurality of routing cell and said a plurality of pad are electrically connected through through hole respectively; Each said routing cell all comprises a plurality of wiring figures, and the electrical connection between said a plurality of wiring figures can be changed according to required electrical connection.
2. universal packaging substrate according to claim 1, wherein, the said a plurality of wiring figures in each said routing cell all open circuit each other.
3. universal packaging substrate according to claim 1, wherein, the said a plurality of wiring figures in each said routing cell all are electrically connected to each other.
4. universal packaging substrate according to claim 1 wherein, has only the part wiring figure to be electrically connected to each other in the said a plurality of wiring figures in each said routing cell.
5. universal packaging substrate according to claim 1; Wherein, the said a plurality of wiring figures in the said routing cell of part all open circuit each other, the said a plurality of wiring figures in the said routing cell of another part all are electrically connected to each other and remaining said routing cell in said a plurality of wiring figures in have only the part wiring figure to be electrically connected to each other.
6. one kind is adopted the method that the described universal packaging substrate of each claim encapsulates chip in the claim 1 to 5, and this method comprises:
With at least one chip attach to the upper surface of said first substrate;
Mode through routing is electrically connected to said at least one bonding pads on the corresponding said wiring figure;
Revise the electrical connection between the said wiring figure according to required electrical connection;
Said at least one chip is carried out plastic packaging;
On the lower surface of said first substrate, plant ball drawing with the signal of telecommunication of realizing said at least one chip.
7. method according to claim 6, wherein, said at least one chip pastes on the upper surface of said first substrate through the silver slurry.
8. method according to claim 6, wherein, said at least one bonding pads is electrically connected on the corresponding said wiring figure through the mode of beating gold thread and/or beat copper cash and/or break aluminum steel.
9. method according to claim 6, wherein, said at least one bonding pads is electrically connected on the corresponding said wiring figure through the mode of forward routing and/or reverse routing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110412525.2A CN102446881B (en) | 2011-12-12 | 2011-12-12 | Universal packaging substrate and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110412525.2A CN102446881B (en) | 2011-12-12 | 2011-12-12 | Universal packaging substrate and packaging method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102446881A true CN102446881A (en) | 2012-05-09 |
| CN102446881B CN102446881B (en) | 2014-02-26 |
Family
ID=46009247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110412525.2A Active CN102446881B (en) | 2011-12-12 | 2011-12-12 | Universal packaging substrate and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102446881B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050006734A1 (en) * | 2003-07-07 | 2005-01-13 | Fuaida Harun | Bonding pad for a packaged integrated circuit |
| CN101145548A (en) * | 2006-09-12 | 2008-03-19 | 日月光半导体制造股份有限公司 | Universal packaging substrate and its application device |
| US20090146299A1 (en) * | 2007-12-10 | 2009-06-11 | Shih-Chi Chen | Semiconductor package and method thereof |
| US7846775B1 (en) * | 2005-05-23 | 2010-12-07 | National Semiconductor Corporation | Universal lead frame for micro-array packages |
-
2011
- 2011-12-12 CN CN201110412525.2A patent/CN102446881B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050006734A1 (en) * | 2003-07-07 | 2005-01-13 | Fuaida Harun | Bonding pad for a packaged integrated circuit |
| US7846775B1 (en) * | 2005-05-23 | 2010-12-07 | National Semiconductor Corporation | Universal lead frame for micro-array packages |
| CN101145548A (en) * | 2006-09-12 | 2008-03-19 | 日月光半导体制造股份有限公司 | Universal packaging substrate and its application device |
| US20090146299A1 (en) * | 2007-12-10 | 2009-06-11 | Shih-Chi Chen | Semiconductor package and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102446881B (en) | 2014-02-26 |
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| C14 | Grant of patent or utility model | ||
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