CN102394648B - Current-mode digital to analog converter - Google Patents

Abstract

The invention discloses a current-mode digital to analog converter which comprises an encoder, a plurality of current source and switch modules, and a complementary current branch corresponding to at least one current source and switch module. Each current source and switch module comprises a current source unit, a first output end and a second output end, a first switch unit connected between the current source unit and the first output end and controlled by a first control signal output by the encoder, and a second switch unit connected between the current source unit and the second output end and controlled by a second control signal which is output by the encoder and in the opposite phase with the first control signal. The complementary current branch comprises a branch current source unit, a branch first switch unit connected between the branch current source unit and the first output end and controlled by the second control signal, and a branch second switch unit connected between the branch current source unit and the second output end and controlled by the first control signal. The output impedance of the digital to analog converter provided by the invention has smaller relativity with signals.

Description

Current mode digital-to-analog converter

Technical field

The present invention relates to integrated circuit (IC) design technical field, relate in particular to a kind of current mode digital-to-analog converter.

Background technology

High dynamic range broadband digital to analog converter (DAC) has accounted for very important position in Modern Communication System.The DAC of current drives framework compares with the DAC of other framework that to have speed faster, the less and stronger feature of carrying load ability of power consumption.Due to problems such as the sequence problem in circuit, burr, Current-source matching error and output impedance are limited, traditional current drives DAC does not solve the problem of the linearity remarkable decline because DAC output impedance declines of DAC when frequency raises.The linearity of DAC uses Spurious Free Dynamic Range (SFDR) to describe conventionally, and the Bi， unit that SFDR is defined as the energy of the harmonic wave of signal energy and energy maximum in output represents with dB.

Accompanying drawing 1 is the block diagram of a typical current mode DAC, and digital input signals produces the control signal of controlling current source and switch arrays by decoder, and these control signals are controlled the break-make of each current source and switch module, and it is output as the two-way electric current of difference.

Accompanying drawing 3 (b) is depicted as a switching current source unit in typical DAC, and from output toward current source with switch, the output impedance of DAC is in parallel and is formed by the output impedance of several current sources.While inputting due to difference, the conducting closed condition of switch is different, and this causes the current source of conducting of output parallel connection also not identical with the number of switch module, so the output impedance of DAC is to input dependence.This dependence has had a strong impact on the lifting of SFDR under high frequency.

From a kind of typical situation, suppose in the DAC of a thermometer decoded device always total N road of switch and current source, the size of current of each road current source is I ₀, R _lfor the constant ohmic load of DAC, Z ₀for the output impedance of circuit branch, suppose that the signal of DAC input is sinusoidal signal sin (ω t), DAC positive output end voltage is so:

$V_{\mathrm{out}}{\left(\mathrm{\&omega;t}\right)}^{+}=\left(\frac{1+\sin \left(\mathrm{\&omega;t}\right)}{2}{\mathrm{NI}}_0\right)\&times;\left(R_L\right|\left|\frac{Z_0}{\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="HDA0000098862250000012.png"\; state="\{\{state\}\}">N</figure-callout>}\frac{1+\sin \left(\mathrm{\&omega;t}\right)}{2}}\right)\&CenterDot;$

Thereby can derive difference output:

$V_{\mathrm{out}}\left(\mathrm{\&omega;t}\right)=\frac{{{4\mathrm{IZ}}_0}^2}{{\mathrm{NR}}_L}\frac{\sin \left(\mathrm{\&omega;t}\right)}{{(2Z_0/N/R_L+1)}^2-\sin {\left(\mathrm{\&omega;t}\right)}^2}$

This function is done to Fourier expansion:

$V_{\mathrm{out}}\left(\mathrm{\&omega;t}\right)=\frac{4{\mathrm{IZ}}_0^2}{{\mathrm{NR}}_L}\&times;(\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA0000098862250000012.png"\; state="\{\{state\}\}">B</figure-callout>}1+\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">B</figure-callout>}2+\&CenterDot;\&CenterDot;\&CenterDot;),$

Wherein:

B1＝(64A ³+48A ²+40A+35)sin(ωt)，

B2＝-(16A ²+20A+21)sin(3ωt)，

A＝(2Z ₀/N/R _L+1) ²。

Ignore the 6th and later high-order small component in expansion, can derive SFDR and be:

$\mathrm{SFDR}=20\lg \left(\frac{64A^3+48A^2+40A+35}{16A^2+20A+21}\right)\left(\mathrm{dB}\right).$

This formula is still set up for the DAC (as segment encoding DAC) of non-thermometer coding.The attached functional relation that Figure 2 shows that the 14 digit currents driving SFDR of DAC and the output impedance of switching current source unit.The 12b DAC that is 50ohm for a differential load, if require SFDR > 70dB, the output impedance of least significant bit (LSB) requires big or small 2.9M ohm so.This means that Gao Liuwei adopts thermometer coding to a 6+6 segment encoding DAC, corresponding each current branch of this thermometer coding can only allow the parasitic capacitance of 18fF when 200MHz output frequency; Or the parasitic capacitance that can only have 7fF when 500MHz output frequency.This condition almost can not meet under current semiconductor technology.

Be more than theoretical derivation, actually because switch output impedance when closing not is infinity, thereby the result of bringing so also can make SFDR distinguish to some extent.Further, because interconnection line in side circuit domain also can be introduced extra parasitic capacitance, further limit the performance of SFDR under high frequency situations.

At present, there is a kind of method to attempt going to alleviate the problem of DAC output impedance deficiency under high frequency, way (the list of references: A 12b 2.9GS/s DAC with IM3 <-60dBc Beyond 1GHz in 65nm CMOS of the little current branch of increase of the middle C.H-Lin proposition of 2009 ISSCCs (ISSCC2009), C-H.Lin, F.van der Goes, J.Westra, J.Mulder, Y.Lin, E.Arslarn, E.Ayranci, X.Liu, K.Bult, ISSCC2009, Session 4) but because its principle is limit, very limited to the lifting of SFDR.

Summary of the invention

(1) technical problem that will solve

The technical problem to be solved in the present invention is: how a kind of current mode digital-to-analog converter is provided, makes the output impedance of digital to analog converter not rely on input as far as possible, and then reduce due to the harmonic wave in limited the caused output of output impedance.

(2) technical scheme

For addressing the above problem, the invention provides a kind of current mode digital-to-analog converter, comprise decoder and a plurality of current source and switch module, described each current source and switch module comprise:

Current source cell;

The first output and the second output;

The first switch element, is connected between described current source cell and the first output, and controlled by the first control signal of described decoder output; And

Second switch unit, is connected between described current source cell and the second output, and be subject to the output of described decoder, control with anti-phase the second control signal of described the first control signal;

Described digital to analog converter is corresponding with at least one current source and switch module is also provided with complementary current branch road, and described complementary current branch road comprises:

Branch current source unit;

Branch road the first switch element, is connected between described branch current source unit and described the first output, and controlled by described the second control signal; And

Branch road second switch unit, is connected between described branch current source unit and described the second output, and controlled by described the first control signal.

Preferably, the size of current of described current source cell and branch current source unit is unequal.

Preferably, the metal-oxide-semiconductor device that described each switch element is source electrode with respective current sources unit is connected, drain electrode is connected with corresponding output end, grid is connected with corresponding control signal.

Preferably, described digital to analog converter also comprises that drain electrode is connected with branch road first switch element of described the first switch element and respective complementary current branch, the first output metal-oxide-semiconductor that source electrode is connected with described the first output, drain electrode is connected with the branch road second switch unit of described second switch unit and respective complementary current branch, the second output metal-oxide-semiconductor that source electrode is connected with described the second output, the grid of described the first output metal-oxide-semiconductor and the second output metal-oxide-semiconductor is connected to bias voltage.

Preferably, described each current source is corresponding with switch module is provided with described complementary current branch road.

(3) beneficial effect

The present invention by current source with in switch module, add the complementary current branch road in parallel with original current branch, thereby make for different inputs, the output impedance of DAC approaches constant, this is well suppressed the high order harmonic component of DAC, thereby improved the linearity, the invention enables the output impedance of DAC and the correlation of signal significantly to reduce, thereby can improve significantly SFDR.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of typical current mode digital-to-analog converter in prior art;

Fig. 2 is the function relation curve figure that in prior art, 14 digit currents drive the SFDR of DAC and the output impedance of switching current source unit;

Fig. 3 (a) is according to the current source of the embodiment of the present invention one DAC and the electrical block diagram of switch module;

Fig. 3 (b) is the current source of DAC and the electrical block diagram of switch module in prior art;

Fig. 4 is the simulation result figure according to the frequency response characteristic of the output impedance of embodiment of the present invention DAC;

Fig. 5 be according to the embodiment of the present invention in different impedance matching situations, the schematic diagram that the SFDR value of DAC changes along with output impedance;

Fig. 6 is the emulation schematic diagram changing with frequency input signal according to the SFDR value of the DAC of the embodiment of the present invention and prior art DAC;

Fig. 7 is according to the current source of the embodiment of the present invention two DAC and the electrical block diagram of switch module;

Fig. 8 is according to the current source of the embodiment of the present invention three DAC and the electrical block diagram of switch module;

Fig. 9 is according to the current source of the embodiment of the present invention four DAC and the electrical block diagram of switch module;

Figure 10 is according to the current source of the embodiment of the present invention five DAC and the electrical block diagram of switch module;

Figure 11 is according to the current source of the embodiment of the present invention six DAC and the electrical block diagram of switch module;

Figure 12 is according to the current source of the embodiment of the present invention seven DAC and the electrical block diagram of switch module.

Embodiment

Below in conjunction with drawings and Examples, that the present invention is described in detail is as follows.

Embodiment mono-:

As shown in Fig. 3 (a), the current mode digital-to-analog converter of the present embodiment, comprises decoder and a plurality of current source and switch module, and described each current source and switch module comprise:

Current source cell 101, in the present embodiment, current source cell 101 comprises tube of current M0 and Cascode pipe M1;

The first output 201 and the second output 202;

The first switch element Ma, is connected between described current source cell 101 and the first output 201, and controlled by the first control signal P of described decoder output; And

Second switch unit Mb, is connected between described current source cell 101 and the second output 202, and be subject to the output of described decoder, control with anti-phase the second control signal N of described the first control signal P; Described here is anti-phase: under the effect of described the first control signal and the second control signal, when the first switch element is closed, second switch unit is closed when second switch cell conduction, the first switch element conducting.Described digital to analog converter is corresponding with each current source and switch module is also provided with complementary current branch road, and described complementary current branch road comprises:

Branch current source unit 102, in the present embodiment, branch current source unit 102 comprises tube of current Mb0 and Cascode pipe Mb1;

Branch road the first switch element Ma2, is connected between described branch current source unit and described the first output 201, and controlled by described the second control signal N; And

Branch road second switch unit Mb2, is connected between described branch current source unit 102 and described the second output 202, and controlled by described the first control signal P.

The present embodiment is by adjusting the parameter of current source and switch module and complementary current branch road, and for example the breadth length ratio of metal-oxide-semiconductor, makes the ratio of the size of current of current source cell 101 and branch current source unit 102 be: I ₁: I ₂=m: n, wherein m and n are unequal real number.

Described the first switch element Ma and second switch unit Mb be source electrode be connected, drain with described current source cell 101 be connected with the second output 202 with described the first output 201 respectively, grid is respectively for two metal-oxide-semiconductor devices of described the first control signal P and the second control signal N input.

Described branch road the first switch element Ma2 and branch road second switch unit Mb2 be source electrode be connected, drain with described branch current source unit 102 be connected with the second output 202 with described the first output 201 respectively, grid is respectively for two metal-oxide-semiconductor devices of described the second control signal N and the first control signal P input.

Now, the control signal of no matter exporting is the first control signal or the second control signal, in any one current source and switch module, from any one output, always there is a path that is connected to power supply Vdd by switch and current source, and the output impedance of these paths is close to identical, therefore output impedance do not rely on input, and high order harmonic component is well suppressed.

Supposing in Fig. 3 (a) that decoder is exported the first control signal P makes switch conduction, and the direct current output impedance of now seeing from the past current source of positive output end (i.e. the first output) of DAC is:

$Z_{\mathrm{out}}\&ap;g_{m\_\mathrm{Ma}}{r}_{\mathrm{ds}\_\mathrm{Ma}}\left(g_{m\_M1}{r}_{\mathrm{ds}\_M1}{r}_{\mathrm{ds}0}\right)\&ap;\frac{4V_E{L}_{\mathrm{Ma}}}{V_{\mathrm{ov}\_\mathrm{Ma}}}\frac{V_E{L}_{M1}}{V_{\mathrm{ov}\_M1}}\frac{V_E{L}_{M0}}{{\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="HDA0000098862250000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_1}.$

G in formula _mfor transistorized mutual conductance, r _dsthe output resistance of transistor drain when considering channel-length modulation, V _efor transistorized ell profit voltage, L is transistorized channel length, I ₁for flowing through the electric current of transistor Ma.The electric current that flows through described current source and switch module and corresponding complementary current branch road thereof is not identical, so can have any different in output impedance.If the output impedance of negative output terminal (i.e. the second output) is Z in Fig. 3 (a) _out'.When high frequency, output impedance also needs to consider the impact of electric capacity in current branch.But, as shown in Figure 4, under high frequency situations, Z _outwith Z _out' both value is more approaching.

When the supplied with digital signal of n bit total temperature meter code DAC is sin (ω t), note N=2 ⁿ-1, I ₁for the electric current of Ma, I ₂for the electric current of Ma2, I=I ₁+ I ₂, Δ I=I ₁-I ₂, the electric current of the first output (be in Fig. 3 (a)+end, or claim 201 ends) and the second output (be in Fig. 3-hold, or claim 202 ends) is respectively:

$I_a=\frac{1+\sin \left(\mathrm{\&omega;t}\right)}{2}{\mathrm{<figure-callout\; id="1"\; label="NI"\; filenames="HDA0000098862250000012.png"\; state="\{\{state\}\}">NI</figure-callout>}}_1+\frac{1-\sin \left(\mathrm{\&omega;t}\right)}{2}{\mathrm{<figure-callout\; id="2"\; label="NI"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">NI</figure-callout>}}_2=\frac{N}{2}(I+\mathrm{\&Delta;}I\sin \left(\mathrm{\&omega;t}\right)),$

$I_b=\frac{1-\sin \left(\mathrm{\&omega;t}\right)}{2}{\mathrm{<figure-callout\; id="1"\; label="NI"\; filenames="HDA0000098862250000012.png"\; state="\{\{state\}\}">NI</figure-callout>}}_1+\frac{1+\sin \left(\mathrm{\&omega;t}\right)}{2}{\mathrm{<figure-callout\; id="2"\; label="NI"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">NI</figure-callout>}}_2=\frac{N}{2}(I-\mathrm{\&Delta;}I\sin \left(\mathrm{\&omega;t}\right))$

If ignore Z _outwith Z _out' between error, think Z _outwith Z _out' equate, the difference of DAC is output as:

V _out(ωt)＝(N·ΔI·sin(ωt))×(R _L||(Z _out/N))；

If do not ignore this error, the output resistance of the first output and the second output is respectively:

$Z_a=R_L\left|\right|\frac{Z_{\mathrm{out}}}{\frac{1+\sin \left(\mathrm{\&omega;t}\right)}{2}N}\left|\right|\frac{{Z_{\mathrm{out}}}^{\&prime;}}{\frac{1-\sin \left(\mathrm{\&omega;t}\right)}{2}N}\stackrel{\mathrm{\&Delta;}}{=}\frac{A}{B-\sin \left(\mathrm{\&omega;t}\right)},$

$Z_b=R_L\left|\right|\frac{Z_{\mathrm{out}}}{\frac{1-\sin \left(\mathrm{\&omega;t}\right)}{2}N}\left|\right|\frac{{Z_{\mathrm{out}}}^{\&prime;}}{\frac{1+\sin \left(\mathrm{\&omega;t}\right)}{2}N}\stackrel{\mathrm{\&Delta;}}{=}\frac{A}{B+\sin \left(\mathrm{\&omega;t}\right)},$

Wherein

$A=\frac{2Z_{\mathrm{out}}k}{N(1-k)},$ $B=\frac{2Z_{\mathrm{out}}k+N{R}_L(1+k)}{(1-k)R_L},$ and $k\stackrel{\mathrm{\&Delta;}}{=}\frac{{Z_{\mathrm{out}}}^{\&prime;}}{Z_{\mathrm{out}}}.$

Finally we ignore above higher order term error seven times, and output voltage is:

$V_{\mathrm{out}}=\frac{\mathrm{AN}(\mathrm{B\&Delta;I}+I)}{B^2}((1+\frac{3}{4{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">B</figure-callout>}}^2}+\frac{5}{8B^4}+\frac{35}{64B^6})\sin \left(\mathrm{\&omega;t}\right)$

$-(\frac{1}{4{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">B</figure-callout>}}^2}+\frac{5}{16B^4}+\frac{21}{64B^6})\sin 3\left(\mathrm{\&omega;t}\right)+\&CenterDot;\&CenterDot;\&CenterDot;),$

So derive SFDR, be:

$\mathrm{SFDR}=20\lg \left(\frac{64B^6+48B^4+40{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">B</figure-callout>}}^2+35}{16B^4+20{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA0000098862250000051.png"\; state="\{\{state\}\}">B</figure-callout>}}^2+21}\right),$

Adopt after the art of this patent, the matching error of DAC positive and negative two ends output impedance (being k-1) has been reduced to approximately 5% from 30%.Under different matching errors, the simulation result of SFDR is shown in accompanying drawing 5 (in Fig. 5, the data such as 5%, 10% are the matching error of positive and negative two ends output impedance, i.e. k-1).As can be seen from Figure 5 the SFDR that the present embodiment has increased the current mode DAC after complementary current branch road is than not improved before increase.

Utilize the integrated circuit of a 14bit 1GS/s DAC of the present embodiment art designs to use Cadence

simulation result see Fig. 6.Can find out, after having increased complementary current branch road, the SFDR performance boost of DAC about 10-15dB (under different incoming frequencies, performance is different).

Embodiment bis-:

As shown in Figure 7, the present embodiment principle is identical with embodiment mono-, in the present embodiment, current source and switch module have the current source cell 101 being connected between power supply Vdd and first, second switch element sa, sb, and complementary current branch road has the branch current source unit 102 being connected between power supply Vdd and first, second switch element of branch road sa2, sb2.Described the first switch element sa is connected with the first output 201 with branch road the first switch element sa2, and described second switch unit sb is connected with the second output 202 with branch road second switch unit sb2.

Wherein said the first switch element Sa and branch road second switch cell S b2 are controlled by the first control signal P, and second switch cell S b and branch road the first switch element Sa2 are by controlling with anti-phase the second control signal N of described the first control signal P.In the present embodiment, the first switch element Sa, second switch cell S b, branch road the first switch element Sa2 and branch road second switch cell S b2 are PMOS pipe.

The electric current sum that described current source cell 101 exports the first switch element Sa, second switch cell S b to is the electric current sum that described branch current source unit 102 exports branch road the first switch element Sa2 and branch road second switch cell S b2 to is

due to m and n unequal, therefore above-mentioned two electric currents are also unequal.

Embodiment tri-:

As shown in Figure 8, the present embodiment structure and embodiment bis-are similar, and difference is, the first switch element Sa described in the present embodiment, second switch cell S b, branch road the first switch element Sa2 and branch road second switch cell S b2 are NMOS pipe; Described current source cell 101 and branch current source unit 102 are connected between switch element and ground.

Embodiment tetra-and five:

As shown in Figures 9 and 10, embodiment tetra-and five is similar with embodiment bis-and three structure respectively, and difference is:

1) in embodiment tetra-and five, described current source cell and branch current source unit are replaced by a total current source cell 100, the current distributing of total current source unit 100 outputs is to described current source and switch module and complementary current branch road thereof, if wherein the electric current of total current source unit 100 outputs is I _always, go to the first switch element Sa of current source and switch module, the electric current sum of second switch cell S b is

go to the branch road first switch element Sa2 of complementary current branch road and the electric current sum of complementary current branch road second switch cell S b2 is

2) in embodiment tetra-and five, also comprise that drain electrode is connected with the branch road first switch element sa2 of described the first switch element sa and complementary current branch road, the first output metal-oxide-semiconductor 301 that source electrode is connected with described the first output 201, drain electrode is connected with the branch road second switch unit sb2 of described second switch unit sb and complementary current branch road, the second output metal-oxide-semiconductor 302 that source electrode is connected with described the second output 202, the grid of described the first output metal-oxide-semiconductor 301 and the second output metal-oxide-semiconductor 302 is connected to bias voltage.The effect of this first output metal-oxide-semiconductor 301 and the second output metal-oxide-semiconductor 302 comprises several aspects: 1, increase output impedance; 2, increase the isolation of control signal and output; 3, further reduce the impedance mismatching of positive-negative output end.

Embodiment six and seven:

As shown in Figure 11 and Figure 12, embodiment six and seven is similar with embodiment bis-and three structure respectively, difference is, embodiment six and seven is provided with the first output metal-oxide-semiconductor 301 on the first output 201, metal-oxide-semiconductor 301 in function and connected mode and embodiment four and five is similar, on the second output 202, be provided with the second output metal-oxide-semiconductor 302, the metal-oxide-semiconductor 302 in function and connected mode and embodiment four and five is similar.

The above embodiment of the present invention significantly reduces the output impedance of DAC and the correlation of signal, thereby can improve significantly SFDR.

Above execution mode is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.

Claims (7)

1. a current mode digital-to-analog converter, comprises decoder and a plurality of current source and switch module, and described each current source and switch module comprise:

Current source cell;

The first output and the second output;

The first switch element, is connected between described current source cell and the first output, and controlled by the first control signal of described decoder output; And

Second switch unit, is connected between described current source cell and the second output, and be subject to the output of described decoder, control with anti-phase the second control signal of described the first control signal;

It is characterized in that, described digital to analog converter is corresponding with at least one current source and switch module is also provided with complementary current branch road, and described complementary current branch road comprises:

Branch current source unit;

Branch road the first switch element, is connected between described branch current source unit and described the first output, and controlled by described the second control signal; And

Branch road second switch unit, is connected between described branch current source unit and described the second output, and controlled by described the first control signal.

2. current mode digital-to-analog converter as claimed in claim 1, is characterized in that, the size of current of described current source cell and branch current source unit is unequal.

3. current mode digital-to-analog converter as claimed in claim 1, is characterized in that, the metal-oxide-semiconductor device that described each switch element is source electrode with respective current sources unit is connected, drain electrode is connected with corresponding output end, grid is connected with corresponding control signal.

4. current mode digital-to-analog converter as claimed in claim 2, is characterized in that, the metal-oxide-semiconductor device that described each switch element is source electrode with respective current sources unit is connected, drain electrode is connected with corresponding output end, grid is connected with corresponding control signal.

5. current mode digital-to-analog converter as claimed in claim 1, it is characterized in that, described digital to analog converter also comprises that drain electrode is connected with branch road first switch element of described the first switch element and respective complementary current branch, the first output metal-oxide-semiconductor that source electrode is connected with described the first output, drain electrode is connected with the branch road second switch unit of described second switch unit and respective complementary current branch, the second output metal-oxide-semiconductor that source electrode is connected with described the second output, the grid of described the first output metal-oxide-semiconductor and the second output metal-oxide-semiconductor is connected to bias voltage.

6. current mode digital-to-analog converter as claimed in claim 2, it is characterized in that, described digital to analog converter also comprises that drain electrode is connected with branch road first switch element of described the first switch element and respective complementary current branch, the first output metal-oxide-semiconductor that source electrode is connected with described the first output, drain electrode is connected with the branch road second switch unit of described second switch unit and respective complementary current branch, the second output metal-oxide-semiconductor that source electrode is connected with described the second output, the grid of described the first output metal-oxide-semiconductor and the second output metal-oxide-semiconductor is connected to bias voltage.

7. the current mode digital-to-analog converter as described in any one in claim 1～6, is characterized in that, described each current source is corresponding with switch module is provided with described complementary current branch road.

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