CN102354486A

CN102354486A - Liquid crystal display capable of compensating gate voltage and method for compensating gate voltage

Info

Publication number: CN102354486A
Application number: CN2011102538138A
Authority: CN
Inventors: 蔡明翰
Original assignee: CPTF Optronics Co Ltd; Chunghwa Picture Tubes Ltd
Current assignee: CPTF Optronics Co Ltd; Chunghwa Picture Tubes Ltd
Priority date: 2011-08-31
Filing date: 2011-08-31
Publication date: 2012-02-15
Anticipated expiration: 2031-08-31
Also published as: CN102354486B

Abstract

The invention discloses a method for compensating a gate voltage of a liquid crystal display, comprising the following steps of: generating a first high gate voltage, a second high gate voltage and a first low gate voltage; generating a first scanning starting signal and a reference frequency; generating and outputting a second scanning starting signal, a first frequency, a second frequency, a third frequency, a fourth frequency and the first low gate voltage according to the first high gate voltage, the second high gate voltage, the first low gate voltage, the first scanning starting signal and the reference frequency; and driving a plurality of pixels of a liquid crystal panel according to the second scanning starting signal, the first frequency, the second frequency, the third frequency, the fourth frequency and the first low gate voltage so as to improve the quality of a display frame of the liquid crystal panel.

Description

Can compensate the LCD and the method thereof of gate voltage

Technical field

The invention relates to a kind of LCD and method thereof, refer to a kind of LCD and method thereof that compensates gate voltage especially.

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Background technology

Please with reference to Fig. 1, Fig. 2 A and Fig. 2 B; Fig. 1 is the synoptic diagram for the double-gate utmost point (dual gate) pixel of explanation LCD; Fig. 2 A be for synoptic diagram and Fig. 2 B that prior art explanation has a gate drive circuit of the identical frequency of two groups of anti-phases and frequency be synoptic diagram for the time sequential routine of the gate drive circuit of key diagram 2A.As shown in Figure 1; Because the row pixel in the liquid crystal panel is corresponding two gate lines (gate line); So the gate line number of double-gate utmost point pixel is the twice for the gate line number of single gate pixel, and double-gate utmost point pixel system is by two groups of anti-phases and the identical corresponding gate line of frequency drives of frequency.Shown in Fig. 2 A; Gate drive unit G1, G3, G5 in the gate drive circuit ... Be corresponding to one group of anti-phase and identical frequency CK1, the CKB1 of frequency, with gate drive circuit in gate drive unit G2, G4 ... System is corresponding to another group anti-phase and identical frequency CK2, the CKB2 of frequency.In addition; Gate drive unit G1, G2, G3, G4, G5 ... Be by gate line GL1, GL2, GL3, GL4, GL5 ... Drive a plurality of pixels of liquid crystal panel; Wherein STV1 is gate drive unit G1, G3, G5 ... Corresponding scanning start signal, STV2 is gate drive unit G2, G4 ... Corresponding scanning start signal.Shown in Fig. 2 B, the opening time of the opening time of a gate line and last gate line is that part overlaps.Therefore; When a thin film transistor (TFT) is opened according to the voltage of corresponding gate line; In preceding half section (the oblique line district of Fig. 2 B) that thin film transistor (TFT) is opened, be the data that write last pixel corresponding to the pixel of thin film transistor (TFT), and in second half section that thin film transistor (TFT) is opened; Pixel corresponding to thin film transistor (TFT) is the data that writes corresponding to pixel, and wherein D1, D2, D3, D4, D5 are the data voltages for source electrode drive circuit output.

Please with reference to Fig. 3 A and Fig. 3 B; Fig. 3 A is that preceding half section of opening at thin film transistor (TFT) for explanation writes with corresponding to the opposite polarity data of the data of pixel the time; The synoptic diagram of the charge condition of pixel; With Fig. 3 B is that preceding half section of opening at thin film transistor (TFT) for explanation writes with corresponding to the identical data of the polarity of the data of pixel the time synoptic diagram of the charge condition of pixel.Shown in Fig. 3 A and Fig. 3 B, the pixel potential among Fig. 3 A is the pixel potential that is lower than among Fig. 3 B, that is the brightness of the pixel among Fig. 3 A is the brightness that is lower than the pixel among Fig. 3 B.Please with reference to Fig. 4 A and Fig. 4 B; Fig. 4 A is for explaining in the double-gate very thin films LCD of 2 lines counter-rotatings (2-line inversion); Synoptic diagram with Z font order driving pixels; With Fig. 4 B be for explanation in the double-gate very thin films LCD of 2 lines counter-rotatings, with the synoptic diagram of arc type order driving pixels, wherein (+), (-) are the polarity of represent pixel.Shown in Fig. 4 A, the brightness of the pixel of odd-numbered line is the brightness that is lower than the pixel of even number line, so fringe phenomena can appear in double-gate very thin films display panels.Shown in Fig. 4 B, though the order type of drive of arc type can reduce the striped sense of double-gate very thin films LCD, and unresolved pixel charge condition different problems.So when pixel is in more harsh charge condition (under low temperature or high frequency), on double-gate very thin films LCD, will show the tessellated bright dark staggered bad picture that shows, cause the quality of picture not good.

Summary of the invention

One embodiment of the invention provide a kind of LCD that compensates gate voltage.This LCD comprises a direct current voltage generation circuit, time schedule controller, a frequency generating circuit and a liquid crystal panel.It is in order to producing one first gate high voltage, one second gate high voltage and one first gate low-voltage that this DC voltage produces circuit, and wherein this first gate high voltage is to be higher than this second gate high voltage; This time schedule controller is in order to produce one first a scanning start signal and a reference frequency; This frequency generating circuit; Being coupled to this DC voltage produces between circuit and this time schedule controller; In order to according to this first gate high voltage, this second gate high voltage, this first gate low-voltage, this first scanning start signal and this reference frequency, produce and export one second scanning start signal, a first frequency, a second frequency, one the 3rd frequency, one the 4th frequency and this first gate low-voltage; This liquid crystal panel comprises a plurality of pixels and a gate drive circuit.This gate drive circuit is to be coupled to this frequency generating circuit; This gate drive circuit comprises a plurality of gate drive unit; Wherein this a plurality of gate drive unit is in order to according to this second scanning start signal, this first frequency, this second frequency, the 3rd frequency, the 4th frequency and this first gate low-voltage; Drive this a plurality of pixels; To improve the quality of this liquid crystal panel display frame, wherein the phase place of the phase place of this first frequency and the 3rd frequency is opposite, and the phase place of the phase place of this second frequency and the 4th frequency is opposite; Wherein the 4n+1 gate drive unit in this a plurality of gate drive unit is that the 4n+2 gate drive unit that receives in this first frequency, this a plurality of gate drive unit is that the 4n+3 gate drive unit that receives in this second frequency, this a plurality of gate drive unit is that the 4n+1 gate drive unit that receives in the 3rd frequency and this a plurality of gate drive unit is to receive the 4th frequency, and wherein n ≧ 0 and n are integer.

Another embodiment of the present invention provides a kind of method that compensates the gate voltage of LCD.This method comprises generation one first gate high voltage, one second gate high voltage and one first gate low-voltage, and wherein this first gate high voltage is to be higher than this second gate high voltage; Produce one first a scanning start signal and a reference frequency; According to this first gate high voltage, this second gate high voltage, this first gate low-voltage, this first scanning start signal and this reference frequency, produce and export one second scanning start signal, a first frequency, a second frequency, one the 3rd frequency, one the 4th frequency and this first gate low-voltage; According to this second scanning start signal, this first frequency, this second frequency, the 3rd frequency, the 4th frequency and this first gate low-voltage; Drive a plurality of pixels of a liquid crystal panel; To improve the quality of this liquid crystal panel display frame; Wherein the phase place of the phase place of this first frequency and the 3rd frequency is opposite, and the phase place of the phase place of this second frequency and the 4th frequency is opposite; Wherein the 4n+1 gate drive unit in a plurality of gate drive unit of this liquid crystal panel is that the 4n+2 gate drive unit that receives in this first frequency, this a plurality of gate drive unit is that the 4n+3 gate drive unit that receives in this second frequency, this a plurality of gate drive unit is that the 4n+1 gate drive unit that receives in the 3rd frequency and this a plurality of gate drive unit is to receive the 4th frequency, and wherein n ≧ 0 and n are integer.

The present invention provides a kind of LCD and method thereof that compensates gate voltage.This LCD and method thereof are to utilize different gate high voltages, with the uneven problem of charge condition between a plurality of picture elements that overcome a liquid crystal panel.Because it is little that the diversity ratio prior art of the charge condition between a plurality of picture elements of this liquid crystal panel comes, so compared to prior art, the present invention can improve the quality of this liquid crystal panel display frame.

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Description of drawings

Fig. 1 is the synoptic diagram for the double-gate utmost point pixel of explanation LCD.

Fig. 2 A is the synoptic diagram that has the gate drive circuit of the identical frequency of two groups of anti-phases and frequency for prior art explanation.

Fig. 2 B is the synoptic diagram for the time sequential routine of the gate drive circuit of key diagram 2A.

Fig. 3 A be for explanation before open-interval half section write with the time synoptic diagram of the charge condition of pixel corresponding to the opposite polarity data of the data of pixel.

Fig. 3 B be for explanation before open-interval half section write with the time synoptic diagram of the charge condition of pixel corresponding to the identical data of the polarity of the data of pixel.

Fig. 4 A is for explaining in the double-gate very thin films LCD of 2 lines counter-rotating, with the synoptic diagram of Z font order driving pixels.

Fig. 4 B is for explaining in the double-gate very thin films LCD of 2 lines counter-rotatings (2-line inversion), with the synoptic diagram of arc type order driving pixels.

Fig. 5 is a kind of synoptic diagram that compensates the LCD of gate voltage of one embodiment of the invention explanation.

Fig. 6 A is the synoptic diagram for explanation first frequency, second frequency, the 3rd frequency and the 4th frequency.

Fig. 6 B is for explaining that the 4n+1 gate drive unit in a plurality of gate drive unit is that reception first frequency, 4n+2 gate drive unit are that reception second frequency, 4n+3 gate drive unit are that reception the 3rd frequency and 4n+4 gate drive unit are the synoptic diagram that receives the 4th frequency.

Fig. 7 A is the charging synoptic diagram for the explanation pixel identical with the polarity of the data of last pixel.

Fig. 7 B is the charging synoptic diagram of explanation with the opposite polarity pixel of the data of last pixel.

Fig. 8 A is a kind of synoptic diagram that compensates the LCD of gate voltage of another embodiment of the present invention explanation.

Fig. 8 B is the synoptic diagram for first frequency, second frequency, the 3rd frequency and the 4th frequency of explanation LCD.

Fig. 9 A is the synoptic diagram for first frequency, second frequency, the 3rd frequency and the 4th frequency of the LCD of another embodiment of the present invention explanation 1+2 line counter-rotating.

Fig. 9 B is the synoptic diagram for the pixel arrangement mode of the LCD of explanation 1+2 line counter-rotating.

Figure 10 A is the synoptic diagram that first frequency, second frequency, the 3rd frequency and the 4th frequency of the LCD that 4 lines reverse are described for another embodiment of the present invention.

Figure 10 B is the synoptic diagram for the pixel arrangement mode of the LCD that the counter-rotating of 4 lines is described.

Figure 11 is the process flow diagram of method that compensates the gate voltage of LCD for another embodiment of the present invention explanation is a kind of.

Figure 12 is the process flow diagram of method that compensates the gate voltage of LCD for another embodiment of the present invention explanation is a kind of.

[primary clustering symbol description]

500 LCDs

502,802 DC voltages produce circuit

504 time schedule controllers

506,806 frequency generating circuits

508 liquid crystal panels

510 printed circuit board (PCB)s

512 source electrode drive circuits

5082 gate drive circuits

CK1, CKB1, CK2, CKB2 frequency

The CLK1 first frequency

The CLK2 second frequency

CLK3 the 3rd frequency

CLK4 the 4th frequency

The CLKV reference frequency

D1, D2, D3, D4, D5 data voltage

G1, G2, G3, G4, G5, Gm-1, Gm gate drive unit

GL1, GL2, GL3, GL4, GL5, GLm-1, GLm gate line

The VGH1 first gate high voltage

The VGH2 second gate high voltage

The VGL1 first gate low-voltage

The VGL2 second gate low-voltage

The STPV first scanning start signal

The STP second scanning start signal

STV1, STV2 scan start signal

1100 to 1110,1200 to 1210 steps

Embodiment

Please with reference to Fig. 5, Fig. 5 is a kind of synoptic diagram that compensates the LCD 500 of gate voltage of one embodiment of the invention explanation, and wherein LCD 500 is to be the LCD of 2 lines counter-rotating.LCD 500 comprises a direct current voltage generation circuit 502, time schedule controller 504, a frequency generating circuit 506 and a liquid crystal panel 508, and wherein to produce circuit 502, time schedule controller 504 and frequency generating circuit 506 be to be positioned on the printed circuit board (PCB) 510 to DC voltage.It is in order to producing one first gate high voltage VGH1, one second gate high voltage VGH2 and one first gate low-voltage VGL1 that DC voltage produces circuit 502, and wherein the first gate high voltage VGH1 is higher than the second gate high voltage VGH2; Time schedule controller 504 is in order to produce one first a scanning start signal STPV and a reference frequency CLKV; Frequency generating circuit 506 is to be coupled to DC voltage to produce between circuit 502 and the time schedule controller 504; In order to scan start signal STPV and reference frequency CLKV according to the first gate high voltage VGH1, the second gate high voltage VGH2, the first gate low-voltage VGL1, first; Produce and export one second scanning start signal STP, a first frequency CLK1, a second frequency CLK2, one the 3rd frequency CLK3, one the 4th frequency CLK4 and the first gate low-voltage VGL1; Wherein the phase place of the phase place of first frequency CLK1 and the 3rd frequency CLK3 is opposite, and the phase place of the phase place of second frequency CLK2 and the 4th frequency CLK4 is opposite.Liquid crystal panel 508 comprises a plurality of pixels and a gate drive circuit 5082.Gate drive circuit 5082 is to be coupled to frequency generating circuit 506; Gate drive circuit 5082 comprises a plurality of gate drive unit G1-Gm; Wherein a plurality of gate drive unit G1-Gm is in order to scan start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 and the first gate low-voltage VGL1 according to second; See through a plurality of pixels that gate line GL1-GLm drives liquid crystal panel 508; Improving the quality of liquid crystal panel 508 display frames, and m is for greater than 1 integer.In addition; 4n+1 gate drive unit among a plurality of gate drive unit G1-Gm is that the 4n+2 gate drive unit that receives among first frequency CLK1, a plurality of gate drive unit G1-Gm is that the 4n+3 gate drive unit that receives among second frequency CLK2, a plurality of gate drive unit G1-Gm is that the 4n+4 gate drive unit that receives among the 3rd frequency CLK3 and a plurality of gate drive unit G1-Gm is to receive the 4th frequency CLk4; N ≧ 0 wherein; N is integer, m＞n, and m ≧ 4n+4.(this section to describe be; Total total m gate drive unit G1-Gm and m bar gate line GL1-GLm; Wherein the 1st, 5,9 of m gate drive unit G1-Gm ... (4n+1) the gate drive unit is to receive first frequency CLK1; The 2nd, 6,10 of m gate drive unit G1-Gm ... (4n+2) the gate drive unit is to receive second frequency CLK2, the 3rd, 7,11 of m gate drive unit G1-Gm ... (4n+3) the gate drive unit is to receive the 4th, 8,12 of the 3rd frequency CLK3 and m gate drive unit G1-Gm ... (4n+4) the gate drive unit is to receive the 4th frequency CLk4.Therefore, the relational expression of m and n is to be m＞n, and m ≧ 4n+4.) in addition, LCD 500 comprises one source pole driving circuit 512 in addition, in order to when the thin film transistor (TFT) that is coupled to a pixel is opened, see through corresponding source electrode line pixel is charged.

Please with reference to Fig. 6 A and Fig. 6 B; Fig. 6 A is the synoptic diagram for explanation first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4; With Fig. 6 B be for explaining that 4n+1 gate drive unit among a plurality of gate drive unit G1-Gm is to receive first frequency CLK1,4n+2 gate drive unit to receive second frequency CLK2,4n+3 gate drive unit to receive the 3rd frequency CLK3 and 4n+4 gate drive unit is the synoptic diagram that receives the 4th frequency CLk4; Wherein (+), (-) are the polarity of represent pixel; Gate drive circuit 5082 is to drive a plurality of pixels in proper order with the Z font, and S1, S2, S3 are source electrode line (source line).Shown in Fig. 6 A, the phase place of the phase place of first frequency CLK1 and the 3rd frequency CLK3 is opposite, and the phase place of the phase place of second frequency CLK2 and the 4th frequency CLK4 is opposite.In addition; The accurate position of the high voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the second gate high voltage VGH2; The accurate position of the high voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the first gate high voltage VGH1, and the accurate position of low-voltage of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 is to be the first gate low-voltage VGL1.Shown in Fig. 6 B, with the opposite polarity pixel of the data of last pixel be corresponding to gate line G1, G3, G5 ..., and be corresponding to gate line G2, G4, G6 with the identical pixel of polarity of the data of last pixel ...Therefore; Gate line G1, G5, G9 ... Be corresponding to first frequency CLK1; Gate line G3, G7, G11 ... Be corresponding to the 3rd frequency CLK3, gate line G2, G6, G10 ... Be corresponding to second frequency CLK2, with gate line G4, G8, G12 ... System is corresponding to the 4th frequency CLK4.

Please with reference to Fig. 7 A and Fig. 7 B, Fig. 7 A be for the charging synoptic diagram of the explanation pixel identical and Fig. 7 B with the polarity of the data of last pixel be to be the charging synoptic diagram of opposite polarity pixel of the data of explanation and last pixel.Shown in Fig. 7 A and Fig. 7 B; Because the first gate high voltage VGH1 is higher than the second gate high voltage VGH2, so the difference between the charge condition of the pixel of the charge condition of the pixel of Fig. 7 A and Fig. 7 B can be littler than the difference between the charge condition of the pixel of the charge condition of the pixel of Fig. 3 A and Fig. 3 B.

Please with reference to Fig. 8 A and Fig. 8 B; Fig. 8 A is a kind of synoptic diagram that compensates the LCD 800 of gate voltage of another embodiment of the present invention explanation; With Fig. 8 B be the synoptic diagram of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 for explanation LCD 800, wherein LCD 800 is to be the LCD of 2 lines counter-rotating.The difference of LCD 800 and LCD 500 is that a direct current voltage generation circuit 802 produces one second gate low-voltage VGL2 in addition to frequency generating circuit 806; Frequency generating circuit 806 is according to the first gate high voltage VGH1, the second gate high voltage VGH2, the first gate low-voltage VGL1, the second gate low-voltage VGL2, first scanning start signal STPV and the reference frequency CLKV; Produce and export the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4, the first gate low-voltage VGL1 and the second gate low-voltage VGL2; To scan start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4, the first gate low-voltage VGL1 and the second gate low-voltage VGL2 according to second with gate drive circuit 5082; Drive a plurality of pixels of liquid crystal panel 508, wherein the first gate low-voltage VGL1 is higher than the second gate low-voltage VGL2.Therefore; Shown in Fig. 8 B; The accurate position of the high voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the second gate high voltage VGH2; The accurate position of the high voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the first gate high voltage VGH1, and the accurate position of the low-voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the second gate low-voltage VGL2, and the accurate position of the low-voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the first gate low-voltage VGL1.So, the accurate position of the high voltage of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 is for identical with the difference of the accurate position of low-voltage.In LCD 800; Because the accurate position of the high voltage of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 is for identical with the difference of the accurate position of low-voltage, so the difference of the charge condition between a plurality of picture elements of liquid crystal panel 508 is also than next little of prior art.In addition, all the other principle of operation of LCD 800 are all identical with LCD 500, repeat no more at this.

Please with reference to Fig. 9 A and Fig. 9 B; Fig. 9 A be for the synoptic diagram of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 of the LCD of another embodiment of the present invention explanation 1+2 line counter-rotating (1+2-line inversion) and Fig. 9 B be synoptic diagram for the pixel arrangement mode of the LCD of explanation 1+2 line counter-rotating.Shown in Fig. 9 A; The accurate position of the high voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the first gate high voltage VGH1; The accurate position of the high voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the second gate high voltage VGH2; The accurate position of the low-voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the first gate low-voltage VGL1, and the accurate position of the low-voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the second gate low-voltage VGL2.Shown in Fig. 9 B, with the opposite polarity pixel of the data of last pixel be corresponding to gate line G2, G4, G6 ..., and be corresponding to gate line G1, G3, G5 with the identical pixel of polarity of the data of last pixel ...Therefore; Gate line G1, G5, G9 ... Be corresponding to first frequency CLK1; Gate line G3, G7, G11 ... Be corresponding to the 3rd frequency CLK3, gate line G2, G6, G10 ... Be corresponding to second frequency CLK2, with gate line G4, G8, G12 ... System is corresponding to the 4th frequency CLK4.In addition, all the other principle of operation of Fig. 9 A and Fig. 9 B embodiment are all identical with LCD 800, repeat no more at this.

Please with reference to Figure 10 A and Figure 10 B; Figure 10 A is that for another embodiment of the present invention synoptic diagram and Figure 10 B of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 of the LCD of 4 lines counter-rotating (4-line inversion) to be described be the synoptic diagram for the pixel arrangement mode of LCD that the counter-rotating of 4 lines is described.Shown in Figure 10 A; The accurate position of the high voltage of first frequency CLK1 is to be the first gate high voltage VGH1; The accurate position of the high voltage of second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 is to be the second gate high voltage VGH2; The accurate position of the low-voltage of first frequency CLK1 is to be the first gate low-voltage VGL1, and the accurate position of the low-voltage of second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 is to be the second gate low-voltage VGL2.Shown in Figure 10 B, with the opposite polarity pixel of the data of last pixel be corresponding to gate line G1, G5, G9 ..., and be corresponding to gate line G2, G3, G4, G6, G7, G8 with the identical pixel of polarity of the data of last pixel ...Therefore; Gate line G1, G5, G9 ... Be corresponding to first frequency CLK1; Gate line G2, G6, G10 ... Be corresponding to second frequency CLK2, gate line G3, G7, G11 ... Be corresponding to the 3rd frequency CLK3, with gate line G4, G8, G12 ... Be corresponding to the 4th frequency CLK4.In addition, all the other principle of operation of Figure 10 A and Figure 10 B embodiment are all identical with LCD 800, repeat no more at this.

Please with reference to Figure 11, Figure 11 is the process flow diagram of method that compensates the gate voltage of LCD for the another embodiment of the present invention explanation is a kind of.The method of Figure 11 is to utilize LCD 500 explanations of Fig. 5, and detailed step is following:

Step 1100: beginning;

Step 1102: DC voltage produces circuit 502 and produces the first gate high voltage VGH1, the second gate high voltage VGH2 and the first gate low-voltage VGL1;

Step 1104: time schedule controller 504 produces first scanning start signal STPV and the reference frequency CLKV;

Step 1106: frequency generating circuit 506 produces and exports the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 and the first gate low-voltage VGL1 according to the first gate high voltage VGH1, the second gate high voltage VGH2, the first gate low-voltage VGL1, first scanning start signal STPV and the reference frequency CLKV;

Step 1108: gate drive circuit 5082 is according to the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 and the first gate low-voltage VGL1; Drive a plurality of pixels of liquid crystal panel 508, to improve the quality of liquid crystal panel 508 display frames;

Step 1110: finish.

In step 1102; DC voltage produces circuit 502 and produces the first gate high voltage VGH1, the second gate high voltage VGH2 and the first gate low-voltage VGL1 to frequency generating circuit 506, and wherein the first gate high voltage VHG1 is higher than the second gate high voltage VGH2.In step 1104, time schedule controller 504 generations, first scanning start signal STPV and reference frequency CLKV are to frequency generating circuit 506.In step 1106, the phase place of the phase place of first frequency CLK1 and the 3rd frequency CLK3 is opposite, and the phase place of the phase place of second frequency CLK2 and the 4th frequency CLK4 is opposite.In step 1108; Gate drive circuit 5082 is to drive a plurality of pixels in proper order with the Z font, and the 4n+1 gate drive unit among a plurality of gate drive unit G1-Gm is that reception first frequency CLK1,4n+2 gate drive unit are that reception second frequency CLK2,4n+3 gate drive unit are that reception the 3rd frequency CLK3 and 4n+4 gate drive unit are to receive the 4th frequency CLk4.In addition; Shown in Fig. 6 B; With the opposite polarity pixel of the data of last pixel be corresponding to gate line G1, G3, G5 ... And be corresponding to gate line G2, G4, G6 with the identical pixel of polarity of the data of last pixel ... And gate line G1, G5, G9 ... Be corresponding to 4n+1 gate drive unit, gate line G3, G7, G11 ... Be corresponding to 4n+3 gate drive unit, gate line G2, G6, G10 ... Be corresponding to 4n+2 gate drive unit; With with gate line G4, G8, G12 ... Be corresponding to 4n+4 gate drive unit; Wherein the accurate position of the high voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the second gate high voltage VGH2, and the accurate position of the high voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the first gate high voltage VGH1, and accurate of the low-voltage of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 is to be the first gate low-voltage VGL1.In addition, because the first gate high voltage VGH1 is higher than the second gate high voltage VGH2,, cause the quality of liquid crystal panel 508 display frames to become good so the diversity ratio prior art of the charge condition between a plurality of picture elements of liquid crystal panel 508 is little.

Please with reference to Figure 12, Figure 12 is the process flow diagram of method that compensates the gate voltage of LCD for the another embodiment of the present invention explanation is a kind of.The method of Figure 12 is to utilize LCD 800 explanations of Fig. 8 A, and detailed step is following:

Step 1200: beginning;

Step 1202: DC voltage produces circuit 802 and produces the first gate high voltage VGH1, the second gate high voltage VGH2, the first gate low-voltage VGL1 and the second gate low-voltage VGL2;

Step 1204: time schedule controller 504 produces first scanning start signal STPV and the reference frequency CLKV;

Step 1206: frequency generating circuit 806 produces and exports the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4, the first gate low-voltage VGL1 and the second gate low-voltage VGL2 according to the first gate high voltage VGH1, the second gate high voltage VGH2, the first gate low-voltage VGL1, the second gate low-voltage VGL2, first scanning start signal STPV and the reference frequency CLKV;

Step 1208: gate drive circuit 5082 is according to the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4, the first gate low-voltage VGL1 and the second gate low-voltage VGL2; Drive a plurality of pixels of liquid crystal panel 508, to improve the quality of liquid crystal panel 508 display frames;

Step 1210: finish.

The difference of the embodiment of Figure 12 and the embodiment of Figure 11 is in step 1202; DC voltage produces circuit 802 and produces one second gate low-voltage VGL2 in addition to frequency generating circuit 806; In step 1206; Frequency generating circuit 806 is according to the first gate high voltage VGH1, the second gate high voltage VGH2, the first gate low-voltage VGL1, the second gate low-voltage VGL2, first scanning start signal STPV and the reference frequency CLKV; Produce and export the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4, the first gate low-voltage VGL1 and the second gate low-voltage VGL2; And in step 1208; Gate drive circuit 5082 is according to the second scanning start signal STP, first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4, the first gate low-voltage VGL1 and the second gate low-voltage VGL2; Drive a plurality of pixels of liquid crystal panel 508, wherein the first gate low-voltage VGL1 is higher than the second gate low-voltage VGL2.In addition; In step 1206; The accurate position of the high voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the second gate high voltage VGH2; The accurate position of the high voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the first gate high voltage VGH1, and the accurate position of the low-voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the second gate low-voltage VGL2, and the accurate position of the low-voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the first gate low-voltage VGL1.In step 1208; Because the accurate position of the high voltage of first frequency CLK1, second frequency CLK2, the 3rd frequency CLK3, the 4th frequency CLK4 is for identical with the difference of the accurate position of low-voltage; So it is little that the diversity ratio prior art of the charge condition between a plurality of picture elements of liquid crystal panel 508 comes, cause the quality of liquid crystal panel 508 display frames to become good.In addition, all the other principle of operation of the embodiment of Figure 12 all embodiment with Figure 11 are identical, repeat no more at this.

In addition, please with reference to Fig. 9 A and Fig. 9 B.In another embodiment of Figure 12; Shown in Fig. 9 A; The accurate position of the high voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the first gate high voltage VGH1; The accurate position of the high voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the second gate high voltage VGH2, and the accurate position of the low-voltage of second frequency CLK2 and the 4th frequency CLK4 is to be the first gate low-voltage VGL1, and the accurate position of the low-voltage of first frequency CLK1 and the 3rd frequency CLK3 is to be the second gate low-voltage VGL2.Shown in Fig. 9 B, with the opposite polarity pixel of the data of last pixel be corresponding to gate line G2, G4, G6 ..., and be corresponding to gate line G1, G3, G5 with the identical pixel of polarity of the data of last pixel ...Therefore; Gate line G1, G5, G9 ... Be corresponding to first frequency CLK1; Gate line G3, G7, G11 ... Be corresponding to the 3rd frequency CLK3, gate line G2, G6, G10 ... Be corresponding to second frequency CLK2, with gate line G4, G8, G12 ... Be corresponding to the 4th frequency CLK4.

In addition, please with reference to Figure 10 A and Figure 10 B.In another embodiment of Figure 12; Shown in Figure 10 A; The accurate position of the high voltage of first frequency CLK1 is to be the first gate high voltage VGH1; The accurate position of the high voltage of second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 is to be the second gate high voltage VGH2, and the accurate position of the low-voltage of first frequency CLK1 is to be the first gate low-voltage VGL1, and the accurate position of the low-voltage of second frequency CLK2, the 3rd frequency CLK3 and the 4th frequency CLK4 is to be the second gate low-voltage VGL2.Shown in Figure 10 B, with the opposite polarity pixel of the data of last pixel be corresponding to gate line G1, G5, G9 ..., and be corresponding to gate line G2, G3, G4, G6, G7, G8 with the identical pixel of polarity of the data of last pixel ...Therefore; Gate line G1, G5, G9 ... Be corresponding to first frequency CLK1; Gate line G2, G6, G10 ... Be corresponding to second frequency CLK2, gate line G3, G7, G11 ... Be corresponding to the 3rd frequency CLK3, with gate line G4, G8, G12 ... Be corresponding to the 4th frequency CLK4.

In sum, LCD and the method thereof that compensates gate voltage provided by the present invention is to utilize different gate high voltages, with the uneven problem of charge condition between a plurality of picture elements that overcome liquid crystal panel.Because it is little that the diversity ratio prior art of the charge condition between a plurality of picture elements of liquid crystal panel comes, so compared to prior art, the present invention can improve the quality of liquid crystal panel display frame.

The above is merely the present invention's preferred embodiment, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. the LCD that can compensate gate voltage is characterized in that, comprises:

One direct current voltage generation circuit, in order to produce one first gate high voltage, one second gate high voltage and one first gate low-voltage, wherein this first gate high voltage is to be higher than this second gate high voltage;

Time schedule controller is in order to produce one first a scanning start signal and a reference frequency;

One frequency generating circuit; Being coupled to this DC voltage produces between circuit and this time schedule controller; In order to according to this first gate high voltage, this second gate high voltage, this first gate low-voltage, this first scanning start signal and this reference frequency, produce and export one second scanning start signal, a first frequency, a second frequency, one the 3rd frequency, one the 4th frequency and this first gate low-voltage; And

One liquid crystal panel comprises:

A plurality of pixels; And

One gate drive circuit; Be coupled to this frequency generating circuit; This gate drive circuit comprises a plurality of gate drive unit; Wherein this a plurality of gate drive unit is in order to according to this second scanning start signal, this first frequency, this second frequency, the 3rd frequency, the 4th frequency and this first gate low-voltage, drives this a plurality of pixels, to improve the quality of this liquid crystal panel display frame; Wherein the phase place of the phase place of this first frequency and the 3rd frequency is opposite, and the phase place of the phase place of this second frequency and the 4th frequency is opposite;

Wherein the 4n+1 gate drive unit in this a plurality of gate drive unit is that the 4n+2 gate drive unit that receives in this first frequency, this a plurality of gate drive unit is that the 4n+3 gate drive unit that receives in this second frequency, this a plurality of gate drive unit is that the 4n+4 gate drive unit that receives in the 3rd frequency and this a plurality of gate drive unit is to receive the 4th frequency, and wherein n ≧ 0 and n are integer.

2. LCD according to claim 1 is characterized in that, wherein this DC voltage generation circuit, this time schedule controller and this frequency generating circuit are to be positioned on the printed circuit board (PCB).

3. LCD according to claim 1; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency and the 4th frequency is to be this second gate high voltage; The accurate position of the high voltage of this first frequency and the 3rd frequency is to be this first gate high voltage, and the accurate position of low-voltage of this first frequency, this second frequency, the 3rd frequency, the 4th frequency is to be this first gate low-voltage.

4. LCD according to claim 1 is characterized in that, wherein this DC voltage produces circuit and produces one second gate low-voltage in addition to this frequency generating circuit, and this first gate low-voltage is to be higher than this second gate low-voltage.

5. LCD according to claim 4; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency and the 4th frequency is to be this second gate high voltage; The accurate position of the high voltage of this first frequency and the 3rd frequency is to be this first gate high voltage, and the accurate position of the low-voltage of this second frequency and the 4th frequency is to be this second gate low-voltage, and the accurate position of the low-voltage of this first frequency and the 3rd frequency is to be this first gate low-voltage.

6. LCD according to claim 4; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency and the 4th frequency is to be this first gate high voltage; The accurate position of the high voltage of this first frequency and the 3rd frequency is to be this second gate high voltage, and the accurate position of the low-voltage of this second frequency and the 4th frequency is to be this first gate low-voltage, and the accurate position of the low-voltage of this first frequency and the 3rd frequency is to be this second gate low-voltage.

7. LCD according to claim 4; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency, the 3rd frequency and the 4th frequency is to be this second gate high voltage; The accurate position of the high voltage of this first frequency is to be this first gate high voltage, and the accurate position of the low-voltage of this second frequency, the 3rd frequency and the 4th frequency is to be this second gate low-voltage, and the accurate position of the low-voltage of this first frequency is to be this first gate low-voltage.

8. LCD according to claim 1 is characterized in that other comprises:

The one source pole driving circuit is when being used to be coupled to the thin film transistor (TFT) unlatching of a pixel, to this pixel charging.

9. a method that compensates the gate voltage of LCD is characterized in that, comprises:

One direct current voltage generation circuit produces one first gate high voltage, one second gate high voltage and one first gate low-voltage, and wherein this first gate high voltage is to be higher than this second gate high voltage;

Time schedule controller produces one first a scanning start signal and a reference frequency;

One frequency generating circuit produces and exports one second scanning start signal, a first frequency, a second frequency, one the 3rd frequency, one the 4th frequency and this first gate low-voltage according to this first gate high voltage, this second gate high voltage, this first gate low-voltage, this first scanning start signal and this reference frequency; And

According to this second scanning start signal, this first frequency, this second frequency, the 3rd frequency, the 4th frequency and this first gate low-voltage; Drive a plurality of pixels of a liquid crystal panel; To improve the quality of this liquid crystal panel display frame; Wherein the phase place of the phase place of this first frequency and the 3rd frequency is opposite, and the phase place of the phase place of this second frequency and the 4th frequency is opposite;

Wherein the 4n+1 gate drive unit in a plurality of gate drive unit of this liquid crystal panel is that the 4n+2 gate drive unit that receives in this first frequency, this a plurality of gate drive unit is that the 4n+3 gate drive unit that receives in this second frequency, this a plurality of gate drive unit is that the 4n+1 gate drive unit that receives in the 3rd frequency and this a plurality of gate drive unit is to receive the 4th frequency, and wherein n ≧ 0 and n are integer.

10. method according to claim 9; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency and the 4th frequency is to be this second gate high voltage; The accurate position of the high voltage of this first frequency and the 3rd frequency is to be this first gate high voltage, and the accurate position of low-voltage of this first frequency, this second frequency, the 3rd frequency, the 4th frequency is to be this first gate low-voltage.

11. method according to claim 9 is characterized in that, other comprises:

This DC voltage produces circuit and produces one second gate low-voltage to this frequency generating circuit, and this first gate low-voltage is to be higher than this second gate low-voltage.

12. method according to claim 11; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency and the 4th frequency is to be this second gate high voltage; The accurate position of the high voltage of this first frequency and the 3rd frequency is to be this first gate high voltage, and the accurate position of the low-voltage of this second frequency and the 4th frequency is to be this second gate low-voltage, and the accurate position of the low-voltage of this first frequency and the 3rd frequency is to be this first gate low-voltage.

13. method according to claim 11; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency and the 4th frequency is to be this first gate high voltage; The accurate position of the high voltage of this first frequency and the 3rd frequency is to be this second gate high voltage, and the accurate position of the low-voltage of this second frequency and the 4th frequency is to be this first gate low-voltage, and the accurate position of the low-voltage of this first frequency and the 3rd frequency is to be this second gate low-voltage.

14. method according to claim 11; It is characterized in that; Wherein the accurate position of the high voltage of this second frequency, the 3rd frequency and the 4th frequency is to be this second gate high voltage; The accurate position of the high voltage of this first frequency is to be this first gate high voltage, and the accurate position of the low-voltage of this second frequency, the 3rd frequency and the 4th frequency is to be this second gate low-voltage, and the accurate position of the low-voltage of this first frequency is to be this first gate low-voltage.