CN102214616B - Metal conductive structure and manufacturing method thereof - Google Patents
Metal conductive structure and manufacturing method thereof Download PDFInfo
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- CN102214616B CN102214616B CN201110141905.7A CN201110141905A CN102214616B CN 102214616 B CN102214616 B CN 102214616B CN 201110141905 A CN201110141905 A CN 201110141905A CN 102214616 B CN102214616 B CN 102214616B
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- Prior art keywords
- metal
- metallic conduction
- conduction structure
- groove
- oxidizing potential
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 205
- 239000002184 metal Substances 0.000 title claims abstract description 205
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims abstract description 9
- 229910052709 silver Inorganic materials 0.000 claims abstract description 3
- 239000004332 silver Substances 0.000 claims abstract description 3
- 230000001590 oxidative effect Effects 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 22
- 230000003139 buffering effect Effects 0.000 claims description 22
- 239000002245 particle Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 14
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 36
- 230000008878 coupling Effects 0.000 description 20
- 238000010168 coupling process Methods 0.000 description 20
- 238000005859 coupling reaction Methods 0.000 description 20
- 239000011521 glass Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000021615 conjugation Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Abstract
The invention discloses a metal conductive structure and a manufacturing method thereof. The metal conductive structure comprises a carrier, a first metal, a second metal and an insulating layer. The first metal and the second metal are sequentially arranged on the carrier. The oxidation potential of the first metal is greater than or equal to the oxidation potential of copper, and the oxidation potential of the second metal is less than or equal to the oxidation potential of silver. The insulating layer covers the side wall of the first metal, and the insulating layer contains an oxide of the first metal.
Description
Technical field
The present invention relates to a kind of metallic conduction structure and preparation method thereof, especially relate to a kind of metallic conduction structure that is used in glass flip chip (chip on glass, COG) technology and preparation method thereof.
Background technology
Glass flip chip (chip on glass, COG) technology refers to the technology that connection gasket chip is direct and on glass substrate engages, and because COG technology has advantage cheaply, the chip join that has therefore been widely used at present display floater is made.At present COG technology is mainly used anisotropic conductive (ACF), and by chip attach, on glass substrate, and the conducting particles of usining is wherein as the bridge that is electrically connected to of the connection gasket of the metal coupling on chip and glass substrate.
Please refer to Fig. 1, Fig. 1 be existing by the chip join with metal coupling to the schematic diagram with the glass substrate of connection gasket.As shown in Figure 1, on the weld pad 12 of chip 10, be formed with respectively a metal coupling 14, and metal coupling 14 is consisted of gold.And, on glass substrate 16, be formed with connection gasket 18, and the position of connection gasket 18 is the positions corresponding to weld pad 12.Carry out metal coupling 14 and connection gasket 18 engage manufacture craft time, first on glass substrate 16, be coated with anisotropic conductive 20, then by metal coupling 14, be to being positioned on corresponding connection gasket 18, and metal coupling 14 is pressed on downwards on connection gasket 18, make the conducting particles 22 in anisotropic conductive 20 can be electrically connected to metal coupling 14 and connection gasket 18.
Yet under the continuous situation promoting of density of configuration, the distance between the weld pad on chip is more and more less, and the spacing of metal coupling is also dwindled, and on glass substrate, the spacing of corresponding connection gasket also can be dwindled thereupon.Therefore, the conducting particles being present in anisotropic conductive can be more close each other because the spacing of metal coupling is dwindled, and makes conducting particles can be used as the electrical connection bridge of adjacent metal projection, and then cause the problem of metal coupling short circuit.And, on the connection gasket that metal coupling engages with institute wish, more there is certain bit errors, therefore after chip engages with glass substrate, the distance of metal coupling and adjacent connection gasket is less than the spacing of metal coupling especially, make the more easily bridge that is electrically connected to adjacent connection gasket as metal coupling of conducting particles, and cause short circuit problem.
In view of this, prevent from laterally linking the real target of making great efforts for industry of the short circuit problem causing because conducting particles in anisotropic conductive produces.
Summary of the invention
One of main purpose of the present invention is to provide a kind of metallic conduction structure and preparation method thereof, to solve because the conducting particles in anisotropic conductive produces, laterally links the short circuit problem being caused.
In order to achieve the above object, the invention provides a kind of metallic conduction structure.Metallic conduction structure comprises a carrier, a conductive layer, one first metal, one second metal and an insulating barrier.Conductive layer is positioned on carrier, and the first metal is located on conductive layer, and wherein the first metal has a upper surface and a sidewall, and the oxidizing potential of the first metal is more than or equal to the oxidizing potential of copper.The second metal is located at the upper surface of the first metal, and bimetallic oxidizing potential is less than or equal to silver-colored oxidizing potential.Insulating barrier covers the sidewall of the first metal, and insulating barrier includes the monoxide of the first metal.
In order to achieve the above object, the invention provides a kind of manufacture method of metallic conduction structure.First, form one first metal on a carrier, the first metal has a upper surface and a sidewall, and upper surface has a groove, and wherein the oxidizing potential of the first metal is more than or equal to the oxidizing potential of copper.Then, form one second metal in the upper surface of the first metal, and the second metal fills up groove, wherein bimetallic oxidizing potential is less than or equal to silver-colored oxidizing potential.Then, remove the second metal being positioned at outside groove.Subsequently, implement an oxidation step, with the sidewall in the first metal, form an insulating barrier.
The present invention first forms the first metal that oxidizing potential is more than or equal to the oxidizing potential of copper on conductive layer, before the first metal is not oxidized, form again the second metal that oxidizing potential is less than or equal to silver-colored oxidizing potential, make the second metal be connected to conductive layer by the first metal electric, the characteristic that can utilize the first metal to have easy oxidation forms insulating barrier in the exposed surface of the first metal simultaneously, to avoid in carrying out when chip engages manufacture craft with substrate causing short circuit because the conducting particles in anisotropic conductive produces laterally link.
Accompanying drawing explanation
Fig. 1 be existing by the chip join with metal coupling to the schematic diagram with the glass substrate of connection gasket;
Fig. 2 to Fig. 9 is the method schematic diagram that the present invention makes metal bump structure.
Main element symbol description
10 chip 12 weld pads
14 metal coupling 16 glass substrates
18 connection gasket 20 anisotropic conductives
22 conducting particles 100 metal bump structures
102 carrier 106 conductive layers
108 protective layer 108a the first perforation
110 buffering metal level 110a the first grooves
112 patterning photoresist 112a the second perforation
Agent layer
114 first metal 114a upper surfaces
114b sidewall 114c the second groove
116a, 116b the first metal layer 118 second metals
120 look edge layers
Embodiment
The present invention is mainly to carry out before a chip engages manufacture craft with a substrate, prior to making metallic conduction structure on chip or substrate, for being electrically connected to chip and substrate, and metallic conduction structure of the present invention can be avoided engaging with substrate in manufacture craft because the conducting particles in anisotropic conductive produces the short circuit problem that laterally link causes in carrying out chip.
Please refer to Fig. 2 to Fig. 9, Fig. 2 to Fig. 9 is the method schematic diagram that the present invention makes metallic conduction structure, the generalized section of the metallic conduction structure that wherein Fig. 9 is preferred embodiment of the present invention.As shown in Figure 2, first provide a carrier 102, and at least one conductive layer 106 and a protective layer 108 are positioned on carrier 102.Wherein, carrier can be substrate, electronic component or chip, but is not limited to this.And protective layer 108 is covered on carrier 102 and conductive layer 106, and protective layer 108 has one first perforation 108a, exposes partially conductive layer 106.Then, carry out a sputter manufacture craft, form a buffering metal level 110 on carrier 102, make to cushion metal level 110 and cover carrier 102, and insert in the first perforation 108a, to contact with conductive layer 106.It is worth mentioning that, buffering metal level 110 is evenly formed on carrier 102, and therefore, when buffering metal level 110 is covered on the protective layer 108 with the first perforation 108a, buffering metal level 110 can have one first groove 110a, corresponding the first perforation 108a.Wherein, the material of the conductive layer 106 of the present embodiment is conductive metallic material, for example: aluminium, and the material that forms buffering metal level 110 can be to be had good bond with conductive layer 106 but does not produce interactional electric conducting material with conductive layer 106, for example: titanium-tungsten (TiW), but be not limited to this.In addition, the method that the present invention forms buffering metal level 110 is not limited to use sputter manufacture craft, also can be electroless plating manufacture craft or other deposition manufacture crafts, but not as limit.
As shown in Figure 3, then carry out a photoetching and etching process, on buffering metal level 110, form a patterning photoresist layer 112, and patterning photoresist layer 112 has one second perforation 112a, make the second perforation 112a corresponding to the position of conductive layer 106, to expose the buffering metal level 110 contacting with conductive layer 106.Wherein, patterning photoresist layer 112 is consisted of photo anti-corrosion agent material, for example: positive photo anti-corrosion agent material or negative photoresist material.In addition, the size of the second perforation 112a is for defining the width of the metallic conduction structure 100 of the present embodiment, and follow-up formed metal is formed in the second perforation 112a, therefore the thickness of patterning photoresist layer 112 must be greater than the gross thickness of follow-up formed metal, and the thickness of patterning photoresist layer 112 can adjust according to the gross thickness of follow-up formed metal.
As shown in Figure 4, next on the buffering metal level 110 in the second perforation 112a, form one first metal 114, and the thickness of the first metal 114 is less than the thickness of patterning photoresist layer 112, make the first metal 114 only be arranged in the second perforation 112a, wherein the first metal 114 has a upper surface 114a and a sidewall 114b, and the first metal 114 is evenly formed on buffering metal level 110, make the upper surface 114a of the first metal 114 there is one second groove 114c along with the profile of the first groove 110a, and the second groove 114c position contact with sidewall 114b.And the oxidizing potential of the first metal 114 is more than or equal to the oxidizing potential of copper, make the first metal 114 belong to easy oxidation metal, for example: iron, copper, palladium, manganese, nickel or above-mentioned combination.In the present embodiment, the first metal 114 is consisted of two metal level 116a, 116b, and the step that forms the first metal 114 can include and carry out two electroplating manufacturing process, sequentially to form the first metal layer 116a, 116b on buffering metal level 110 respectively.Thus, the first metal 114 can be pair of lamina structure, and double-decker is the stacking of two kind of first metal 114.Yet the first metal 114 of the present invention is not limited to only be consisted of two the first metal layer 116a, 116b., in other embodiments of the invention, the first metal 114 can form (not shown) by single metal level, and only utilizes single electroplating manufacturing process to form single the first metal 114.Or, also can utilize and carry out a plurality of electroplating manufacturing process, to form the first metal 114 by a plurality of the first metal layer was formed, and each the first metal layer is consisted of different the first metals 114 respectively, making the first metal 114 is a sandwich construction, and sandwich construction is the stacking of multiple the first metal 114, but the present invention is not as limit.
It should be noted that, the present embodiment is before forming the first metal 114, prior to forming buffering metal level 110 on carrier 102, to block the first metal 114, diffuse to the conductive layer 106 on carrier 102, and pass through the conjugation of the first metal 114 and buffering metal level 110 higher than the conjugation with conductive layer 106, to promote the first metal 114, be incorporated into the adhesive force on carrier 102.Yet the present invention is not limited to palpiform and becomes buffering metal level 110.
As shown in Figure 5, then form one second metal 118 in the upper surface 114a of the first metal 114, and the second metal 118 fills up the second groove 114c.Wherein, the second metal 118 is not covered on patterning photoresist layer 112, and is only arranged in the second perforation 112a, makes the gross thickness of the first metal 114 and the second metal 118 be less than the thickness of patterning photoresist layer 112.In addition, the oxidizing potential of the second metal 118 is less than or equal to silver-colored oxidizing potential, makes the second metal 118 belong to not easy oxidation metal, for example: gold, platinum, silver or above-mentioned combination.In the present embodiment, the second metal 118 is consisted of single the second metal level, and the step that forms the second metal 118 can utilize an electroplating manufacturing process, but is not limited to this.
As shown in Figure 6, utilize subsequently an etching process, remove patterning photoresist layer 112, and expose not by the buffering metal level 110 of the first metal 114 and the second metal 118 coverings.As shown in Figure 7, then, take the first metal 114 and the second metal 118 is mask, removes not by the buffering metal level 110 of the first metal 114 and the second metal 118 coverings.
As shown in Figure 8, then, carry out a grinding manufacture craft (polishing process), to remove the second metal 118 being positioned at outside the second groove 114c, make the upper surface 114a exposing of the first metal 114 and the upper surface of the second metal 118 form a plane, to help being engaged on substrate.Now, the second metal 118 is only arranged in the second groove 114c, and therefore the second metal 118 does not contact with the sidewall 114b of the first metal 114.The present invention removes the second metal 118 being positioned at outside the second groove 114c and is not limited to grind manufacture craft, also can utilize photoetching and etching process to remove, but not as limit.
As shown in Figure 9, finally, implement an oxidation step, with the sidewall 114b in the first metal 114 and the upper surface 114a that not covered by the second metal 118, form an insulating barrier 120, make insulating barrier 120 not only be covered in the sidewall 114b of the first metal 114, more extend to the upper surface 114a that is positioned at the first metal 114 outside the second groove 114c, so far completed the metallic conduction structure 100 of the present embodiment.In the present embodiment, oxidation step can be placed in the carrier 102 that is formed with the first metal 114 and the second metal 118 under the environment of high temperature and high humidity, for example: 85 ℃ and relative humidity 85%, make to produce oxidation with the first metal 114 of environmental exposure, and form insulating barrier 120 in the exposed surface of the first metal 114.And insulating barrier 120 is formed by oxidation the first metal 114.Yet the method that the present invention forms insulating barrier 120 is not limited to be arranged at hot and humid environment, and only need to make the first metal 114 to react with oxygen, produces oxidation, can form insulating barrier 120.
The second metal 118 of being located on the first metal 114 of it should be noted that the present embodiment can't react with oxygen under hot and humid environment, therefore still can have conductive characteristic.Because the second groove 114c does not contact with the sidewall 114b of the first metal 114, therefore the second metal 118 can not contact with the sidewall 114b of the first metal 114 yet.And, insulating barrier 120 is reacted with oxygen and is formed by the first metal 114, make the exposed surface of the first metal 114 all have insulating barrier 120 coverings, and insulating barrier 120 effectively cover the sidewall 114b of the first metals 114 and the part upper surface 114a contacting with sidewall 114b.Therefore, engage in manufacture craft with substrate carrying out chip, while being formed with a plurality of the first metal 114 on carrier 102, each first metal 114 can be electrically insulated by insulating barrier 120 and the conducting particles that is positioned at the anisotropic conductive of one side, or each first metal 114 can be electrically insulated by insulating barrier 120 and adjacent conductive layer 106, and then solve because of the horizontal short circuit problem causing that links of the conducting particles generation in anisotropic conductive.
Separately it should be noted that, because current COG Manufacturing Techniques is to utilize the conducting particles of ACF and the metal coupling on chip pressing generation impression, in the present embodiment, if the second metal material character is soft compared with the material character of the conducting particles of ACF, Au for example, easily make the conducting particles of ACF be absorbed in Au metal coupling, cause impression partially light.For solving the partially light problem of impression, the thickness that can control the second metal is less than 80% of anisotropic conductive (ACF) particle diameter, ACF particle is being pressed on metal coupling produce to be greater than 20% impression of ACF particle diameter, and the hardness of controlling the first metal is greater than the hardness of ACF particle.
In sum, the present invention first forms the first oxidizable metal on carrier, before the first metal is not oxidized, form again the second not oxidizable metal, make the second metal be connected to conductive layer by the first metal electric, the characteristic that can utilize the first metal to have easy oxidation forms insulating barrier in the exposed surface of the first metal simultaneously, to avoid in carrying out when chip engages manufacture craft with substrate causing short circuit because the conducting particles in anisotropic conductive produces laterally link.Moreover, the upper surface of the first metal of the present invention has more the second groove not contacting with sidewall, the second metal can only be inserted in the second groove and and do not contact with sidewall, so insulating barrier more can effectively be electrically insulated two adjacent the second metals or be electrically insulated the second metal and adjacent conductive layer.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. a metallic conduction structure, comprises:
Carrier;
Conductive layer, is positioned on this carrier;
The first metal, is located on this conductive layer, and wherein this first metal has upper surface and sidewall, and the oxidizing potential of this first metal is more than or equal to the oxidizing potential of copper;
The second metal, be located at this upper surface of this first metal, and this bimetallic oxidizing potential is less than or equal to silver-colored oxidizing potential; And
Insulating barrier, covers this sidewall of this first metal, and this insulating barrier includes the monoxide of this first metal,
Wherein this upper surface of this first metal has a groove, and this second metal fills up this groove,
Wherein this second metal does not contact with the sidewall of this first metal.
2. metallic conduction structure as claimed in claim 1, wherein this insulating barrier extends to this upper surface that is positioned at this first metal outside this groove.
3. metallic conduction structure as claimed in claim 1, wherein this first metal is iron, copper, palladium, manganese, nickel or above-mentioned combination.
4. metallic conduction structure as claimed in claim 1, wherein this carrier comprises substrate or electronic component.
5. metallic conduction structure as claimed in claim 1, wherein this carrier comprises chip.
6. metallic conduction structure as claimed in claim 1, wherein this first metal is sandwich construction.
7. metallic conduction structure as claimed in claim 1, wherein this second metal is gold, platinum or silver.
8. metallic conduction structure as claimed in claim 1, wherein this bimetallic thickness is less than 80% of an anisotropic conductive (ACF) particle diameter.
9. metallic conduction structure as claimed in claim 1, wherein the hardness of this first metal is greater than the hardness of an anisotropic conductive (ACF) particle.
10. metallic conduction structure as claimed in claim 1, separately includes a buffering metal level, is located between this conductive layer and this first metal.
The manufacture method of 11. 1 kinds of metallic conduction structures, includes:
Form one first metal on a carrier, this first metal has upper surface and sidewall, and this upper surface has a groove, and wherein the oxidizing potential of this first metal is more than or equal to the oxidizing potential of copper;
Form one second metal on this first metal, and this second metal fills up this groove, wherein this bimetallic oxidizing potential is less than or equal to silver-colored oxidizing potential, and this second metal does not contact with the sidewall of this first metal;
Remove this second metal being positioned at outside this groove; And
Implement an oxidation step, so that this sidewall oxidation of this first metal forms an insulating barrier.
12. manufacture methods as claimed in claim 11, wherein removing this bimetallic step being positioned at outside this groove is to utilize a grinding manufacture craft.
13. manufacture methods as claimed in claim 11, the step that wherein forms this first metal is to utilize respectively an electroplating manufacturing process with forming this bimetallic step.
14. manufacture methods as claimed in claim 11, wherein, before forming the step of this first metal, this manufacture method separately includes:
On this carrier, form a buffering metal level; And
On this buffering metal level, form a patterning photoresist layer, and this patterning photoresist layer has a contact hole, expose this buffering metal level.
15. manufacture methods as claimed in claim 14, wherein in forming this bimetallic step and removing between this bimetallic step outside this groove, this manufacture method separately includes and removes this patterning photoresist layer.
16. manufacture methods as claimed in claim 15, wherein after removing the step of this patterning photoresist layer, this manufacture method separately includes and removes not by this first plated this buffering metal level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099147202A TWI423410B (en) | 2010-12-31 | 2010-12-31 | Metal conductive structure and manufacturing method |
| TW099147202 | 2010-12-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102214616A CN102214616A (en) | 2011-10-12 |
| CN102214616B true CN102214616B (en) | 2014-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110141905.7A Expired - Fee Related CN102214616B (en) | 2010-12-31 | 2011-05-30 | Metal conductive structure and manufacturing method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN102214616B (en) |
| TW (1) | TWI423410B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856221A (en) * | 2012-08-17 | 2013-01-02 | 江苏汇成光电有限公司 | Manufacturing process for IC (integrated circuit) packaging bump |
| JP7148300B2 (en) * | 2018-07-12 | 2022-10-05 | 上村工業株式会社 | Conductive Bump and Electroless Pt Plating Bath |
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| JP4115306B2 (en) * | 2003-03-13 | 2008-07-09 | 富士通株式会社 | Manufacturing method of semiconductor device |
| JP2007073617A (en) * | 2005-09-05 | 2007-03-22 | Tamura Seisakusho Co Ltd | Electrode structure, substrate for packaging, projection electrode, and manufacturing method thereof |
| TW200737456A (en) * | 2006-03-24 | 2007-10-01 | Phoenix Prec Technology Corp | Flip chip substrate structure and method for fabricating the same |
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| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| CN1161573A (en) * | 1995-11-14 | 1997-10-08 | 株式会社日立制作所 | Semiconductor IC device and method for mfg. same |
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Also Published As
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| TWI423410B (en) | 2014-01-11 |
| TW201227890A (en) | 2012-07-01 |
| CN102214616A (en) | 2011-10-12 |
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