CN102214616A - Metal conductive structure and manufacturing method thereof - Google Patents
Metal conductive structure and manufacturing method thereof Download PDFInfo
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- CN102214616A CN102214616A CN2011101419057A CN201110141905A CN102214616A CN 102214616 A CN102214616 A CN 102214616A CN 2011101419057 A CN2011101419057 A CN 2011101419057A CN 201110141905 A CN201110141905 A CN 201110141905A CN 102214616 A CN102214616 A CN 102214616A
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- groove
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 211
- 239000002184 metal Substances 0.000 title claims abstract description 211
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims abstract description 9
- 229910052709 silver Inorganic materials 0.000 claims abstract description 9
- 239000004332 silver Substances 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 23
- 230000003139 buffering effect Effects 0.000 claims description 23
- 239000002245 particle Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 36
- 230000008878 coupling Effects 0.000 description 20
- 238000010168 coupling process Methods 0.000 description 20
- 238000005859 coupling reaction Methods 0.000 description 20
- 239000011521 glass Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000021615 conjugation Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Abstract
The invention discloses a metal conductive structure and a manufacturing method thereof. The metal conductive structure comprises a carrier, a first metal, a second metal and an insulating layer. The first metal and the second metal are sequentially arranged on the carrier. The oxidation potential of the first metal is greater than or equal to the oxidation potential of copper, and the oxidation potential of the second metal is less than or equal to the oxidation potential of silver. The insulating layer covers the side wall of the first metal, and the insulating layer contains an oxide of the first metal.
Description
Technical field
The present invention relates to a kind of metallic conduction structure and preparation method thereof, especially relate to a kind of glass flip chip (chip on glass, COG) metallic conduction structure of technology and preparation method thereof of being used in.
Background technology
Glass flip chip (chip on glass, COG) technology is meant the technology that connection gasket chip is direct and on the glass substrate engages, and because the COG technology has advantage cheaply, the chip join that therefore has been widely used at present display floater is made.At present the COG technology is mainly used anisotropic conductive (ACF), with chip attach on glass substrate, and with wherein conducting particles the bridge that is electrically connected as the connection gasket of the metal coupling on the chip and glass substrate.
Please refer to Fig. 1, Fig. 1 will have the schematic diagram of the chip join of metal coupling to the glass substrate with connection gasket for existing.As shown in Figure 1, be formed with a metal coupling 14 on the weld pad 12 of chip 10 respectively, and metal coupling 14 is made of gold.And, be formed with connection gasket 18 on the glass substrate 16, and the position of connection gasket 18 is the positions corresponding to weld pad 12.Carry out metal coupling 14 and connection gasket 18 engage manufacture craft the time, on glass substrate 16, be coated with anisotropic conductive 20 earlier, be to being positioned on the corresponding connection gasket 18 then with metal coupling 14, and metal coupling 14 is pressed on downwards on the connection gasket 18, make the conducting particles 22 in the anisotropic conductive 20 can be electrically connected metal coupling 14 and connection gasket 18.
Yet under the continuous situation that promotes of the density of configuration, the distance between the weld pad on the chip is more and more littler, and the spacing of metal coupling is also dwindled thereupon, and the spacing of corresponding connection gasket also can be dwindled on the glass substrate.Therefore, the conducting particles that is present in the anisotropic conductive can be more close each other because the spacing of metal coupling is dwindled, and makes conducting particles can be used as the electrical connection bridge of adjacent metal projection, and then cause the metal coupling problem of short-circuit.And, more there is certain bit errors on metal coupling and the connection gasket that the institute desire engages, therefore in chip with after glass substrate engages, the distance of metal coupling and adjacent connection gasket is especially less than the spacing of metal coupling, make conducting particles easier, and cause short circuit problem as the bridge that is electrically connected of metal coupling with adjacent connection gasket.
In view of this, prevent from laterally to link the real target of making great efforts for industry of the short circuit problem that is caused because of the conducting particles in the anisotropic conductive produces.
Summary of the invention
One of main purpose of the present invention is to provide a kind of metallic conduction structure and preparation method thereof, laterally links the short circuit problem that is caused to solve because of the conducting particles in the anisotropic conductive produces.
In order to achieve the above object, the invention provides a kind of metallic conduction structure.Metallic conduction structure comprises a carrier, a conductive layer, one first metal, one second metal and an insulating barrier.Conductive layer is positioned on the carrier, and first metal is located on the conductive layer, and wherein first metal has a upper surface and a sidewall, and the oxidizing potential of first metal is more than or equal to the oxidizing potential of copper.Second metal is located at the upper surface of first metal, and the oxidizing potential of second metal is less than or equal to the oxidizing potential of silver.Insulating barrier covers the sidewall of first metal, and insulating barrier includes the monoxide of first metal.
In order to achieve the above object, the invention provides a kind of manufacture method of metallic conduction structure.At first, form one first metal on a carrier, first metal has a upper surface and a sidewall, and upper surface has a groove, and wherein the oxidizing potential of first metal is more than or equal to the oxidizing potential of copper.Then, form one second metal in the upper surface of first metal, and second metal fills up groove, wherein the oxidizing potential of second metal is less than or equal to the oxidizing potential of silver.Then, remove second metal that is positioned at outside the groove.Subsequently, implement an oxidation step, form an insulating barrier with sidewall in first metal.
The present invention forms first metal of oxidizing potential more than or equal to the oxidizing potential of copper earlier on conductive layer, before first metal is not oxidized, form second metal that oxidizing potential is less than or equal to the oxidizing potential of silver again, make second metal be electrically connected to conductive layer by first metal, the characteristic that can utilize simultaneously first metal to have easy oxidation forms insulating barrier in the exposed surface of first metal, to avoid causing short circuit because of the conducting particles in the anisotropic conductive produces horizontal binding in carrying out chip when engaging manufacture craft with substrate.
Description of drawings
Fig. 1 will have the schematic diagram of the chip join of metal coupling to the glass substrate with connection gasket for existing;
Fig. 2 to Fig. 9 makes the method schematic diagram of metal bump structure for the present invention.
The main element symbol description
10 chips, 12 weld pads
14 metal couplings, 16 glass substrates
18 connection gaskets, 20 anisotropic conductives
22 conducting particless, 100 metal bump structures
102 carriers, 106 conductive layers
108 protective layer 108a, first perforation
110 buffering metal level 110a, first groove
112 patterning photoresist 112a, second perforation
The agent layer
114 first metal 114a upper surfaces
116a, 116b the first metal layer 118 second metals
120 look edge layers
Embodiment
Before the present invention mainly is to carry out a chip and a substrate engages manufacture craft, prior to making metallic conduction structure on chip or the substrate, being used to being electrically connected chip and substrate, and metallic conduction structure of the present invention can be avoided engaging with substrate in the manufacture craft and laterally linking the short circuit problem that is caused because of the conducting particles in the anisotropic conductive produces in carrying out chip.
Please refer to Fig. 2 to Fig. 9, Fig. 2 to Fig. 9 makes the method schematic diagram of metallic conduction structure for the present invention, and wherein Fig. 9 is the generalized section of the metallic conduction structure of preferred embodiment of the present invention.As shown in Figure 2, at first provide a carrier 102, and at least one conductive layer 106 and a protective layer 108 are positioned on the carrier 102.Wherein, carrier can be substrate, electronic component or chip, but is not limited thereto.And protective layer 108 is covered on carrier 102 and the conductive layer 106, and protective layer 108 has one first perforation 108a, exposes partially conductive layer 106.Then, carry out a sputter manufacture craft, form a buffering metal level 110 on carrier 102, make buffering metal level 110 cover carrier 102, and insert among the first perforation 108a, to contact with conductive layer 106.What deserves to be mentioned is that buffering metal level 110 evenly is formed on the carrier 102, therefore when buffering metal level 110 was covered on the protective layer 108 with first perforation 108a, buffering metal level 110 can have one first groove 110a, the corresponding first perforation 108a.Wherein, the material of the conductive layer 106 of present embodiment is a conductive metallic material, for example: and aluminium, and the material that forms buffering metal level 110 can be and has good bond with conductive layer 106 but do not produce interactional electric conducting material with conductive layer 106, for example: titanium-tungsten (TiW), but be not limited thereto.In addition, the method that the present invention forms buffering metal level 110 is not limited to use the sputter manufacture craft, also can be electroless plating manufacture craft or other deposition manufacture crafts, but not as limit.
As shown in Figure 3, then carry out a photoetching and etching process, on buffering metal level 110, form a patterning photoresist layer 112, and patterning photoresist layer 112 has one second perforation 112a, make the position of the second perforation 112a, to expose the buffering metal level 110 that contacts with conductive layer 106 corresponding to conductive layer 106.Wherein, patterning photoresist layer 112 is made of photo anti-corrosion agent material, for example: positive photo anti-corrosion agent material or negative photoresist material.In addition, the size of the second perforation 112a is used to define the width of the metallic conduction structure 100 of present embodiment, and follow-up formed metal is formed among the second perforation 112a, therefore the thickness of patterning photoresist layer 112 must be greater than the gross thickness of follow-up formed metal, and the thickness of patterning photoresist layer 112 can adjust according to the gross thickness of follow-up formed metal.
As shown in Figure 4, next form one first metal 114 on the buffering metal level 110 in the second perforation 112a, and the thickness of first metal 114 is less than the thickness of patterning photoresist layer 112, make first metal 114 only be arranged in the second perforation 112a, wherein first metal 114 has a upper surface 114a and a sidewall 114b, and first metal 114 evenly is formed on the buffering metal level 110, make the upper surface 114a of first metal 114 have one second groove 114c, and the second groove 114c position contact with sidewall 114b along with the profile of the first groove 110a.And the oxidizing potential of first metal 114 makes first metal 114 belong to easy oxidation metal, for example: iron, copper, palladium, manganese, nickel or above-mentioned combination more than or equal to the oxidizing potential of copper.In the present embodiment, first metal 114 is made of two metal level 116a, 116b, and the step that forms first metal 114 can include and carry out two and electroplate manufacture crafts, to form the first metal layer 116a, 116b in regular turn on buffering metal level 110 respectively.Thus, first metal 114 can be the pair of lamina structure, and double-decker is piling up of two kind of first metal 114.Yet first metal 114 of the present invention is not limited to only be made of two the first metal layer 116a, 116b., in other embodiments of the invention, first metal 114 can be made of (figure does not show) single metal level, and only utilizes single plating manufacture craft to form single first metal 114.Perhaps, also can utilize and carry out a plurality of plating manufacture crafts, to form first metal 114 by a plurality of the first metal layer was constituted, and each the first metal layer is made of different first metals 114 respectively, making first metal 114 is a sandwich construction, and sandwich construction is piling up of multiple first metal 114, but the present invention is not as limit.
It should be noted that, present embodiment is before forming first metal 114, prior to forming buffering metal level 110 on the carrier 102, diffuse to conductive layer 106 on the carrier 102 to block first metal 114, and the conjugation by first metal 114 and buffering metal level 110 is higher than the conjugation with conductive layer 106, is incorporated into adhesive force on the carrier 102 to promote first metal 114.Yet the present invention is not limited to palpiform and becomes buffering metal level 110.
As shown in Figure 5, form the upper surface 114a of one second metal 118 then, and second metal 118 fills up the second groove 114c in first metal 114.Wherein, second metal 118 is not covered on the patterning photoresist layer 112, and only is arranged in the second perforation 112a, makes the thickness of the gross thickness of first metal 114 and second metal 118 less than patterning photoresist layer 112.In addition, the oxidizing potential of second metal 118 is less than or equal to the oxidizing potential of silver, makes second metal 118 belong to not easy oxidation metal, for example: gold, platinum, silver or above-mentioned combination.In the present embodiment, second metal 118 is made of single second metal level, and the step that forms second metal 118 can utilize one to electroplate manufacture craft, but is not limited thereto.
As shown in Figure 6, utilize an etching process subsequently, remove patterning photoresist layer 112, and expose not by the buffering metal level 110 of first metal 114 and 118 coverings of second metal.As shown in Figure 7, then, be mask with first metal 114 and second metal 118, remove not by the buffering metal level 110 of first metal 114 and 118 coverings of second metal.
As shown in Figure 8, then, carry out one and grind manufacture craft (polishing process), be positioned at the second outer metal 118 of the second groove 114c to remove, make the upper surface 114a that exposes of first metal 114 and the upper surface of second metal 118 constitute a plane, to help being engaged on the substrate.At this moment, second metal 118 only is arranged in the second groove 114c, and therefore second metal 118 does not contact with the sidewall 114b of first metal 114.The present invention removes second metal 118 that is positioned at outside the second groove 114c and is not limited to grind manufacture craft, also can utilize photoetching and etching process to remove, but not as limit.
As shown in Figure 9, at last, implement an oxidation step, form an insulating barrier 120 with sidewall 114b with the upper surface 114a that not covered by second metal 118 in first metal 114, make insulating barrier 120 not only be covered in the sidewall 114b of first metal 114, more extend to the upper surface 114a that is positioned at the first outer metal 114 of the second groove 114c, so far promptly finished the metallic conduction structure 100 of present embodiment.In the present embodiment, oxidation step can be placed in the carrier 102 that is formed with first metal 114 and second metal 118 under the environment of high temperature and high humidity, for example: 85 ℃ and relative humidity 85%, make first metal 114 that contacts with environment produce oxidation, and form insulating barrier 120 in the exposed surface of first metal 114.And insulating barrier 120 is formed by oxidation first metal 114.Yet the method that the present invention forms insulating barrier 120 is not limited to be arranged at hot and humid environment, and only need make first metal 114 and oxygen reaction produce oxidation, can form insulating barrier 120.
Second metal of being located on first metal 114 118 that it should be noted that present embodiment can't descend and the oxygen reaction in hot and humid environment, therefore still can have conductive characteristic.Because the second groove 114c does not contact with the sidewall 114b of first metal 114, therefore second metal 118 can not contact with the sidewall 114b of first metal 114 yet.And, insulating barrier 120 is formed with the oxygen reaction by first metal 114, make the exposed surface of first metal 114 all have insulating barrier 120 and cover, and insulating barrier 120 effectively cover first metals 114 sidewall 114b and with the contacted part upper surface of sidewall 114b 114a.Therefore, engage in the manufacture craft with substrate carrying out chip, when being formed with a plurality of first metal 114 on the carrier 102, each first metal 114 can be electrically insulated by insulating barrier 120 and the conducting particles that is positioned at the anisotropic conductive of one side, perhaps each first metal 114 can be electrically insulated by insulating barrier 120 and adjacent conductive layer 106, and then solves because of the horizontal short circuit problem that is caused that links of the generation of the conducting particles in the anisotropic conductive.
Other it should be noted that, because COG manufacture craft technology is to utilize the conducting particles of ACF and the metal coupling on the chip pressing the generation impression at present, in present embodiment, if the second metal material character is soft than the material character of the conducting particles of ACF, Au for example, the conducting particles of ACF is absorbed in the Au metal coupling, causes impression light partially.For solving the light partially problem of impression, the thickness of may command second metal is less than 80% of anisotropic conductive (ACF) particle diameter, the ACF particle is being pressed produce 20% impression on metal coupling, and control the hardness of the hardness of first metal greater than the ACF particle greater than the ACF particle diameter.
In sum, the present invention forms first metal of easy oxidation earlier on carrier, before first metal is not oxidized, form second metal that is difficult for oxidation again, make second metal be electrically connected to conductive layer by first metal, the characteristic that can utilize simultaneously first metal to have easy oxidation forms insulating barrier in the exposed surface of first metal, to avoid causing short circuit because of the conducting particles in the anisotropic conductive produces horizontal binding in carrying out chip when engaging manufacture craft with substrate.Moreover, the upper surface of first metal of the present invention has more not and contacted second groove of sidewall, second metal can only be inserted in second groove and not contact with sidewall, so insulating barrier two adjacent second metal or be electrically insulated second metal and the adjacent conductive layers that more can effectively be electrically insulated.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. metallic conduction structure comprises:
Carrier;
Conductive layer is positioned on this carrier;
First metal is located on this conductive layer, and wherein this first metal has upper surface and sidewall, and the oxidizing potential of this first metal is more than or equal to the oxidizing potential of copper;
Second metal is located at this upper surface of this first metal, and the oxidizing potential of this second metal is less than or equal to the oxidizing potential of silver; And
Insulating barrier cover this sidewall of this first metal, and this insulating barrier includes the monoxide of this first metal.
2. metallic conduction structure as claimed in claim 1, wherein this upper surface of this first metal has a groove, and this second metal fills up this groove.
3. metallic conduction structure as claimed in claim 2, wherein this insulating barrier extends to this upper surface that is positioned at this outer first metal of this groove.
4. metallic conduction structure as claimed in claim 1, wherein this first metal comprises iron, copper, palladium, manganese, nickel or above-mentioned combination.
5. metallic conduction structure as claimed in claim 1, wherein this carrier comprises substrate, electronic component or chip.
6. metallic conduction structure as claimed in claim 1, wherein this first metal is a sandwich construction.
7. metallic conduction structure as claimed in claim 1, wherein this second metal comprises gold, platinum or silver.
8. metallic conduction structure as claimed in claim 1, wherein the thickness of this second metal is less than 80% of an anisotropic conductive (ACF) particle diameter.
9. metallic conduction structure as claimed in claim 1, wherein the hardness of this first metal is greater than the hardness of an anisotropic conductive (ACF) particle.
10. metallic conduction structure as claimed in claim 1, other includes a buffering metal level, is located between this conductive layer and this first metal.
11. the manufacture method of a metallic conduction structure includes:
Form one first metal on a carrier, this first metal has upper surface and sidewall, and this upper surface has a groove, and wherein the oxidizing potential of this first metal is more than or equal to the oxidizing potential of copper;
Form one second metal on this first metal, and this second metal fills up this groove, wherein the oxidizing potential of this second metal is less than or equal to the oxidizing potential of silver;
Remove and be positioned at this outer second metal of this groove; And
Implement an oxidation step, form an insulating barrier with this sidewall in this first metal.
12. manufacture method as claimed in claim 11, wherein this insulating barrier is formed by this first metal of oxidation.
13. manufacture method as claimed in claim 11, wherein removing the step that is positioned at this outer second metal of this groove is to utilize one to grind manufacture craft.
14. manufacture method as claimed in claim 11, the step that wherein forms this first metal is to utilize one to electroplate manufacture craft respectively with the step that forms this second metal.
15. manufacture method as claimed in claim 11, wherein before the step that forms this first metal, this manufacture method includes in addition:
On this carrier, form a buffering metal level; And
On this buffering metal level, form a patterning photoresist layer, and this patterning photoresist layer has a contact hole, expose this buffering metal level.
16. manufacture method as claimed in claim 15, wherein in the step that forms this second metal and remove between the step of this second metal outside this groove, this manufacture method includes in addition and removes this patterning photoresist layer.
17. manufacture method as claimed in claim 16, wherein after the step that removes this patterning photoresist layer, this manufacture method includes in addition and removes not by this first plated this buffering metal level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099147202A TWI423410B (en) | 2010-12-31 | 2010-12-31 | Metal conductive structure and manufacturing method |
| TW099147202 | 2010-12-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102214616A true CN102214616A (en) | 2011-10-12 |
| CN102214616B CN102214616B (en) | 2014-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110141905.7A Expired - Fee Related CN102214616B (en) | 2010-12-31 | 2011-05-30 | Metal conductive structure and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102214616B (en) |
| TW (1) | TWI423410B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856221A (en) * | 2012-08-17 | 2013-01-02 | 江苏汇成光电有限公司 | Manufacturing process for IC (integrated circuit) packaging bump |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7148300B2 (en) * | 2018-07-12 | 2022-10-05 | 上村工業株式会社 | Conductive Bump and Electroless Pt Plating Bath |
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| JP2007073617A (en) * | 2005-09-05 | 2007-03-22 | Tamura Seisakusho Co Ltd | Electrode structure, substrate for packaging, projection electrode, and manufacturing method thereof |
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- 2010-12-31 TW TW099147202A patent/TWI423410B/en not_active IP Right Cessation
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| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| CN1161573A (en) * | 1995-11-14 | 1997-10-08 | 株式会社日立制作所 | Semiconductor IC device and method for mfg. same |
| CN1344017A (en) * | 2000-09-18 | 2002-04-10 | 联友光电股份有限公司 | Structure with several convex and blocks having insulating side walls and its making method |
| US20040180527A1 (en) * | 2003-03-13 | 2004-09-16 | Fujitsu Limited | Method of manufacturing semiconductor device |
| CN1930672A (en) * | 2004-03-29 | 2007-03-14 | 英特尔公司 | Under bump metallization layer to enable use of high tin content solder bumps |
| CN101290917A (en) * | 2007-04-17 | 2008-10-22 | 南亚电路板股份有限公司 | Structure of welding mat |
| CN101779526A (en) * | 2007-08-10 | 2010-07-14 | 夏普株式会社 | Wiring board and liquid crystal display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856221A (en) * | 2012-08-17 | 2013-01-02 | 江苏汇成光电有限公司 | Manufacturing process for IC (integrated circuit) packaging bump |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI423410B (en) | 2014-01-11 |
| TW201227890A (en) | 2012-07-01 |
| CN102214616B (en) | 2014-07-30 |
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