CN101984506A - Method for preparing thin film transistor by two-time photo-etching - Google Patents
Method for preparing thin film transistor by two-time photo-etching Download PDFInfo
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- CN101984506A CN101984506A CN 201010504099 CN201010504099A CN101984506A CN 101984506 A CN101984506 A CN 101984506A CN 201010504099 CN201010504099 CN 201010504099 CN 201010504099 A CN201010504099 A CN 201010504099A CN 101984506 A CN101984506 A CN 101984506A
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Abstract
The invention provides a method for preparing a thin film transistor by two-time photo-etching, and belongs to semiconductor technology and flat display field. The method comprises the following steps of: growing a semiconductor channel layer on a glass or plastic substrate; then growing a grid insulating dielectric layer; performing first photo-etching and etching to define patterns of the grid insulating dielectric layer; and growing a layer of conductive thin film material, and forming a grid electrode, a source electrode and a drain electrode by photo-etching and etching. The method for preparing the thin film transistor by two-time photo-etching technology reduces the photo-etching times, and simplifies the processes so as to improve the work efficiency and reduce the manufacturing cost. The invention provides the simple, convenient and feasible thin film transistor preparing method for the industries of liquid crystal display and the like.
Description
Technical field
The present invention relates to the manufacture method that a kind of secondary photoetching realizes thin-film transistor structure, belong to semiconductor technology flat panel display field.
Background technology
Along with the develop rapidly of semiconductor technology, the integrated level of semiconductor device is more and more higher, and the characteristic size of device is more and more littler, and preparation technology also becomes increasingly complex.In recent years, be applicable to that the thin-film transistor technologies of flat panel display industry is also in fast development.Thin-film transistor is one of kind of field-effect transistor, and main production method is the various film of deposition on substrate, as the metal or the compound electrode layer of semiconductor channel layer, gate insulation dielectric layer and conduction.Thin-film transistor is that deposition layer of semiconductor film is regarded conductivity channel layer on substrate.The thin-film transistor major part of using is amorphous silicon hydride (a-Si:H) thin-film transistor at present, and the polycrystalline SiTFT technology is also among constantly improving.The performance of amorphous silicon film transistor is more stable, but mobility is low.The mobility of polycrystalline SiTFT improves a lot, but the preparation temperature height of polycrystalline SiTFT, the lack of homogeneity of large-area preparation.In addition, amorphous silicon film transistor and polycrystalline SiTFT are all to photaesthesia, and great changes will take place for device performance under the illumination condition, therefore, need to introduce black matrix in flat panel display, this complexity that has also increased preparation technology has reduced the aperture opening ratio of display device simultaneously.In order further to improve the performance of thin-film transistor, solve problems such as black matrix, aperture opening ratio, brightness, the international semiconductor technical field has started the research boom of transparent electronics in recent years.Transparent electronics is exactly to utilize transparent electronic material to make a kind of semiconductor technology of electronic device and interlock circuit thereof.A collection of researchers such as the John Wager of Oregon State University have also carried out deep research to transparent electronics, and have obtained some progress.At present to the transparent semiconductor investigation of materials more be zinc oxide material.Zinc oxide material has lot of advantages: be easy to preparation, utilize methods such as magnetron sputtering method, molecular beam epitaxy (MBE) method, sol-gel (Sol-Gel) method, MOCVD method can prepare well behaved zinc oxide material; Preparation temperature is low, and the temperature of general preparation can be controlled at 500
oIn the C, on glass substrate; Transparency height, zinc oxide are wide-band gap materials, and energy gap is about 3.37eV, are transparent in visible-range therefore; Electric property is good, and the electric property of zinc oxide material is good, and carrier mobility is far above amorphous silicon; Nontoxic, environment-friendly materials, zinc oxide material are a kind of nontoxic environment-friendly materials; Material price is low, and Zinc material is aboundresources on earth, and is cheap, can reduce the manufacturing cost of product effectively.Scientists is thought, transparent electronics will develop into an emerging electron trade that efficient is higher, price is more cheap, its range of application is quite extensive, comprises from the flat-panel monitor to the solar cell, many-sided field such as mobile phone, flexible electronic paper, organic light emitting display.
The current thin film transistor technology mainly adopts photoetching process five times, and photoetching process is also arranged four times.Photoetching process is the key technology in the thin-film transistor technology, is one of difficult point in the whole preparation process, and the photoetching process complexity is directly connected to the manufacturing cost of thin-film transistor.
Summary of the invention
The object of the present invention is to provide a kind of preparation method of new thin-film transistor.Utilize the secondary photoetching to realize thin-film transistor structure.The gate insulation dielectric layer of the first lithographic definition thin-film transistor, photoetching for the second time defines grid, source end and drain terminal electrode simultaneously.This method will reduce the complexity of prepared greatly, improve make efficiency effectively, thereby reduce the manufacturing cost of thin-film transistor.
Technical scheme of the present invention is as follows:
The structure of the thin-film transistor of the present invention's preparation comprises substrate, gate insulation dielectric layer, gate electrode and source-drain electrode as shown in Figure 1, is formed on the substrate, and substrate is glass or plastics; Described semiconductor channel layer is positioned on the glass substrate, and described gate insulation dielectric layer is positioned on the semiconductor channel layer, and described gate electrode is positioned on the gate medium.Described source-drain electrode is positioned on the semiconductor channel layer.
The technical process that the present invention prepares thin-film transistor only adopts Twi-lithography, specifically may further comprise the steps:
(1) growth layer of semiconductor channel layer on glass or plastic at first, semiconductor channel layer is formed by amorphous silicon, polysilicon or compound semiconductor materials;
(2) growth one deck gate insulation dielectric layer, the gate insulation dielectric layer is formed by silicon dioxide, silicon nitride or high-K gate dielectric insulating material;
(3) carry out the photoetching first time and etching definition gate insulation dielectric layer figure then;
(4) growth layer of conductive film material is formed by metal A l, Cu, Mo, Ti or transparent compound conductive film material, and photoetching and etching form gate electrode, source termination electrode and drain terminal electrode then.
The present invention adopts the secondary photoetching to form the technology of thin-film transistor, has reduced the photoetching number of times, has simplified processing step, thereby has improved operating efficiency, has reduced manufacturing cost.For industries such as liquid crystal display provide simple and feasible film crystal tube preparation method.
Description of drawings
Fig. 1 is the cross-sectional view that the described secondary photoetching of the specific embodiment of the invention forms thin-film transistor;
Fig. 2 is the plan structure schematic diagram that the described secondary photoetching of the specific embodiment of the invention forms thin-film transistor;
Fig. 3 is the main technique step of a manufacture method of thin-film transistor of the present invention, wherein:
Fig. 3 (a) has illustrated the sectional view of substrate;
Fig. 3 (b) has illustrated the processing step that the semiconductor conductivity channel layer forms;
Fig. 3 (c) has illustrated the processing step of gate insulation dielectric layer growth;
Fig. 3 (d) has illustrated grid, source, drain electrode layer deposit and patterned processing step.
Embodiment
The present invention will be further described below by example.It should be noted that the purpose of publicizing and implementing example is to help further to understand the present invention, but it will be appreciated by those skilled in the art that: in the spirit and scope that do not break away from the present invention and claims, various substitutions and modifications all are possible.Therefore, the present invention should not be limited to the disclosed content of embodiment, and the scope of protection of present invention is as the criterion with the scope that claims define.
Thin-film transistor of the present invention is formed on the substrate 1, as depicted in figs. 1 and 2.This thin-film transistor comprises semiconductor conductivity channel layer 2, one gate insulation dielectric layers, 3, one gate electrodes (G) 4, a source termination electrode (S) 4 and a drain terminal electrode (D) 4.Described semiconductor conductivity channel layer 2 is positioned on the glass substrate 1, described gate insulation dielectric layer 3 is positioned on the semiconductor conductivity channel layer 2, described gate electrode (G) 4 is positioned on the gate insulation dielectric layer 3, and described source termination electrode (S) 4 and drain terminal electrode (D) 5 are positioned on the semiconductor conductivity channel layer 2.
One instantiation of the manufacture method of described thin-film transistor, be may further comprise the steps to shown in Fig. 3 (d) by Fig. 3 (a):
Shown in Fig. 3 (a), substrate is selected transparent glass substrate or plastics 1 for use.
Shown in Fig. 3 (b), with the layers of semiconductor thin-film materials 2 of rf magnetron sputtering deposit one deck 50～500 nanometer thickness, semiconductor channel layer is formed by amorphous silicon, polysilicon or compound semiconductor materials.
Shown in Fig. 3 (c), utilize PECVD on semiconductor channel layer, grow layer of silicon dioxide or insulating silicon nitride material, the gate insulation dielectric layer 3 of formation, photoetching and etching form gate insulation medium figure then.
Shown in Fig. 3 (d), the metal film of magnetron sputtering growth one deck 100～200 nanometer thickness or transparent compound conductive layer be photoetching and etching formation gate electrode (G) 4, source termination electrode (S) 5 and drain terminal electrode D (5) then.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1. the preparation method of a thin-film transistor, its step comprises:
1) growth layer of semiconductor channel layer on glass or plastic;
2) growth one deck gate insulation dielectric layer;
3) carry out the photoetching first time and etching definition gate insulation dielectric layer figure;
4) growth layer of conductive film material, photoetching and etching form gate electrode, source termination electrode and drain terminal electrode then.
2. the method for claim 1 is characterized in that, semiconductor channel layer is formed by amorphous silicon, polysilicon or semiconductive thin film.
3. the method for claim 1 is characterized in that, the gate insulation dielectric layer adopts silicon dioxide, silicon nitride or high-K gate dielectric insulating material.
4. the method for claim 1 is characterized in that, conductive film material is metal A l, Cu, Mo, Ti or transparent compound conductive film.
5. method as claimed in claim 2 is characterized in that, with the semiconductive thin film of rf magnetron sputtering deposit 50～500 nanometer thickness.
6. method as claimed in claim 3 is characterized in that, utilizes PECVD growth layer of silicon dioxide or insulating silicon nitride material.
7. method as claimed in claim 4 is characterized in that, the metal or the transparent compound conductive film of magnetron sputtering growth one deck 100～200 nanometer thickness.
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| CN2010105040990A CN101984506B (en) | 2010-10-12 | 2010-10-12 | Method for preparing thin film transistor by two-time photo-etching |
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| CN2010105040990A CN101984506B (en) | 2010-10-12 | 2010-10-12 | Method for preparing thin film transistor by two-time photo-etching |
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| CN101984506A true CN101984506A (en) | 2011-03-09 |
| CN101984506B CN101984506B (en) | 2012-07-04 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102629621A (en) * | 2012-01-09 | 2012-08-08 | 京东方科技集团股份有限公司 | Circuit, array substrate and manufacturing method thereof, and display |
| CN102981359A (en) * | 2012-11-28 | 2013-03-20 | 中国科学院苏州纳米技术与纳米仿生研究所 | Photoetching method |
| CN106229320A (en) * | 2016-09-06 | 2016-12-14 | 武汉华星光电技术有限公司 | The manufacture method of LTPS array base palte |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413790B1 (en) * | 1999-07-21 | 2002-07-02 | E Ink Corporation | Preferred methods for producing electrical circuit elements used to control an electronic display |
| CN101000916A (en) * | 2007-01-04 | 2007-07-18 | 京东方科技集团股份有限公司 | TFI array structure and manufacturing method thereof |
| CN100449391C (en) * | 2006-08-04 | 2009-01-07 | 北京京东方光电科技有限公司 | Thin-film transistor LCD pixel structure and manufacturing method therefor |
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2010
- 2010-10-12 CN CN2010105040990A patent/CN101984506B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413790B1 (en) * | 1999-07-21 | 2002-07-02 | E Ink Corporation | Preferred methods for producing electrical circuit elements used to control an electronic display |
| CN100449391C (en) * | 2006-08-04 | 2009-01-07 | 北京京东方光电科技有限公司 | Thin-film transistor LCD pixel structure and manufacturing method therefor |
| CN101000916A (en) * | 2007-01-04 | 2007-07-18 | 京东方科技集团股份有限公司 | TFI array structure and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102629621A (en) * | 2012-01-09 | 2012-08-08 | 京东方科技集团股份有限公司 | Circuit, array substrate and manufacturing method thereof, and display |
| CN102981359A (en) * | 2012-11-28 | 2013-03-20 | 中国科学院苏州纳米技术与纳米仿生研究所 | Photoetching method |
| CN106229320A (en) * | 2016-09-06 | 2016-12-14 | 武汉华星光电技术有限公司 | The manufacture method of LTPS array base palte |
| CN106229320B (en) * | 2016-09-06 | 2019-04-05 | 武汉华星光电技术有限公司 | The manufacturing method of LTPS array substrate |
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| CN101984506B (en) | 2012-07-04 |
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