CN101867469B - Realization method of precision synchronous clock - Google Patents
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Abstract
The invention discloses a realization method of a precision synchronous clock and aims at providing a transmission method of a precision synchronous clock in a measuring and automatic system based on an industrial Ethernet. The essential points of the technical scheme of the invention are that the realizing method comprises a frequency and deviation adjusting algorithm based on a fuzzy PID (Proportion Integration Differentiation), a quick internal clock synchronous algorithm, a real-time synchronous check method and a real-time clock frequency and time deviation adjusting algorithm. The invention has the following applications that the method can be used for realizing quick switch of the clock, can be applied to a high-reliability redundant clock source system and can finish the switch of the clock in ten seconds; the transmission precision of a single-stage clock can reach 50ns level; and since the algorithm can be used for realizing the quick switch of the clock, the algorithm is also applied to a high-reliability clock synchronous system under a redundant loop net and the clock HOLDOVER function on terminal equipment is degraded. The invention achieves the functions of software for receiving and transmitting a precision synchronous clock protocol message and adjusting and calibrating a system clock.
Description
Technical field
The present invention relates to field of network communication, more particularly, relate to the transmission method based on Industrial Ethernet precise synchronization clock in measurement and automated system.
Background technology
The synchronous protocol that precise synchronization clock is usually used in Ethernet TCP/IP network with other is compared as SNTP or NTP, main difference is: precise synchronization clock is for more stable and safer Environment Design, so more simple, the network taking and computational resource are also still less, in addition, due to precision interval clock employing is that hardware hardware is beaten markers, can accurately measure the message residence time of switch and the link delay between switch, its synchronization accuracy is higher, in the wonderful level of sub-micro, and the stability of synchronization accuracy is also higher.
Precise synchronization clock mainly in relatively localization, networking system, subnet is better, intraware is relatively stable, is particularly suitable for industrial automation and measurement environment.Different from precise synchronization clock, Network Time Protocol is aimed at the security descriptor of extensive dispersion each autonomous system on the internet.GPS (satellite-based global positioning system) is also aimed at dispersion extensively and system independently separately.
Network Time Protocol will obtain good precision, will adopt a lot of algorithms, and requires there are many NTP Server, and this realization for control system and control terminal has sizable difficulty.
The network configuration of precise synchronization clock definition can make the precision that self reaches very high, and the network path of setting redundancy enters the unactivated state of precise synchronization clock agreement.Contrary with SNTP and NTP, time seal is more easily realized on hardware, and is not limited to application layer, and this makes PTP can reach microsecond with interior precision.In addition, the modular design of PTP also makes it be easy to adapt to low side devices.
For precision clock system, should there is failover capability faster, this failover capability comprises, and master clock is lost the ability etc. that is switched to fast standby clock, and this requires clock synchronization compliant with precision time protocol to have quick, stable adjustment algorithm to guarantee.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of implementation method of precise synchronization clock is provided.Technical scheme of the present invention is: comprise frequency and deviation adjusting algorithm based on fuzzy, and quick internal clock synchronization algorithm, real-time synchronization checks algorithm and real-time embedded clock frequency and time deviation fine setting algorithm.
According to IEC 61588V2 agreement, by 1588 clock PHY chips, obtain PTP message timestamp, adopt fuzzy adjustment algorithm to do frequency adjustment and deviation adjusting to 1588 clock PHY chip clock systems, frequency adjustment and deviation adjusting synchronously carry out.
Internal clocking benchmark PHY, whole second outwards sends PPS pulse, other clocks PHY chip want and internal clocking benchmark PHY between synchronous; First from ns level, after inner ns aims at, to level clock second; Configuration PHY chip PPS output function.
To time process as follows:
A, empty all clock PHY PPS event clocks;
B, wait two seconds, read up-to-date PPS event, gets local PHY clock, calculates nanosecond deviation, adjusts nanosecond deviation, (all clock PHY except reference clock PHY);
C, wait two seconds, get the reference clock PHY time, if a second following clock is less than time definite value, waits for certain hour, continues step C, if a second following clock is greater than time definite value, and lock task, continuation step D;
D, read up-to-date PPS event, get local PHY clock calculation level second deviation, adjust a second level deviation, (all clock PHY except reference clock PHY);
E, release task.
In order to guarantee the reliability in operating process, the synchronous regime of regular check chip, does re-synchronization operation for not synchronous 1588 clock PHY chips.
The synchronous regime step of regular check chip is as follows:
A, selection both port of origination;
B, inspection port time deviation are greater than time definite value;
C, be not more than time definite value, select next port, if be greater than time definite value, adjust port internal clocking deviation, select next port;
D, poll all of the port;
E, end of polling(EOP), postpone certain hour, restarts A-E step.
Real-time embedded clock frequency algorithm, frequency adjustment formula: F
k+1=F
k-λ F δ
k+1.
Real-time embedded clock time deviation fine setting algorithm, deviation adjusting formula: δ T=-TOffset
k+1.
The invention has the beneficial effects as follows: this method can realize the quick switching of clock, can be used in highly reliable, redundancy clock origin system, at 10 seconds with the interior switching that can complete clock; The transmission precision of single-stage clock can reach 50ns rank; Because this algorithm can be realized the quick switching of clock, be equally applicable under redundant looped network, realize highly reliable clock system the clock HOLDOVER function of having demoted to terminal equipment.The present invention has realized software transmitting-receiving precise synchronization clock protocol massages, adjustment, critique system time clock feature.
Accompanying drawing explanation
Fig. 1 hardware plan sketch;
Fig. 2 internal port to time flow chart; ;
Fig. 3 port is inner synchronous process chart regularly;
Fig. 4 clock is adjusted sketch;
Embodiment
Explanation of nouns:
1588 clock PHY chips: there is the PHY chip of supporting IEEE 1588 and IEC 61588 protocol functions, comprising:
1, can identify IEEE 1588 or IEC 61588 protocol massages (comprising two kinds of agreements of IPV4 and IPV6);
2, support clock frequency adjustment, support that clock adjustment, clock are ns level;
3, support to receive and send message timestamp function;
4, support pulse per second (PPS) output function;
5, support pulse per second (PPS) to beat timestamp function, provide clock PHY chip chamber inner synchronous.
Clock HOLDOVER function: equipment in the situation that losing clock source, the ability of the clock accuracy that maximum can keep.
Overall plan:
The precision net synchronous protocol of the present invention's definition has been realized the high level of synchronization in network, make when distributing control work without carrying out again special synchronous communication, thereby reached the effect that call duration time pattern and application program time of implementation pattern are separated, its step comprises:
Select optimized master clock, according to optimized master clock algorithm (IEC 61588 agreement BMC algorithms), from all clock nodes, select optimized master clock.
The offset measurement stage is used for revising the time difference of master clock and slave clock.In this offset correction process, master clock cycle sends a definite synchronizing information (being called for short Sync information) (being generally every two seconds once), it has comprised a time seal (time stamp), has accurately described the scheduled time that packet sends.
Delay measurements (delay measurement) stage is used for measuring the time of delay that Internet Transmission causes, and it should be noted that, in this measuring process, supposes that transmission medium is symmetrically and evenly.
Through the exchange of synchronizing information, slave clock and master clock have been realized precise synchronization.
The present embodiment is the implementation method of a synchronous precise clock in Ethernet switch.Below in conjunction with width figure, the present invention will be described.
Fig. 1 has indicated hardware plan; Native system is that the clock synchronization compliant with precision time protocol transmission system based on Ethernet switch mainly comprises cpu system, exchange chip system and 1588 clock PHY chips;
Wherein cpu system is responsible for the operation of system 1588V2 agreement, and deviation is calculated, the functions such as message transmission and management;
Exchange chip is key data repeater system, is responsible for message distribution;
Clock PHY chip is mainly responsible for the identification of 1588V2 message, and interocclusal record when 1588 messages of turnover 1588PHY chip are done, and is responsible for the maintenance of this chip time system;
Fig. 2 indicated internal port to time flow chart;
Due to each PHY clock chip, it all can safeguard local time system; Its precision is ns rank, how synchronous, and to keep good precision be the problem that we study.
Chip itself has PPS output function, and configuration PHY chip PPS output function, like this, can select a slice PHY as tracing source according to software, and PHY chip possesses another function simultaneously, according to input PPS signal, extracts PPS event clock;
Internal clocking synchronously can be divided into second that level is synchronous and ns level is synchronous; Internal clocking benchmark PHY, whole second outwards sends PPS pulse, other clocks PHY chip want and internal clocking benchmark PHY between synchronous; First from ns level, after inner ns aims at, to level clock second.
To time process as follows:
1., empty all clock PHY PPS event clocks;
2., wait for two seconds, read up-to-date PPS event, get local PHY clock, calculate nanosecond deviation, adjust nanosecond deviation, (all clock PHY except reference clock PHY);
3., wait for two seconds, get the reference clock PHY time, if a second following clock is less than 200ms, wait for 800ms, continue step C, if a second following clock is greater than 200ms, lock task, continuation step D;
4., read up-to-date PPS event, get local PHY clock calculation level second deviation, adjust a second level deviation, (all clock PHY except reference clock PHY);
5., release task.
Fig. 3 has indicated regularly inner synchronous handling process of port; For guarantee to time accurate, need regular check to time accuracy.
1., select both port of origination;
2., check that port time deviation is greater than 100ms;
3., be not more than 100ms, select next port, if be greater than 100ms, adjust port internal clocking deviation, select next port;
4., poll all of the port;
5., end of polling(EOP), postpone 10s, restart 1.-5. step.
Fig. 4 has indicated clock to adjust sketch;
Clock adjustment under A, transparent clock pattern
For transparent clock, it is mainly processed residence time and time of delay and calculates, therefore do not need and master clock lock in time, but its will with master clock synchronizing frequency, thereby guarantee that it calculates residence time and the accuracy of time of delay.
The Sync/Follow up message markers sending according to master clock is calculated the frequency departure between local clock and master clock.
As shown in Figure 4, by clock transmission system, can obtain delivery time and the time of reception of K and K+1 Sync message, be respectively T2
k+1, T2
k, T1
k+1, T1
k,
Can obtain frequency departure is:
Fδ
k+1＝((T2
k+1-T2
k)-(T1
k+1-T1
k))/(T2
k+1-T2
k)
Frequency adjustment formula is:
F
k+1＝F
k-K
IFδ
k+1
K wherein
ifor fuzzy is adjusted the factor, it is to guarantee starting the quick of adjusting stage, and stable, high precision tracking master clock need be set decision condition subsequently, adjusts its size.
Clock adjustment under B, boundary clock pattern P2P delay measurements mechanism
For boundary clock or ordinary clock, need and master clock lock in time, thereby guarantee that its markers precision is consistent with master clock.Under P2P delay measurements mechanism, its clock jitter can be calculated by receiving the markers of SNC message, its delay can be broken down into residence time and link delay, residence time is through P2P transparent clock, be added in the correction field of Sync message/Follow UP message, link delay has calculating at each P2P port, also beats in P2P transparent clock in Correction Field, by Sync/Follow UP message, is passed;
Like this:
Toffset
k+1＝(T2
k+1-T1
k+1)-Tdelay
k+1
Delay is:
TDelay
k+1＝TCorrectionfield
k+1
Frequency departure is
Fδ
k+1＝(TOffset
k+1-TOffset
k)/TOffset
k+1
Frequency adjustment formula:
F
k+1＝F
k-K
IFδ
k+1
Deviation adjusting formula:
δT＝-K
P TOffset
K+1
K wherein
iand K
pfor fuzzy is adjusted the factor
Clock adjustment under C, boundary clock pattern E2E delay measurements mechanism
For boundary clock, need and master clock lock in time, thereby guarantee that its markers precision is consistent with master clock.Under E2E delay measurements mechanism, its deviation can be calculated by receiving the markers of SNC message, its delay can be broken down into residence time and P2P postpones, residence time is through E2E transparent clock, be added in the correctionfield of Sync message/Follow UP message, link delay is by border clock clock port transmission lag request, E2E transparent clock forwards this message, border clock responds this message, each section calculates link delay, by delay, asks response message and postpone to ask to respond the Correctionfield following in message to carry;
Like this:
Deviation is:
TOffset
K+1＝(T2
k+1-T1
k+1)-TDelay
K+1
Delay is:
TDelay
K+1＝TSCorrectionfield
K+1+TDCorrectionfield
K+1；
Wherein, TSCorrectionfield
k+1for Sync or Follow up message clock carry;
TDCorrectionfield
k+1for postponing request response or postponing, in request response Follow up message, carry;
Frequency departure is
Fδ
k+1＝(TOffset
k+1-TOffset
k)/TOffset
k+1
Frequency adjustment formula:
F
k+1＝F
k-K
IFδ
k+1
Deviation adjusting formula:
δT＝-K
P TOffset
K+1
K wherein
iand K
pfor fuzzy is adjusted the factor
Fuzzy clock is adjusted
The features such as that pid control algorithm has is simple in structure, the scope of application is wide and robustness is stronger, so it remains most widely used control algolithm so far.But the simple pid control parameter that relies on one group of off-line setting calculation of conventional PID controller, does not have online self-adjusting function, and in doing control adjustment, the pid parameter of adjusting can not adapt to whole control procedure, thereby can not reach optimal effectiveness effect.
In order to overcome the deficiency of conventional PID adjuster, improve its performance, people conduct extensive research, the self adaptation that has proposed many PID is adjusted scheme, wherein adopt fuzzy technology to be combined with PID forming fuzzy is one of conventional control method, its basic principle is on the basis of conventional PID control device, to add a fuzzy control link, regulates respectively online 3 parameter (K of PID according to the real-time status of system
p, K
i, K
d).
In clock adjustment process, adjustment aim is to be minimum from clock jitter and master clock deviation, adjusts the speed of deviation, and can keep stable tracking accuracy.Native system can reach from clock and accurately follow the tracks of master clock with deviation by adjusting frequency, and differential regulation part, deviation adjusting that its medium frequency adjustment is equivalent in PID adjustment are equivalent to resize ratio part.The last adjustment precision of the same impact of frequency and deviation adjusting, the adjustment between two parts also exists and influences each other, and finally also affects the result of adjusting and adjusts convergence rate.Therefore, clock adjustment can not be simply realize according to the theoretical formula of calculating, need to be according to the feature of clock system, and experimental result is carried out the adjusting parameter of determination module PID.
According to fuzzy theory, and simplify obfuscation and defuzzification processing, setpoint frequency (difference) is adjusted Regulations The table:
| Frequency departure | Be greater than 400000ns/s | Be less than 400000ns/s and be greater than 20000ns/s | Be less than 20000ns/s and be greater than 200ns/s | Be less than 200ns |
| K I | 0 | 0.8 | 1.0 | 0.5 |
According to fuzzy theory, and simplify obfuscation and defuzzification processing, set deviation (ratio) adjustment form
| Frequency departure | Be greater than 400000ns/s | Be less than 400000ns/s and be greater than 20000ns/s | Be less than 20000ns/s and be greater than 200ns/s | Be less than 200ns |
| K P | 1 | 0.8 | 0.7 | 0.9 |
Integral adjustment parameter is always 0.
The foregoing is only process of the present invention and embodiment of the method, not in order to limit the present invention, all any modifications of making, be equal to replacement, improvement etc., within all should being included in protection range of the present invention within spirit of the present invention and essence.
Claims (3)
1. the implementation method of a precise synchronization clock, it is characterized in that, comprise frequency and deviation adjusting algorithm based on fuzzy, fast internal clock synchronization algorithm, real-time synchronization checks algorithm and real-time embedded clock frequency and time deviation fine setting algorithm, the steps include:
(1), 1588 clock PHY chips are carried out to frequency adjustment and deviation adjusting synchronous, be specially: according to IEC61588V2 agreement, by 1588 clock PHY chips, obtain PTP message timestamp, adopt fuzzy adjustment algorithm to do frequency adjustment and deviation adjusting to 1588 clock PHY chip clock systems, frequency adjustment and deviation adjusting synchronously carry out;
(2) synchronous and keep the good precision of the local zone time system of PHY clock chip, be specially: internal clocking benchmark PHY, within whole second, outwards send PPS pulse, other clocks PHY chip want and internal clocking benchmark PHY between synchronous; First from nanosecond, after inner nanosecond aims at, to level clock second; Configuration PHY chip PPS output function;
(3), in order to guarantee the reliability in operating process, the synchronous regime of regular check chip, does re-synchronization operation for not synchronous 1588 clock PHY chips, is specially:
Use real-time embedded clock frequency algorithm, frequency adjustment formula: F
k+1=F
k– K
if δ
k+1, K wherein
ifor fuzzy is adjusted the factor;
Use real-time embedded clock time deviation fine setting algorithm, deviation adjusting formula: δ T=-K
ptOffset
k+1, K wherein
pfor fuzzy is adjusted the factor.
2. method according to claim 1, is characterized in that, internal clocking benchmark PHY whole second outwards sends PPS pulse, other clocks PHY chip want and internal clocking benchmark PHY between synchronizing process as follows:
A, empty all clock PHY PPS event clocks;
B, wait two seconds, read up-to-date PPS event, gets local PHY clock, calculates and adjust the nanosecond deviation of all clock PHY except reference clock PHY;
C, wait two seconds, get the reference clock PHY time, if a second following clock is less than time definite value, waits for certain hour, continues step C, if a second following clock is greater than time definite value, and lock task, continuation step D;
D, read up-to-date PPS event, get local PHY clock, calculate and adjust grade deviation second of all clock PHY except reference clock PHY; E, release task.
3. method according to claim 1, is characterized in that, the synchronous regime step of regular check chip is as follows:
A, selection both port of origination;
Whether B, inspection port time deviation are greater than time definite value;
If C is not more than time definite value, select next port; If be greater than time definite value, adjust port internal clocking deviation, select next port;
D, poll all of the port;
E, end of polling(EOP), postpone certain hour, restarts A-E step.
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