CN101840902A - Direct chip placing lead frame structure and production method thereof - Google Patents
Direct chip placing lead frame structure and production method thereof Download PDFInfo
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- CN101840902A CN101840902A CN201010165898A CN201010165898A CN101840902A CN 101840902 A CN101840902 A CN 101840902A CN 201010165898 A CN201010165898 A CN 201010165898A CN 201010165898 A CN201010165898 A CN 201010165898A CN 101840902 A CN101840902 A CN 101840902A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a direct chip placing lead frame structure and a production method thereof. The structure comprises pins (2). A first metal layer (4) is arranged on the front surface of each pin (2). A second metal layer (5) is arranged on the back surface of each pin (2). The front surface of each pin (2) extends as much as possible to a position below a chip which is subsequently attached. Encapsulation material (3) with no packing is embedded in the peripheral area of each pin (2) and an area between the pin (2) and the pin (2). The encapsulation material (3) with no packing connects the periphery of the lower part of the pin (2) and the lower part of the pin (2) with the lower part of the pin (2) into a whole body. The dimension of the back surface of the pin (2) is enabled to be smaller than the dimension of the front surface of the pin (2) to form a pin structure with a large upper part and a small lower part. The invention has the advantages that the binding capacity between the encapsulation body and the pin is high, the cost is reduced, the energy is saved, the carbon emission is reduced and the waste is reduced.
Description
(1) technical field
The present invention relates to a kind of lead frame structure and production method thereof.Belong to the semiconductor packaging field.
(2) background technology
Traditional lead frame structure mainly contains two kinds:
First kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in figure 14) that to carry out encapsulation process.
Second kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in figure 15) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but this kind lead frame must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, and in the ball bonding bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of ball bonding bonding parameter, seriously influenced the quality of ball bonding and the stability of production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in figure 16) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
5) general lead frame all has the design of Ji Dao, causes the size of chip to be limited by the size of Ji Dao, and the area of packaging body also will amplify thereupon when bigger as the size of fruit chip.
Second kind:
This kind lead frame structure has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in figure 17) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the metal leg is far away, the length of metal wire is longer, shown in Figure 18～19, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (being the product of storage class and the calculating that needs mass data by it, more outstanding); Too because the length of metal wire is longer, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are also higher to the interference of signal; Because the distance between chip and the metal leg is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
In addition, general lead frame all has the design of Ji Dao, causes the size of chip to be limited by the size of Ji Dao, and the area of packaging body also will amplify thereupon when bigger as the size of fruit chip.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide a kind of and reduce that packaging cost, selectable product category are wide, the big direct chip placing lead frame structure and the production method thereof of constraint ability of good stability, plastic-sealed body and the metal leg of the quality of ball bonding and production reliability.
(3) summary of the invention
The object of the present invention is achieved like this: a kind of direct chip placing lead frame structure, comprise pin, front at described pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, described pin front extends to the below of follow-up pasting chip as much as possible, zone in described pin periphery, zone between the lower zone of follow-up pasting chip and pin and the pin is equipped with packless plastic packaging material, described packless plastic packaging material links into an integrated entity periphery, pin bottom and pin bottom and pin bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The production method of direct chip placing lead frame structure of the present invention, described method comprises following processing step:
Step 1, get metal substrate
Step 2, pad pasting operation
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at the front and the back side of metal substrate,
The metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation is carried out exposure imaging and is removed the part photoresist film, exposing the zone that follow-up needs etch partially on the metal substrate,
Step 4, metal substrate front etch partially
The positive zone of removing the part photoresist film of metal substrate in the step 3 is etched partially,, forms the back side of pin simultaneously relatively in the positive half-etched regions that forms depression of metal substrate,
The film operation is taken off at step 5, the positive back side of metal substrate
The positive remaining photoresist film of metal substrate and the photoresist film at the back side are removed.
In the positive half-etched regions that forms depression of step 4 metal substrate, packless soft gap filler in the full-filling, and toast simultaneously, impel packless soft underfill cures to become packless plastic packaging material.
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at the front and the back side of the metal substrate of finishing the packless soft gap filler operation of full-filling,
The part photoresist film is removed at the front and the back side at metal substrate, and purpose is the back side and the front of exposing pin.
The back side of the pin that exposes in step 8 plates second metal level, plates the first metal layer in the front of pin
Remove metal substrate back portion photoresist film, with the zone of exposing pin periphery, the metal substrate back side and the zone between pin and the pin,
Is the front that the metal etch of step 4 remaining part goes out described pin at the back side of metal substrate to the zone that is not covered by photoresist film, simultaneously the pin front is extended to as much as possible the below of follow-up pasting chip, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The film operation is taken off at step 12, the positive back side of metal substrate
The photoresist film of metal substrate front and back remainder is removed.
The invention has the beneficial effects as follows:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of this kind lead frame.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame, guaranteed the stability of ball bonding bonding parameter, guaranteed the quality of ball bonding and the stability of production reliability.
4) but again because this kind lead frame need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the zone between described pin and pin is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole pin with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
6) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form slightly little and the structure that positive pin size is big slightly of the size of back side pin, and slided by the tighter more difficult generation that packless plastic packaging material coated and falling pin with the size that varies in size up and down of a pin.
7) separate etched technology owing to used the back side with the front, so the pin in lead frame front can be extended to as much as possible the below of follow-up pasting chip, impel chip and pin distance significantly to shorten, as Figure 20～21, so the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter).
8) also because the shortening of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
9) because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
10) because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
11) because metal pins is directly extended to the below of chip, thus more high power capacity or bigger chip can be installed under identical packaging body area, on the contrary the following packaging body area can be contracted littler of identical chip size.
(4) description of drawings
Fig. 1～12 are each operation schematic diagram of production method of direct chip placing lead frame of the present invention.
Figure 13 is a direct chip placing lead frame structure schematic diagram of the present invention.
Figure 14 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Figure 15 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Figure 16 was for formed insulation pin schematic diagram in the past.
Figure 17 pin figure for what formed in the past.
Figure 18 is an encapsulating structure schematic diagram in the past.
Figure 19 is 18 vertical view.
Figure 20 is for adopting the encapsulating structure schematic diagram of lead frame of the present invention.
Figure 21 is 20 vertical view.
Reference numeral among the figure:
Pin 2, packless plastic packaging material 3, the first metal layer 4, second metal level 5, metal substrate 6, photoresist film 7 and 8, half-etched regions 9, photoresist film 10 and 11.
(5) embodiment
Direct chip placing lead frame production method of the present invention is as follows:
Step 1, get metal substrate
Referring to Fig. 1, get the suitable metal substrate of a slice thickness 6.The material of metal substrate 6 can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Step 2, pad pasting operation
Referring to Fig. 2, utilize film sticking equipment to stick the photoresist film 7 and 8 that can carry out exposure imaging respectively, to protect follow-up etch process operation at the front and the back side of metal substrate.
Referring to Fig. 3, exposure imaging removal part photoresist film is carried out in the metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation, to expose the zone that follow-up needs etch partially on the metal substrate.
Step 4, metal substrate front etch partially
Referring to Fig. 4, the positive zone of removing the part photoresist film of metal substrate in the step 3 is etched partially, in the positive half-etched regions 9 that forms depression of metal substrate, form the back side of pin 2 simultaneously relatively, its purpose mainly is to avoid occurring in subsequent job the glue that overflows.
The film operation is taken off at step 5, the positive back side of metal substrate
Referring to Fig. 5, the positive remaining photoresist film of metal substrate and the photoresist film at the back side are removed.
Referring to Fig. 6, in the positive half-etched regions 9 that forms depression of step 4 metal substrate, packless soft gap filler in the full-filling, and toast simultaneously, impel packless soft underfill cures to become packless plastic packaging material 3.
Referring to Fig. 7, utilize film sticking equipment to stick the photoresist film 10 and 11 that can carry out exposure imaging respectively, to protect follow-up metal cladding process operation at the front and the back side of the metal substrate of finishing the packless soft gap filler operation of full-filling.
Referring to Fig. 8, remove the part photoresist film at the front and the back side of metal substrate, purpose is the back side and the front of exposing pin.
Referring to Fig. 9, the back side of the pin that exposes in step 8 plates second metal level 5, plate the first metal layer 4 in the front of pin, can be tightr, firm between metal wire and chip region and the routing Nei Jiao district during in order to follow-up bonding wire engage is increased in the conjugation that impels in the encapsulating process between Packed plastic packaging material simultaneously.And the one-tenth branch of metal level can be to adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. because of different chip materials.
Referring to Figure 10, remove metal substrate back portion photoresist film, with the zone of exposing pin periphery, the metal substrate back side and the zone between pin and the pin,
Referring to Figure 11, is the front that the metal etch of step 4 remaining part goes out described pin at the back side of metal substrate to the zone that is not covered by photoresist film, simultaneously the pin front is extended to as much as possible the follow-up chip below that mounts, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The film operation is taken off at step 12, the positive back side of metal substrate
Referring to Figure 12, the photoresist film of metal substrate front and back remainder is removed.
End product is referring to Figure 13: among Figure 13, pin 2, packless plastic packaging material 3, the first metal layer 4 and second metal level 5, as seen from Figure 13, direct chip placing lead frame structure of the present invention, comprise pin 2, described pin 2 fronts extend to the below of follow-up pasting chip as much as possible, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of described pin 2, zone in described pin 2 peripheries, zone between the zone of the below of follow-up pasting chip and pin 2 and the pin 2 is equipped with packless plastic packaging material 3, described packless plastic packaging material 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The present invention can electroplate the making that the first metal layer 4 or regional area are electroplated the first metal layer 4 because of the Zone Full that need carry out in the front of above-mentioned pin 2 of chip functions.
Claims (2)
1. direct chip placing lead frame structure, comprise pin (2), be provided with the first metal layer (4) in the front of described pin (2), be provided with second metal level (5) at the back side of described pin (2), it is characterized in that: described pin (2) front extends to the below of follow-up pasting chip, in the peripheral zone of described pin (2), zone between the lower zone of follow-up pasting chip and pin (2) and the pin (2) is equipped with packless plastic packaging material (3), described packless plastic packaging material (3) links into an integrated entity periphery, pin bottom and pin (2) bottom and pin (2) bottom, and make described pin (2) back side size less than the positive size of pin (1), form up big and down small pin configuration.
2. the production method of a direct chip placing lead frame as claimed in claim 1 is characterized in that described method comprises following processing step:
Step 1, get metal substrate
Step 2, pad pasting operation
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at the front and the back side of metal substrate,
Step 3, the positive part photoresist film of removing of metal substrate
The metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation is carried out exposure imaging and is removed the part photoresist film, exposing the zone that follow-up needs etch partially on the metal substrate,
Step 4, metal substrate front etch partially
The positive zone of removing the part photoresist film of metal substrate in the step 3 is etched partially,, forms the back side of pin simultaneously relatively in the positive half-etched regions that forms depression of metal substrate,
The film operation is taken off at step 5, the positive back side of metal substrate
The positive remaining photoresist film of metal substrate and the photoresist film at the back side are removed.
Step 6, the packless soft gap filler of the positive half-etched regions full-filling of metal substrate
In the positive half-etched regions that forms depression of step 4 metal substrate, packless soft gap filler in the full-filling, and toast simultaneously, impel packless soft underfill cures to become packless plastic packaging material.
Step 7, the pad pasting operation of the positive back side of metal substrate
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at the front and the back side of the metal substrate of finishing the packless soft gap filler operation of full-filling,
Step 8, removal part photoresist film
The part photoresist film is removed at the front and the back side at metal substrate, and purpose is the back side and the front of exposing pin.
Step 9, metal cladding
The back side of the pin that exposes in step 8 plates second metal level, plates the first metal layer in the front of pin,
Step 10, removal metal substrate back portion photoresist film
Remove metal substrate back portion photoresist film, with the zone of exposing pin periphery, the metal substrate back side and the zone between pin and the pin,
Step 11, the metal substrate back side etch partially
Is the front that the metal etch of step 4 remaining part goes out described pin at the back side of metal substrate to the zone that is not covered by photoresist film, simultaneously the pin front is extended to as much as possible the below of follow-up pasting chip, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
The film operation is taken off at step 12, the positive back side of metal substrate
The photoresist film of metal substrate front and back remainder is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010165898XA CN101840902B (en) | 2010-04-30 | 2010-04-30 | Direct chip placing lead frame structure and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010165898XA CN101840902B (en) | 2010-04-30 | 2010-04-30 | Direct chip placing lead frame structure and production method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN101840902A true CN101840902A (en) | 2010-09-22 |
| CN101840902B CN101840902B (en) | 2011-06-15 |
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| CN201010165898XA Active CN101840902B (en) | 2010-04-30 | 2010-04-30 | Direct chip placing lead frame structure and production method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020158347A1 (en) * | 2000-03-13 | 2002-10-31 | Hiroshi Yagi | Resin -encapsulated packing lead member for the same and method of fabricating the lead member |
| CN101231958A (en) * | 2007-01-24 | 2008-07-30 | 先进科技新加坡有限公司 | Chip carrier including an interlocking structure |
| CN201681890U (en) * | 2010-04-30 | 2010-12-22 | 江苏长电科技股份有限公司 | Lead frame structure for direct placement by chip |
-
2010
- 2010-04-30 CN CN201010165898XA patent/CN101840902B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020158347A1 (en) * | 2000-03-13 | 2002-10-31 | Hiroshi Yagi | Resin -encapsulated packing lead member for the same and method of fabricating the lead member |
| CN101231958A (en) * | 2007-01-24 | 2008-07-30 | 先进科技新加坡有限公司 | Chip carrier including an interlocking structure |
| CN201681890U (en) * | 2010-04-30 | 2010-12-22 | 江苏长电科技股份有限公司 | Lead frame structure for direct placement by chip |
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| Publication number | Publication date |
|---|---|
| CN101840902B (en) | 2011-06-15 |
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