CN101601133B - 部分图案化的引线框以及在半导体封装中制造和使用其的方法 - Google Patents

部分图案化的引线框以及在半导体封装中制造和使用其的方法 Download PDF

Info

Publication number
CN101601133B
CN101601133B CN2007800398623A CN200780039862A CN101601133B CN 101601133 B CN101601133 B CN 101601133B CN 2007800398623 A CN2007800398623 A CN 2007800398623A CN 200780039862 A CN200780039862 A CN 200780039862A CN 101601133 B CN101601133 B CN 101601133B
Authority
CN
China
Prior art keywords
chip
lead frame
lead
wire
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007800398623A
Other languages
English (en)
Other versions
CN101601133A (zh
Inventor
M·J·拉莫斯
A·苏巴乔
L·辛普里奥斯吉瑞特
R·S·圣安东尼奥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Interconnect Technology Ltd
Unisem (Mauritius) Holdings Ltd
Original Assignee
Advanced Interconnect Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/553,664 external-priority patent/US7799611B2/en
Application filed by Advanced Interconnect Technology Ltd filed Critical Advanced Interconnect Technology Ltd
Publication of CN101601133A publication Critical patent/CN101601133A/zh
Application granted granted Critical
Publication of CN101601133B publication Critical patent/CN101601133B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48701—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/48711—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48739—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48744—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48747—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48755—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48801—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/48811—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48855—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/85411—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20754—Diameter ranges larger or equal to 40 microns less than 50 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20755—Diameter ranges larger or equal to 50 microns less than 60 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20756—Diameter ranges larger or equal to 60 microns less than 70 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20757—Diameter ranges larger or equal to 70 microns less than 80 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20758—Diameter ranges larger or equal to 80 microns less than 90 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20759—Diameter ranges larger or equal to 90 microns less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/2076—Diameter ranges equal to or larger than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

一种制造引线框和具有近似芯片级封装引线数目的部分图案化引线框封装的方法，其中该方法适于更佳的生产线自动化以及从中生产封装的改进的质量和可靠性。制造工艺步骤的主要部分用在一侧上形成为蹼状引线框的部分图案化的金属条执行，以使蹼状的引线框也是机械上刚性的和热力学上鲁棒的以在芯片附连和引线接合工艺期间、在芯片级和封装级上没有扭曲或变形地执行。仅在包括芯片和布线的前侧使用密封材料密闭地密封之后，金属引线框的底侧被图案化以隔离芯片焊盘和引线接合触点。被电隔离的所得封装允许进行拉伸测试和可靠的单片化。

Description

部分图案化的引线框以及在半导体封装中制造和使用其的方法
发明领域
本申请是2006年10月27日提交的美国专利申请S/N.11/553,664的部分继续申请，后者是2005年8月4日提交的美国专利申请S/N.11/197,944的部分继续申请，而后者是2004年8月10日提交的美国专利申请S/N.10/916,093、现为US 7,129,116的继续申请，而后者又是2002年4月29日提交的美国专利申请S/N.10/134,882、现为US 6,812,552的继续申请。所有这些申请通过引用完整结合于此。
本发明一般涉及电子封装，尤其涉及部分图案化的引线框以及用于制造和使用其的方法。部分图案化的引线框相比常规引线框更坚固且更稳定。部分图案化的引线框的坚固性改进了制造引线框封装的工艺并且增强最终产品的总的可靠性。引线框还为器件集成提供高度灵活性以及增加的功能性。
发明背景
在制造使用引线框的电子封装中，存在若干使引线框经受机械和热应力的工艺步骤。当前引线框的更细致的几何形状以及半导体芯片上电路的进一步增大的集成度已导致在引线框上施加甚至更大应力的处理。精细配置的引线框常常类似非常精致的刺绣品、或者倾向于容易弯曲、破裂、损坏或变形的模板型的金属结构。(参见图1a和1b)。这些常规引线框在行业中用以创建包括引线接合和倒装芯片(FC)封装的各种芯片封装。(参见图2a-2d以及3a-3b)。
常规引线框通常缺乏结构刚度。引线框的指型部分可以是非常脆弱的并且难以保持在原位。这在集成工艺以及复杂的引线接合情况中导致处理缺陷、损伤以及扭曲。因而，接合参数不得不被优化以补偿在接合工艺期间的引线框弹跳。无法优化接合参数以补偿引线框的机械不稳定性可导致较差的接合粘性，且因而较差的接合质量和可靠性。
通常引线框的大金属板部分从称为芯片容纳区域、也称为芯片焊盘的中心位置延伸。芯片通常附连到容纳区域，并且背侧朝下且前侧被放置成面朝上，且端子外围地置于芯片的周边上、或以阵列形式置于芯片的表面上。容纳区域通常具有约5mmx5mm的尺寸，并且从芯片焊盘区域向外延伸的引线具有约10mm长x1mm宽x0.2mm厚的典型尺寸。引线框通常被真空夹盘和机械夹具压紧。夹盘和夹具必需为不同大小和形状的引线框进行改装。本发明解决了这一问题。
现有技术尚未示出任何可耐受在当前半导体封装工艺中遇到的应力并且可以节省成本的方式制造的引线框。本发明通过提供部分图案化的引线框来实现此目的，该部分图案化的引线框不仅改进了引线框自身的可制造性，而且改进从其形成的电子封装的集成度和可靠性。本发明还解决对于常规引线框不能提供的持续增加的器件复杂性需求，诸如高的I/O数目、多芯片设计、系统级封装、以及布线上的灵活性。
发明内容
引线框由具有顶面和底面的膜构成。膜的第一区域从顶面被部分图案化但是不完全穿过膜到达底面。膜的第二区域(未从顶面图案化)形成用于支承集成电路(IC)芯片的芯片容纳区域以及多个用于提供到IC芯片的电连接的引线触点。第一区域在膜中形成槽，并且产生互连未从顶面部分图案化的第二区域的蹼状结构。本发明还涉及一种制造部分图案化的引线框的方法以及采用这些引线框的电子封装。本发明的引线框已因为其蹼形或蹼状结构改进结构刚度。
根据本发明，首先使用标准的光刻技术或类似技术图案化由其形成引线框的金属膜的顶面以绘出将与芯片容纳区域和引线相对应的区域的轮廓。在下一步骤，蚀刻在膜的绘出轮廓区域之外的第一区域中执行，从膜的顶面穿过下层膜的厚度以在膜中产生引线框图案。在部分图案化之后，未从顶面图案化的剩余区域形成第二区域，其将用作芯片容纳区域以及沿顶面的引线。第一区域形成膜的顶面之下的凹入蹼状区域。第一区域的蹼状结构使引线部分相互连接并且连接到芯片容纳区域。因而，部分图案化膜看上去与蹼足(webbedfoot)类似并且保持其刚度以及强度，所以它可耐受后续制造工艺步骤的应力。特别地，部分图案化的引线框可耐受在引线接合和封装工艺期间遭遇的应力。在一些实施例中，芯片容纳区域和电引线可从第二区域的相同部分形成(例如，在电引线支承集成芯片并且提供与其的电连接的情况下)。
本发明还提供一种使用部分图案化的引线框制造多个电子封装的独特方法。该方法涉及具有顶面和底面的膜。在第一区域中，膜从顶面部分图案化但不是完全穿过到达底部。膜上的未从顶面部分图案化的剩余第二区域形成多个部分图案化的引线框。所以引线框各自具有一个用于支承集成电路(IC)芯片的芯片容纳区域以及多个用于提供与IC芯片的电连接的电引线。
膜的第一区域形成使芯片容纳区域与每个引线框的电引线互连的蹼状结构。第一区域还在膜的芯片间隔(street)部分中使多个引线框相互连接。
设置有多个芯片，每一个芯片具有用于附连到相应引线框的多个电端子。每个芯片被附连到相应引线框上的芯片容纳区域并且电连接在每个芯片的至少一个端子与引线框的电引线之一之间形成。此外，密封材料被涂敷在引线框和膜的芯片间隔部分上以完全覆盖膜的顶部。一旦密封材料被弄干，背部图案化工艺就在第一区域从膜的底面执行以去除蹼状结构和膜的芯片间隔部分。设置在膜的芯片间隔部分上的密封材料然后被单片化以形成各个封装。
在优选实施例中，该方法包括将引线框形成为框/窗口图案中的矩阵中的膜，并且涉及芯片级封装的生产。
若干优点从本发明的部分图案化引线框产生。引线框的平坦和实心的未蚀刻底面在引线接合工艺期间用作出色的热沉。这为更佳和更一致的接合质量提供均匀的热传输。另外，实心结构为通用真空夹盘压紧引线框提供连续的表面，从而使得在后续工艺步骤期间芯片附连工艺更稳定并且引线更安全。引线框的外缘的笨拙夹紧被消除以允许阵列矩阵引线框设计和加工而无需转换。因为部分图案化的引线框的底侧是平坦的连续表面，所以通用真空夹盘可被用来压紧许多不同尺寸的框。这去除每次在封装工艺中采用不同尺寸的引线框时不得不改装真空夹盘的复杂性。此外，没有对夹钳的进一步需求。通用真空夹盘的使用以及夹紧的消除允许在第二区域上构造两行或三行的交错引线以得到更高数目的引线。
本发明涉及将不仅容纳引线接合芯片而且容纳焊凸倒装芯片的部分图案化引线框。此外，本发明示教一种为制造使用引线接合的蚀刻引线框封装(ELP)、具有倒装芯片的ELP(ELPF)、以及具有岸栅阵列(LGA)焊盘以形成蚀刻岸栅阵列(ELGA)封装的ELP或ELPF使用部分图案化引线框的方法，如本发明的各实施例中进一步所述。
倒装芯片(FC)技术是向将芯片上的电端子的完全自动结合到下一级封装的另一步骤，该下一级封装即为陶瓷或塑料基板、或者稍后结合到基板的芯片微载体(microcarrier)。微载体(其仅稍大于芯片本身)现在称为芯片级封装(CSP)。FC技术从带自动化接合(TAB)发展而来，而TAB又从引线接合(WB)发展而来。尽管在WB和TAB中芯片被放置在其背面上并且对位于其顶面上的周边周围的端子进行电连接，然而在FC技术中芯片的取向被反转。芯片被面向下地放置并且芯片的背侧朝上。此倒装芯片取向具有显著优点，因为它在芯片的下侧集中电功能，留下顶侧在开发高效的热传输设计时自由使用。
在FC工艺中，芯片端子或接合焊盘用芯片的表面上的不同类型的凸块密封，其中图案可布置成区域阵列、外围图案或其它图案。芯片可以按以下方式附连到下一级：a)FC附连到引线框；b)层/基板的FC附连(称为插入物)，用于在引线框上重新路由连接空隙；c)FC附连到引线框上的预附连插入物；或者d)使用包括芯片重熔方法的常规技术FC附连到印刷电路板。
使用常规技术的芯片附连在制造QFN封装及其诸如VFQPF-N之类的派生物的过程中应用于QFN(方型扁平无引线封装)引线框时变得尤其困难。这是因为常规引线框通常缺乏结构刚度。引线框的指型部分可以是相当脆弱的并且难以保持在一个精确位置。这在组装工艺以及复杂的芯片接合情况中导致处理缺陷、损伤以及扭曲。PC结合工艺需要凸起焊料头与引线框的悬挂和脆弱的引线端的精确对准。此外，弄湿的焊料端必须在通过焊料重熔工艺之后保持在它们的位置。因此，重熔参数必须被最优化以补偿芯片结合期间的引线框弹跳，这(如果未处理得当)可以导致差的结合点，并且从而导致最终产品的较差质量和较差可靠性。
一般惯例是通过图案化金属条或金属膜上的光致抗蚀剂、并且蚀刻穿图案来形成从芯片容纳区域向外延伸的指型引线来形成常规模板型引线框。也习惯使用手指之间的“分流条”(tie-bar)，以使手指在各工艺步骤期间被保持分开，如图3a和3b所示。本发明通过形成蹼形、部分图案化引线框而非模板型引线框来解决引线框的结构刚度缺乏的问题。
根据本发明的一种方法，形成半导体封装的所有主要工艺步骤从膜的要变成引线框的一侧执行。另一侧(即底侧)在诸如真空夹盘的表面之类的表面上保持平坦且未触摸。这包括封装且密闭地密封封装的部分形成前侧的步骤。一旦封装完成，底面就被背部蚀刻以选择性地去除使引线相互连接并且连接到芯片容纳区域的蹼状部分。在其中芯片被倒装接合到芯片容纳区域上的芯片焊盘并且通过引线接合进行与芯片端子的电连接的ELP情况下，所有中间蹼状部分通过蚀刻被切断使得芯片焊盘和引线接合端的引线触点通过围绕芯片、引线和引线接合触点区域的正面的模制材料相互隔离。然而，在ELFP封装的情况下，仅使引线相互连接的蹼状部分通过蚀刻切断，因为连接到芯片焊料头凸块的引线本身提供与下一级封装的电连接。
嵌入蹼状部分中的锯厚、或芯片间隔的金属的去除具有若干优点，包括消除在整个引线框结构中传播的锯切力，并且因此，防止金属塑料界面上的分层。此外，通过背部蚀刻的电绝缘使拉伸测试能在任何锯切或单片化之前拉伸测试、或在任何进一步工艺步骤之前进行。在背部图案化之后，底面上的保留和暴露金属部分可以使用任何数目的可焊材料通过浸锡浸镀或化学镀镍来进行毛刺修整(flash finish)。然而，ELGA封装使用ELPF封装的PC，且LGA焊盘用于连接到下一级封装。
为了防止在制造期间模制材料与封装的其它组件之间的任何分离，本发明还示教如何在部分蚀刻引线框的凹入蹼状部分的暴露垂直壁上(诸如在引线的侧壁上)形成锁定部件，这些部件将与诸如树脂之类的模制材料接触。作为替换，还示教在芯片焊盘和引线触点的边缘上形成“唇缘”，以便于捕捉各个唇缘之下的模制材料，从而使得模制材料难以与匹配表面分离。
从以上显然可见，部分蚀刻的引线框提供结构的一致性以及伴随的刚性和强度来在制造电子封装时很好地耐受各种制造工艺的应力和应变。这是因为这些独特的机械特性造成的，使得部分蚀刻引线框封装还可耐受用于连接到下一级封装的布线到封装底部的严密超声接合，迄今为止这对于常规塑料封装是不可能的。
本发明的一个方面提供一种用于形成电子封装的方法。该方法包括形成具有选择性预电镀顶面和底面的一块部分蚀刻引线框。该引线框包括蹼状部分并且通过芯片间隔部分相互分离。
第一组芯片附连到引线框上的芯片焊盘区域。为方便起见，支承集成芯片(IC)、或者IC芯片附着其上的引线框的区域将被称为芯片焊盘区域或者芯片容纳区域，不论此区域是用于引线接合芯片、倒装芯片、还是本领域已知的任何其它类型。这些第一组的芯片可使用粘合剂、树脂、或者与这两个组件相容的其它材料倒装接合到芯片容纳区域。例如，倒装接合可使用环氧树脂、不导电环氧树脂、带或焊膏完成。其它适当的材料在本领域中是已知的。
第二组芯片然后管芯叠装在相应的第一组芯片的顶部上。在第二组芯片被管芯叠装在第一组芯片的顶部上之后，一个或多个其它芯片组可被管芯叠装在第二组芯片的顶部上，从而提供包括叠装在彼此顶部的两个、三个、或更多个芯片的封装。在本发明的某些实施例中，不是第一组芯片中的所有芯片可具有管芯叠装在它们顶部的芯片。在这些实施例中，引线框将具有一个或多个单个(非叠装)芯片以及一组或多组管芯叠装芯片。
电连接在第一芯片的每一个的端子与相应引线框的电引线部分之间形成。电引线部分与芯片焊盘区域电绝缘。也形成与第二或附加芯片组的电连接。多个电连接可在芯片已被管芯叠装到引线框上之后同时形成。替换地，第一组芯片可附连并且电连接到引线框，并且随后第二或附加组芯片可被管芯叠装到第一组芯片的顶部并且电连接到引线框。
在芯片被管芯叠装到引线框上并且电连接到引线框之后，引线框然后通过在引线框和分隔引线框的芯片间隔部分上涂覆密封材料来封装。在封装之后，引线框的底部背面被背部图案化以去除蹼状部分和芯片间隔部分。背部图案化可通过任何便利方法来执行，诸如通过蚀刻。
如果预电镀材料被涂敷在引线框的底部例如用作光致抗蚀剂，则此预电镀材料可在背部图案化之后被去除。
隔离图案可在背部图案化之后在引线框的底部形成。这些隔离图案可被电镀或用材料涂敷以保护其表面。适当材料的示例包括化学镀Ni/浸Au、浸Ag、浸Sn、有机表面防护剂(OSP)、以及其它可焊材料。此抛光或电镀步骤便于向芯片封装的背面提供附加稳定性，并且可容许与计算机板、插口、或芯片封装所放置的其它位置的经改进的可连接性。
置于芯片间隔部分上的密封材料被单片化以形成单个芯片级封装以供用于半导体行业中的各种应用。单片化可使用任何可用于分离各个芯片封装的任何便利手段完成。在一实施例中，单片化可通过使用锯或磨耗喷水切割密封材料来进行。
本发明的另一方面提供包括芯片焊盘区域和引线以及具有交替可变体(alternation)的引线框。交替可变体可被视为位于引线框的结构部件上的元件，其在与不具有交替可变体的引线框相比时提供增大的表面积。这些交替可变体便于保留在单片化之前涂敷于引线框上的密封材料。这些交替可变体可以是任何形式的，诸如引线框的电引线上的凹口。
第二组芯片的每一个可以与相应第一芯片大小相同或不同。此外，附连到引线框的第一组芯片不需要是全部相同的，因而这些第一组芯片可包括更大或更小的芯片。通常，最大的芯片将被附连到芯片焊盘区域并且越来越小的芯片将被管芯叠装在此芯片的顶部。在替换实施例中，最大芯片将不被附连到芯片焊盘区域，但是将在管芯叠装芯片的中间或顶部。管芯叠装芯片的大小可全部相同。
第二组和附加组的芯片可使用本领域已知的任何便利手段叠装并接合到相应的第一芯片。例如，芯片可以使用不导电环氧树脂或者诸如带之类的绝缘材料叠装以防止芯片之间或之内的干涉或电移动。在另一实施例中，第二组芯片可使用带、导电粘合剂或导电环氧树脂附着于相应的第一芯片。
第一组芯片使用已知技术电连接到引线框。例如，芯片可使用引线接合技术或者使用倒装芯片技术连接到引线框。
第一组芯片可在第二组芯片管芯叠装在第一芯片之前电连接到引线框。替换地，第一组芯片可在第二组或附加组芯片管芯叠装到相应的第一组芯片上之后连接到引线框。形成电连接的步骤可通过将芯片上的各端子连接到延伸到芯片区域的电引线的端部实现。电连接可使用任何便利或适当技术形成。例如，如果芯片是引线接合芯片，则连接可使用诸如热声接合(thermasonic bonding)之类的引线接合技术形成。倒装芯片将通常使用倒装芯片技术电连接到引线框。引线接合和倒装芯片技术的组合也在本发明的范围之内。当倒装芯片被直接附连到引线框时，相应的引线可被电镀或不电镀。
第二组芯片接收功率以执行计算或其它功能。该第二组芯片可以电连接到相应的第一芯片、引线框或它们两者。在各芯片与引线框之间建立的连接依赖于邻近的具体情况以及形成的特定电子封装。
用在本发明中的芯片类型还将取决于具体环境。例如，芯片可以是引线接合芯片、倒装芯片、或者适用于电子芯片封装的任何其它类型的芯片。在一实施例中，第一组芯片包括倒装芯片或者引线接合芯片或者它们两者，并且第二组以及任何随后组芯片包括引线接合芯片。芯片中的何一个还可包括半导体器件。
根据本发明通过管芯叠装芯片形成的电子封装在封装和单片化之后将具有特定高度。为了降低电子封装的高度，芯片焊盘区域可凹入以降低所获封装的高度。即，引线框上的芯片焊盘可形成为具有降低内部，以便于使芯片能装入此区域内并且因此提供具有降低高度的芯片。
根据所公开方法形成的电子封装是坚固且稳定的。为了提供封装在应力状况和制造期间的进一步可靠性，交替可变体可被用来增加密封材料的保留。交替可变体可沿芯片焊盘、引线或它们两者的周边设置。
底部引线框的选择性预电镀可用来限定引线框的底部部件。此选择性预电镀可在引线框的顶面和底部表面提供类似的图案。选择性预电镀可使用任何便利材料完成。在一实施例中，NiPdAu或银合金被用来预电镀引线框。
在封装之后，管芯叠装芯片将被固体密封材料围绕以防止芯片与引线框之间的电连接的移动或减弱。整组的叠装芯片可被密封材料覆盖。替换地，诸如背面或顶面之类的最顶层芯片的一部分可在封装之后保持暴露。例如，最顶层芯片的表面可穿透密封材料以及嵌入密封材料中的芯片的剩余部分暴露。以此方式，密封材料的量可被减少而不会剧烈影响最终封装的稳定性。此外，如果最顶层芯片的顶面或背面包含标识信息，则封装可形成为使此信息不被密封材料覆盖并且可被用户容易地查看。
如先前所述，芯片和管芯叠装芯片电附连到引线框以便于向芯片提供电力。除了诸如倒装芯片或引线接合芯片的芯片之外，其它元件也可连接到引线框。这些附加的元件可以是向封装提供增大的支承或稳定性的结构元件。附加的元件还可以是支持芯片或芯片封装的功能的电元件。这些附加元件的示例是无源组件、隔离焊盘、电源环、接地环以及选定布线。芯片封装中的这些以及其它结构或电元件的任何组合在本发明的范围之内。
封装材料可以是任何类型的物质，其可涂敷到管芯叠装芯片或者固化以形成可固化固体。在一实施例中，密封材料可以是围绕芯片并且硬化以获得芯片的液态树脂。密封材料的示例是环氧树脂。密封材料将通常是不导电物质以防止密封材料内的电信号从一个芯片跨接到另一个。
当附加的元件包括电元件时，这些元件可以是直接电连接或间接电连接到引线框。这些附加的元件还可电连接到封装中的一个或多个芯片，并且这些实施例可依赖于所形成的具体芯片级封装。
引线框还可使用本领域已知的生产技术形成。例如，引线框可以使用化学蚀刻、冲压或压印技术形成。
引线框可用诸如导电材料之类的材料的膜涂敷或部分涂敷。该膜可提供引线框与附连到引线框的芯片之间提供增大的电通过量(与没有这样的膜的引线框相比)。在一实施例中，膜由铜或铜合金形成。膜的厚度通常不是关键，尽管膜将不得不足够厚以具有机械稳定性。在一实施例中，膜的厚度大于或等于约0.05mm。
本发明的另一方面提供包括芯片焊盘区域和引线的引线框。引线框具有提供覆盖引线框的密封材料的增加保留的交替可变体。芯片将通常附连到芯片焊盘区域并且电连接到引线。
交替可变体可被结构设计并且配置成提供用于保留密封材料的增大表面积。交替可变体可采用提供密封材料的增大保留的任何类型的形式。例如，交替可变体可以是空穴、凹陷或凹口的形状，其位于引线框上或引线框的一部分上。交替可变体还可出现在形成与芯片的电连接的引线上。
交替可变体可在引线框的任何部分上。例如，交替可变体可在芯片焊盘区域的周边或引线、或它们两者之上。交替可变体还可以是粗糙化芯片焊盘区域、引线或它们两者的周边的形式。
除了为密封材料的改进保留提供交替可变体之外，引线框的表面可以被粗糙化以提供增大的表面积。经粗糙化的表面将便于密封材料粘合到引线框的表面。
线夹可优选地用来代替引线接合以增大电力向芯片的流动并且因而改进芯片的性能。
在本发明的另一实施例中，一种用于形成具有超声接合布线的电子封装的方法是。形成一块部分蚀刻的引线框，其中包括蹼状部分并且通过芯片间隔部分相互分离的引线框具有连续的底面。芯片被附连到引线框上的芯片容纳区域。在各个芯片的端子与相应引线框的电引线部分之间进行电连接。布线被超声地接合到引线框的底面。引线框通过在引线框上，包括隔离引线框的芯片间隔部分上涂敷密封材料来封装。接着执行底面的背部图案化来去除蹼状部分以及芯片间隔部分。经封装的引线框然后在芯片间隔部分上被单片化以形成底面上具有超声接合布线的芯片级封装。
本发明的一实施例提供一种形成芯片级封装的方法。该方法包括形成一块部分蚀刻引线框，该引线框包括蹼状部分、芯片安装区域、多个电引线部分、以及芯片间隔部分。集成电路芯片被附连到膜的第一区域的芯片安装区域。电连接然后在芯片上的一个或多个端子与引线框上的一个或多个电引线部分之间形成。引线框然后通过在引线框和芯片间隔部分上涂敷密封材料封装。引线框的底面然后被背部蚀刻以去除蹼状部分、芯片间隔部分以及芯片安装部分，从而在集成电路芯片下面的整个或相当部分的引线框被去除。置于膜的芯片间隔部分上的密封材料然后被单片化以形成各个芯片级封装。任何类型的任何数目的芯片被附着于部分图案化引线框。
引线框可用预电镀材料进行选择性地预电镀，或者它们可在封装之前用掩模材料在它们的顶侧、底侧、或这两者之上进行掩蔽。
引线框可用任何便利或常规物质进行预电镀。这些物质的示例包括Ni/Pd/Au-底板镀层、浸Ag、Sn/Pb、无铅焊料、浸锡化学镀镍、银(Ag)以及Au(金)底板镀层。
引线框还可用任何便利或常规掩模物质来掩蔽，诸如可印刷墨、制版墨、环氧树脂墨、或者有机物质。
预电镀材料或掩模材料可以在任何适当时间，诸如在背部图案化之后从引线框的底部去除。
引线框可以由本领域已知的任何适当物质形成。例如，引线框可以包括铜或铜合金的膜、或者另一金属或金属合金的膜。
如先前所述，集成电路芯片被附连到引线框的芯片安装区域。芯片可用粘合剂或者其它本领域已知的能触知或固定物质附着。例如，粘合剂可以是树脂、环氧树脂、焊膏、或者带。
引线框可使用例如通过化学蚀刻、压印或精压之类的常规工艺形成。
芯片可使用诸如通过引线接合之类的适当电连接手段连接到引线框。
在进一步的实施例中，本发明的方法允许在芯片安装区域管芯叠装多个芯片。例如，该方法可包括将一个或多个第二芯片管芯叠装到附着于引线框的集成电路芯片的顶部上。这些第二芯片可电连接到引线框，或者附着于引线框的集成电路芯片，或者它们两者。这些连接方法的组合是可能的。第二芯片还可以相互电连接。
本发明的另一方面提供部分图案化的引线框以用于制造电子封装。
部分图案化的引线框可由具有顶面和底面的膜构成。该膜可具有顶面，其具有(a)从顶面部分图案化但不完全穿到底面的第一区域，以及(b)未从顶面部分图案化的第二区域。第二区域可形成用于支承集成电路(IC)芯片的芯片焊盘区域和用于提供到IC芯片的电连接的多个电引线。芯片焊盘区域和多个电引线可经由第一区域连接，但不经由顶面连接。膜的底面还可从底面部分图案化，但不完全通过顶面。
引线框的顶面和底面可以任何特定方式图案化。例如，顶面和底面可以补充图案图案化，以使两个表面在引线框的两侧上具有基本一致的特征。
引线框的底面可被图案化为开口、通道或它们两者。这些开口或通道有利地允许侧向通风孔以及侧向通风，所以在重熔期间没有夹带空气。
本发明的另一方面的进一步实施例提供一种用于形成芯片级封装的方法。该方法包括提供具有(a)从顶面部分图案化但不完全穿到底面的第一区域、以及(b)未从顶面部分图案化的第二区域。第二区域形成(a)用于支承集成电路(IC)芯片的芯片焊盘区域以及(b)用于提供到IC芯片的电连接的多个电引线。芯片焊盘区域和多个电引线可以经由第一区域连接，但不通过顶面连接。
集成电路芯片然后附连到引线框的第一区域的芯片焊盘区域。电连接然后在芯片上的一个或多个端子与引线框上的一个或多个电引线部分之间形成。引线框然后通过在引线框和芯片间隔部分上涂敷密封材料来封装。引线框的底面然后被背部图案化以去除蹼状部分和芯片间隔部分。芯片焊盘区域的底面的小部分还被去除以形成通过芯片焊盘区域的一个或多个通道。这些通道有利地允许侧向通风孔和侧向通风，所以在重熔期间没有夹带空气。置于引线框的芯片间隔部分上的密封材料然后被单片化以形成各个芯片级封装，其为后续使用作好准备。
芯片焊盘区域的通道在整个芯片焊盘区域的长度上延伸，或者它们可在芯片焊盘区域的一部分上延伸。这些通道可以是开口(hatching)或其它类似结构的形式。
本发明的另一方面提供在电子封装的制造中使用的部分图案化的引线框。引线框由具有顶面和底面的膜构成。该膜从顶面部分图案化，但是不完整地穿到底部。膜还从底面部分图案化但不是完全穿到顶面。顶面上的图案化比底面上的图案化更深。所得引线框在其顶部具有相比其底部更深的图案化。双面蚀刻允许引线框的各部分具有降低厚度，这些部分将最终被去除并且因而流线化所得电子封装的处理以及制造。
本发明的另一方面提供一种具有带有通道的底面的芯片级封装。芯片级封装包括一个或多个经封装的计算机芯片、以及用作气孔以在重熔期间减少或消除夹带空气的通道。
附图简述
图1a是根据现有技术的具有引线和芯片焊盘区域的常规引线框的示图。
图1b是根据现有技术的图1a的常规引线框的示图，示出了芯片与芯片焊盘的附连、以及芯片上的端子与引线的引线接合。
图2a是根据现有技术的经引线接合和有引线(具有引线)的近似芯片级封装(CSP)的截面图，示出了通过引线与下一级封装的连接。
图2b是根据现有技术的经引线接合和无引线(不具有引线)的近似CSP的截面图，示出了通过焊料凸块或焊球与下一级封装的连接。
图2c是根据现有技术的经倒装芯片和有引线的近似CSP的截面图，示出通过引线与下一级封装的连接。
图2d是根据现有技术的经倒装芯片和无引线的近似CSP的截面图，示出了通过焊球与下一级封装的连接。
图3a是根据现有技术的模板型引线框的俯视图，示出了倒装接合芯片与引线框引线的引线接合连接。
图3b是根据现有技术的模板型引线框的俯视图，示出了通过焊料重熔工艺的倒装接合芯片与引线框引线的连接。
图4是根据本发明的用可接合材料在两侧上均匀厚度预电镀的金属膜的截面图。
图5是根据本发明的图4的金属膜的截面图，其中仅顶面上的预电镀层已对应于两个芯片位置被图案化，且每个位置包括芯片焊盘和围绕每个芯片焊盘的引线触点。
图6是根据本发明的已被部分图案化的图4的电镀金属膜的截面图。
图6a是示出根据本发明的部分图案化的引线框的矩阵的俯视图。
图6b和6c示出6a中所示的矩阵中的引线框的逐步放大俯视图。
图7a是根据本发明的图6的部分图案化金属膜的截面图，其中芯片已被附连到两个芯片位置的每一个上的芯片焊盘。
图7b是根据本发明的示出包括环氧树脂或焊料的附连物的芯片与芯片焊盘之间的结合处的放大图。
图8是根据本发明的图7a或7b的芯片附连金属膜的截面图，其中每个芯片上的端子已被引线接合到在每个芯片位置上所形成的引线框的引线部分。
图9是根据本发明的图8的引线接合引线框的截面图，其中包括芯片的金属膜的顶面以及引线接合已被密闭地密封在密封材料中。
图10是根据本发明的图9的密闭密封的封装的截面图，该封装已从背侧蚀刻以去除各个引线框的第一区域以及膜中的芯片间隔区域。
图11是根据本发明的形成两个独立封装的两个近似芯片大小的部分图案化的封装的截面图，其中密封材料已在芯片间隔区域中被单片化。这些封装可使用铝线、铜线焊球接合技术、或者使用任何其它便利的接合技术来超声接合。
图12a是根据本发明的图11的单片化封装之一的俯视图，其示出芯片、将芯片端子连接到引线触点的触点和布线、以及具有引线接合的触点之一的放大截面。
图12b是根据本发明的芯片焊盘与触点之一之间的区域的截面图，其示出使用与模制材料接触的垂直表面上的“唇缘”以便于提供锚定并防止分层。
图12c是根据本发明的芯片焊盘与触点之一之间的区域的截面图，其示出使用与模制材料接触的垂直表面上的不同形状空穴以便于提供锚定并防止分层。
图13a-13f是根据本发明的可用来为图12b和12c中所示的垂直表面上的模制材料提供锚定手段的各种空穴的示图。
图14是根据本发明的归纳形成部分图案化封装的各种工艺步骤的流程图。
图15a是根据本发明的示出具有外围I/O配置的封装的俯视图、侧视图和仰视图的示图。
图15b是根据本发明的示出具有I/O焊盘的阵列配置的封装的俯视图、侧视图和仰视图的示图。
图16是根据本发明的图4的金属膜的截面图，其中仅顶面上的预电镀层已对应于两个芯片位置被图案化，且每个位置包括芯片容纳区域和围绕每个芯片容纳区域的引线。
图17是根据本发明的已被部分图案化以形成蹼形引线框(即蹼状结构)的图16的电镀金属膜的截面图。
图18是根据本发明的示出倒装芯片(FC)结合的芯片结合引线框(FCL)的截面图。
图19是根据本发明的图18的FCL的截面图，其中包括芯片的金属膜的顶面已被密闭地密封在密封材料中。
图20是根据本发明的图19的密闭密封的封装的截面图，该封装已从背侧蚀刻以选择性地去除各个引线之间以及各个凹入芯片容纳区域之间的蹼状部分。
图21是根据本发明的已从图20的封装单片化的两个近似芯片大小的部分图案化的封装的截面图。
图22a是根据本发明的图21的单片化封装之一的俯视图，其示出芯片以及引线且芯片端子连接到引线的端部，引线的端部又连接到下一级的封装。
图22b是根据本发明的倒装芯片与与下一级封装的连接之间的区域的放大截面图，示出了引线的两个端部。
图23是根据本发明的归纳形成支承倒装芯片的部分图案化封装的各工艺步骤的流程图。
图24a和24b示出根据本发明的两个近似芯片大小的部分图案化封装的截面图和仰视图，该封装已被单片化、并且然后设置有用于连接到下一级封装以形成ELGA型封装的岸栅阵列连接器。
图25a和25b示出本发明的进一步任选实施例，其包括本发明的引线框封装与下一级封装的引线接合。这些附图示出图24a和24b的封装使用铝线(图25a所示)或者使用铜线焊球接合技术(图25b所示)超声接合。铜线焊球接合技术可用来将倒装芯片封装连接到引线框。
图26a和26b是本发明实施例的立体图和截面图，其中多个芯片管芯叠装以形成半导体封装。
图27a-27c是本发明实施例的立体图和截面图，其中芯片焊盘凹入以允许经改进的管芯叠装以及封装高度的降低。
图28a和28b示出根据本发明实施例的具有凹入的芯片焊盘区域和管芯叠装芯片的引线框的立体图。
图29a-29c示出具有根据本发明的一方面的芯片焊盘锁定部件形式的交替可变体的引线框的立体图。
图30a-30d示出根据本发明一方面的若干实施例的具有交替可变体的若干类电引线的俯视图和侧视图。图31a和31b示出根据本发明的另一实施例的电引线的俯视图和侧视图，其中引线框或引线的表面已被粗糙化。
图32a-32e示出根据本发明的另一方面的设置在电引线上的若干类交替可变体的立体图。图32f示出根据本发明的另一方面的电引线的俯视图和侧视图，其中引线框的表面已被粗糙化以提供密封材料的经改进粘附性。此表面粗糙化可与本发明所给出的交替可变体组合进行。
图33a-33b示出本发明的实施例的一方面，其中线夹被用来代替引线接合以改进芯片的功率能力。
图34a-34f示出部分图案化引线框的实施例，在该引线框中芯片容纳区域不存在，并且芯片被直接放置在引线框上。在后续管芯附连、引线接合、封装、以及背部图案化和修整步骤之后，引线框在芯片下面的部分被去除。此修整步骤将暴露用来将芯片附着于引线框的不导电粘合剂(诸如环氧树脂材料或带)。
图35示出经由图34a-34f所示的工序制备的芯片级封装的仰视图。
图36a提供图34f中所示的芯片级封装的截面图。图36b提供本发明的另一实施例的截面图，其中芯片级封装包括多个管芯叠装的引线接合芯片。
图37a示出其中在任何芯片被附连到引线框之前顶面和底面已被部分图案化的引线框。图37b示出芯片已与之电连接的图37a的引线框，并且该引线框在背部图案化和单片化之前已被封装。
图38示出包括多个管芯叠装的引线接合芯片的芯片级封装，其中管芯焊盘的底部已被开口以提供通风。
详细描述
现在将参考附图描述本发明，其中相同的附图标记指示相同的元件。图4-15b和图16-24b示出形成引线数目与近似芯片级封装(CSP)相当的部分图案化的引线框封装的不同实施例。本发明的方法改进生产线的自动化以及从中制造的封装的质量和可靠性。这通过执行制造工艺步骤的主要部分、并且部分图案化的金属膜在一侧形成网状的引线框来实现。与常规穿通的模板型的引线框对比，用在本发明中的引线框在一侧被部分图案化并且在另一侧上是实心且平坦的。此构造通过机械和热力学手段改进，并且在芯片附连、引线接合、以及封装工艺期间没有扭曲或变形地进行。下表面可被加以掩模或者以其它方式标记以绘出最终将通过背部蚀刻去除的区域的轮廓。在芯片附连和引线接合工艺步骤完成并且芯片和引线接合被附着并密闭地封装在模制材料中之后，在不被下表面的选择性预电镀层掩蔽的区域中下表面被部分地蚀刻穿膜，以使引线触点与芯片焊盘隔离并且相互隔离。随后，所得经封装的封装被单片化而无需切入任何附加金属。
更具体地，图4-15b示出用于引线接合芯片的部分图案化的引线框的形成以及使用其形成ELP型电子封装的方法。另一方面，图16-22示出用倒装芯片的部分图案化的引线框的形成以及使用其形成ELPF型电子封装的方法。一种使用本发明部分图案化的引线框形成ELGA型电子封装的方法也结合图24a和24b进行描述。
图4是优选为金属(优选为铜)片的膜的截面图，该膜不仅形成为引线框，而且也在确保形成引线框的工艺步骤期间用作稳定的载体。金属条的厚度等于或大于约0.05mm。在另一实施例中，该厚度可在约0.05到0.5mm的范围内。
形成引线框通常涉及切穿金属条，类似切割模板，且然后对非常纤细的指型引线起作用。为了将这样纤细的结构压紧到位，可使用真空夹盘。然而，常规真空夹盘通常不适于为这样纤细的器件提供吸力并且引线框必需通常在外围夹紧。用于此目的的任何索具从一种类型和大小的引线框到另一种必需进行改装。然而，本发明消除了此改装步骤。因为部分图案化的引线框的下表面是实心且连续的，所以常规真空夹盘可在加工期间将该引线框容易地保持到位。此外，可适应各种工业引线框的一种大小的金属条可普遍用于引线框的制造中。芯片附连和引线接合的后续工艺步骤可在引线框上有小得多的应力和应变形成的情况下完成。具有纤细得多的几何形状的引线框可容易地制造，因为引线通过蹼状结构被结合在一起并且相互不分离直到最终步骤。
在引线框上形成各种图案可以各种方式完成。一种方法可以是将图案压印/精压到金属上。其它方法可包括化学或电化学研磨和放电加工(EDM)。另一方面，优选光刻图案化，其是半导体制造的支柱。在本发明中，图4中所示的金属条(100)在光刻图案化之前在前(或上)侧以及背(或下)侧预电镀。正面和背面之一或两者可分别使用能接合以及可焊的材料进行预电镀。在一实施例中，正面用诸如Ni/Pd/Au底板镀层或银之类的可接合材料进行预电镀。在另一实施例中，背面使用诸如Sn/Pb、无铅焊料、浸锡化学镀镍或金底板镀层进行预电镀。在另一实施例中，背面使用与顶侧相同的材料进行预电镀，其然后可以在背部图案化期间起抗蚀膜作用。该抗蚀膜类电镀层可稍后在最终修整之前被剥去。预电镀可以在稍后步骤中执行(如果需要这样的话)。
在下一步骤，预电镀的前侧(110)被光刻图案化以形成对应于芯片焊盘(115)和围绕芯片焊盘区域的电触点(113)的区域。电触点(113)可表征为引线的端部，引线通过形成蹼状结构的中间凹入部分的第一区域连接到芯片焊盘区域(115)。这些中间凹入的蹼状部分在金属膜(100)从背部被蚀刻的稍后时间被去除，以使端部和芯片焊盘部分相互隔离。包括芯片焊盘(115)和周围触点(113)的区域有时称为芯片位置(chip site)。多个芯片位置可以在绕到线轴上的一连续卷铜片上形成，以使包括一个或多个芯片位置的引线框的形成容易地自动化。图5示出两个芯片位置，其将形成为两个相应的引线框，这些引线框又将是将由其形成的两个封装的一部分。
为图5中所示的两个芯片位置所示的图案然后通过蚀刻转移到膜条(100)。如图6所示，本发明的主要特征是蚀刻仅部分地穿透金属的厚度执行，这在此称为部分图案化。部分图案化在膜的第一区域中执行以形成使每个引线框的引线触点(113)的芯片焊盘(115)连接的蹼状结构(130)。该第一区域还使引线框在膜的芯片间隔部分(street portion)(136)相互连接。
如图6a-c所示，矩阵或这些引线框(例如，16x16)可在框/窗口膜(138)中形成。图6b和6c示出第一区域包括使各个引线框的芯片焊盘和引线触点连接的蹼状结构(139)。第一区域还在膜的芯片间隔部分(136)使多个引线框相互连接。
在一实施例中，部分图案化可从膜厚度的25％改变到90％。然而，部分图案化实际上可以是任何百分比的膜厚度，并且部分蚀刻的量可以通过考虑影响可制造性参数的各种因素来确定，这些因素包括灵活性、刚度以及热厚度(或导热性)。引线触点区域(113)和芯片焊盘区域(115)的横向尺寸可以基于给定芯片大小和引线接合或其它连接介质所需的小型化的程度决定，引线接合或其它连接介质可用于给定封装内或下一级封装的封装之间的级间或级内连接。尤其应注意，对引线框的纤细部件以及尺寸稳定性的可制造性因素现在依靠指型引线的蹼状结构变得较不重要。
如图7所示，芯片(140)接着使用诸如环氧树脂(150)之类的任何便利手段附连到芯片焊盘区域。芯片与示出附连的芯片焊盘之间的结合处根据本发明包括环氧树脂或焊料。环氧树脂(150)可填充有导电颗粒以增强芯片的冷却。作为替换，代替环氧树脂(150)的焊膏(150’)也可用来提供芯片与芯片焊盘之间的更坚固接合、以及对周围环境的更有效的冷却路径。环氧树脂被固化并且如图8所示，在芯片附连之后，线(160)使用已知的引线接合技术接合到端子(145)和相应的引线触点(113)，如图8所示。因为根据本发明形成的引线框具有坚固固定并且诸如由真空夹盘(未示出)压紧在平面上的实心、连续的背侧，所以引线的蹼状结构不在引线接合期间摆动或弹跳。此导致出色接合，这改进最终产品的可靠性。虽然背侧是实心且连续的，但是它仍可具有关于背部蚀刻将在哪里进行的指示符。例如，背侧可以具有破裂或可以是膜的表面的一部分的其它指示符，或者背侧可用预电镀材料(120)掩蔽以绘出将被背部蚀刻的预定区域的轮廓。例如，预电镀材料(120)可以在区域(113)之下被掩蔽以指示引线框的相应部分将在稍后蚀刻期间被保留并且在区域(130)和(136)之下的区域将被去除。
在图9中，在使芯片与相应触点连接之后，金属膜的前侧上的所有组件然后例如通过树脂被密闭封装在模制材料中。密封材料(170)在膜与包括引线框和它们相关联的线(160)、芯片(140)和触点(113)以及蹼状结构(130)和芯片间隔部分(136)的所有暴露表面上形成。当所得模制封装被举起时，干净的背侧现在可供进一步加工。通常遇到的到封装下侧上的覆盖区域的模制毛刺(mold flashing)问题使用此公开的方法消除。干净的背侧可以已预先用将便于后续加工或蚀刻的物质电镀。
如图10所示，引线触点(113)和芯片焊盘(115)现在可以通过蚀刻第一区域的蹼状结构(135)穿透封装背侧以容易地相互隔离来形成它们自己的岛。此时，芯片间隔部分(136)也被背部蚀刻。使用诸如可印刷墨或有机材料之类的物质的预电镀层(120)可用作掩模或抗蚀膜以形成所需底部部件(123、125)。在其它实施例中，有机材料可用来代替金属或可焊材料作为蚀刻掩模。有机材料可以在背部蚀刻之前在任何便利步骤被印刷或涂敷到引线框上。
背部蚀刻继续直到到达模制材料。用于背部蚀刻金属的蚀刻方法可与用于前侧的不同。根据从前侧执行的部分蚀刻的程度，用于背侧的蚀刻时间可与用于前侧的不同。因而，部分蚀刻引线框的最初形成可以是定制的以适合最终封装的自动化、质量、可靠性以及功能性的制造需求。起化学抗蚀膜作用的底部的预电镀层(120)可被剥去以暴露金属条(100)。
为保护材料且便于安装到印刷电路板，诸如化学镀Ni/浸Au、浸Ag、浸Sn之类的可焊材料、或者其它这样的材料可被电镀到金属条(100)。认为适合特定环境时，任何预电镀层可保留或剥去。
作为最终步骤，引线框之间的芯片间隔部分(136)上的密封材料(170)被单片化以形成如图11所示的两个单独封装。这按多种方式实现，包括锯切片、喷水切割、激光切割或其组合、或者特别适用于切割塑料的其它技术。换言之，不再切开金属并且因此没有与切割塑料和金属的组合相关联的分层或其它问题。这与其中芯片间隔之间的桥接金属必需在封装被单片化的同时被切割的常规封装作比较。多次地，当同时切割金属和塑料时，金属芯片中的一部分可以是短路线路和触点，从而导致锯条上非期望的以及不可预知的损耗。如图6a所示，此方法还可应用于由引线框矩阵制造大量的封装。
透过单片化ELP的密封材料俯视的截面俯视图在图12a中示出。图12b显示封装的在芯片与触点之一之间的角落的放大图，所述角落包括原始金属条(100)的一部分、预电镀以形成可接合层(113)的顶面、以及预电镀以形成可焊层(123)的底面。在图12b中，“唇缘”在触点和芯片的角落上示出。触点(113)和芯片(140)示为在它们自己的岛上相互隔离，但是仅通过已引线接合的线(160)相互连接。
在封装的下侧上的可焊预电镀表面(120)如未剥离则现在可以用于若干用途。第一，到芯片焊盘(140)的背部(125)的直接外部通路为冷却提供附加的热路径。第二，近似芯片级封装(CSP)的覆盖面积内的触点(123)使得可能在下一级封装中安装紧密间隔的封装，并且因此提升同一区域的性能。
本发明的另一方面提供一种减小模制材料与它附连的表面之间的分层的可能性的方法。这通过半蚀刻芯片焊盘和触点区域周围的边缘以形成诸如图12b中的附图标记(105)所指的凸缘或“唇缘”来完成。还可能形成图12所示的不规则形状的空穴(107)以增强与模制材料接触的表面的互锁机制。各种其它空穴的放大图也在图13a-13f示出，并且这些表面增强的形成可被容易地结合入从前侧的部分蚀刻。这对于从背侧蚀刻不是必要的，因为模制材料仅封装从前侧部分地形成的表面。
图14将本发明的方法归纳为以引线框从前侧部分蚀刻入(200)金属条开始并且以使用形成所需芯片焊盘和周围触点的方式背部图案化蚀刻(250)同一金属条结束。芯片附连(210)、环氧树脂固化(220)、引线接合(230)、以及封装(240)的中间步骤都在机械上和热力学上稳定的引线框上实现，因为引线仍通过金属膜中的部分蚀刻的蹼状或蹼状结构上的中间凹入部分的第一区域连接。也重要的是需要注意，仅在封装的所有组件已被保护在密封材料中之后，中间凹入部分的第一区域通过背部图案蚀刻(250)被去除、并且使得外围触点和芯片焊盘相互分离以供适当隔离。在最终步骤之前，可以执行剥离预电镀层(120)以及涂敷可焊材料。因此，不需要在单片化(260)成单个近似芯片级封装期间切开任何金属。
本发明的方法可用于形成各种封装，诸如用于电子封装的阵列型引线框。阵列型封装(400)的俯视图在图15b中被视为与图15a所示的标准外围型封装(300)相邻。虽然附图标记(305)指外围排列的芯片端子，但是附图标记(405)指可同轴或交错配置的阵列型排列的端子。使用如由附图标记(310)和(410)指示的所公开的部分图案化发明形成这两种封装。在阵列型ELP中，内引线(440)和外引线(445)被示出。这两种封装被封装在模制材料(320)或(420)中。背部图案化蚀刻以隔离触点和芯片由(330)和(430)指示。附图标记(450)描绘接地环部件，其被蚀刻到与模子相同的水平。附图标记(460)指ELP的俯视图上的阵列型输入/输出配置。
附图16-24b中所示的第二实施例公开了一种形成部分图案化的VFQFP-N型引线框的方法，该方法尤其适用于大规模生产的FC电子封装。作成容纳倒装芯片的引线框将在下文中被称为FCL以将它与常规引线框区别开。这是因为，与常规引线框不同，FCL更坚固并且更适于自动化生产线，如以下所述。
FCL也是蹼状结构，与常规通用的穿通、模板型引线框相反。蹼状FCL的前侧具有包括部分图案化引线的凹入部分，而背侧是实心且平坦的。这在制造工艺期间提供机械刚度来没有扭曲或变形地执行。在完成封装的芯片附连和密闭密封之后，背侧被蚀刻以使引线触点相互隔离。去除预电镀层、或者使用其它可焊材料重新电镀可通过化学镀或浸入工艺完成。随后，所得经封装的封装被单片化而无需切入任何附加金属。因而，将显而易见的是诸如具有VFQFP-N封装的具有更纤细几何形状的FCL可容易地制造，因为引线通过蹼形、或蹼状结构被保持在一起并且相互不完全分离直到最终的单片化步骤。
类似已公开第一实施例的部分图案化引线框，第二实施例的FCL也由金属片、优选如图4所示的铜膜形成，其中正面和背面被预电镀，或者如先前所述电镀可被推延至稍后步骤。(注意，由于这两个实施例的工艺步骤是类似的，所以附图标记已按需保持为相同，除了用质数指示第二实施例的那些标记。相同的附图标记(100)已出于一致性保持用于这两个实施例的金属膜。然后，预电镀前侧(110’)被光刻图案化以形成芯片容纳区域(115’)、围绕芯片容纳区域的引线部分(113’)、以及其它中间区域(117’)。在以下公开的后续工艺步骤，引线的一个端部将连接到PC的端子，而另一个端部将连接到下一级封装。与具有引线接合芯片的芯片位置类似，包括芯片容纳区域和周围引线的区域有时称为芯片位置。包括多个芯片位置的多个引线框可以在绕到线轴的一连续卷铜片上形成，以容易地使包括一个或多个芯片位置的引线框的形成自动化。图16示出两个芯片位置，其将形成为两个相应的引线框，这些引线框又将是将由其形成的两个封装的一部分。
图16中所示的两个芯片位置的图案然后通过经由蚀刻的部分图案化转移到金属膜(100)。图17中所示的部分图案化可最多达二分之一、四分之一，或者可最高达金属条的厚度的任何比率，并且部分蚀刻的量可以通过考虑影响可制造性参数的各种因素来确定，执行因素包括灵活性、刚度以及热厚度(或导热性)。引线触点区域(113’)和芯片区域(115’)的横向尺寸可基于给定芯片位置所需的小型化程度来确定，包括芯片大小以及可用于在给定封装内或在下一级封装的封装之间的级间或级内连接的引线。尤其应注意，对引线框的纤细部件以及尺寸稳定性的可制造性因素现在凭借指型引线的蹼状结构变得较不重要。
倒装芯片(FC)(130’)然后被倒装，以使芯片前侧上的端子(135’)搁在如图18所示的引线的一个端部上。在稍后步骤，引线的相反端将被形成为用于连接到诸如卡或板之类的下一级封装的电触点。然而，首先，如图18所示的组装在蹼状引线框结构上的芯片通过如在本领域中实践的芯片结合炉传送。焊球重熔以使重熔受BLM限制，从而形成焊柱。因为根据本发明形成的引线框具有坚固密封并且压紧在平面上的实心、连续的背侧，所以引线的蹼状结构不在芯片结合炉周围摆动或弹跳，从而获得出色的芯片结合。结果，所公开的方法改进了最终产品的可靠性，即VFQFP-N型封装的可靠性。
在芯片结合之后，芯片与在原始金属膜的前侧上的部分图案化引线一起然后例如通过树脂被密闭封装在模制材料中，如图19所示。密封材料(140’)形成在所有暴露表面周围，所有暴露表面包括引线(113’)的、焊球(135’)周围的、芯片下面的、沿凹入芯片容纳区域(115’)的垂直壁的暴露表面，以及凹入区域(117’)的垂直壁的暴露表面，除了坚固压紧在平面上的金属条(100)的未蚀刻、实心且平坦的背侧之外。当所得模制封装被举起时，干净的背侧现在可供进一步加工。通常遇到的到封装的下侧上的覆盖区域的模制毛刺问题也在此实施例中被消除。
引线(113’)现在可以容易地通过与在工艺开始时从前侧部分蚀刻的图案对准地图案化穿过封装的背侧来相互隔离。背部蚀刻继续直到到达模制材料。这在图20中示出，其中引线框的蹼状部分，即区域(111’)和(119’)被去除以使芯片区域(115’)相互断开，并且引线(113’)相互断开。用于背部图案化金属的蚀刻方法可以或可以不与用来从前侧部分蚀刻的方法相同。此外，根据从前侧执行的部分蚀刻的程度，从背侧蚀刻的时间可与用于前侧的不同。因而，部分蚀刻引线框的最初形成可以是定制的以适合最终封装的自动化、质量、可靠性以及功能性的制造需求。起化学抗蚀膜作用的底部的预电镀层(120)可以被剥去以暴露金属条(100)。为保护材料且便于安装到印刷电路板，诸如化学镀Ni/浸Au、浸Ag、浸Sn之类的可焊材料、或者其它材料可被电镀到金属条(100)。
作为最终步骤，为了说明本发明，具有两个封装芯片位置的图20的封装接着被单片化成单个近似芯片级封装(CSP)，其更多是VFQFP-N型封装，如图21所示。单片化图案化引线框封装的俯视图在图22a中示出，其中引线(113’)被示为相互隔离、并且连接到芯片(130’)的下侧上的焊球(135’)。图22b示出封装的在芯片与连接到可设置在卡或板(150’)上的外部触点(145’)的引线之一之间的角落的放大图。预电镀表面(120’)已制备成结合到如同一附图所示的下一级的触点。如在此时认为适合或合乎需要时，预电镀或掩模可被保持或去除。预电镀或掩模还可在工艺中的其它时候被去除，从而适于各种环境。此外，引线(113’)的下侧(114’)被暴露到周围环境，从而提供增强的冷却。在一些情况中，涂层可被涂覆到下侧(114)以在板安装期间减少潜在短路的可能性，尤其对于细距应用。
如以前公开的相同技术可用来通过在蹼状引线框的凹入区域(115’)和(117’)的垂直壁上结合图13a-13f的不规则形状的空穴，防止密封材料从FCL的表面分层。这些表面增强的形成可容易地结合入从前侧的部分蚀刻。这对于从背侧蚀刻将是不必要的，因为模制材料仅封装从前侧部分形成的表面。
图23将本实施例的方法归纳为以引线框从前侧部分蚀刻入(200’)金属条开始并且以使用形成所需芯片容纳区域和周围引线的方式背部图案化(240’)同一金属条结束结束。FC放置(210’)、FC芯片结合(220’)、以及封装(230’)的中间步骤都在机械上和热力学上稳定的FCL上实现，因为引线仍然通过金属膜中的部分蚀刻的蹼状结构连接。也重要的是需要注意，仅在封装的所有组件已被保护在密封材料中之后，引线的蹼状部分通过背部图案化蚀刻(240’)被选择性地去除、并且使得引线相互分离以供适当隔离。因此，不需要在单片化(250’)成单个近似芯片级封装期间切开任何金属。
类似于在本文中公开的使用焊料凸块的外围组的方法，本发明的方法可用来形成各种封装，诸如阵列型的多个部分图案化引线框，其中焊料凸块的区域阵列可同时芯片结合到有倒装芯片的引线框。此外，部分图案化的引线框本身的阵列可以同时形成，并且然后同时FC结合，随后阵列被单片化成多个分离的VFQFP-N型封装。此外，每个所得CSP然后可设置有在封装之下用于阵列型结合到下一级封装的焊料凸块、焊盘、或者其它电学连接以形成如图24a和24b所示的具有岸栅阵列的蚀刻引线框封装或ELGA型封装。在图24a，示出芯片焊盘(135’)在引线(145’)上形成的横截面视图。在背部图案化之后，引线(145’)相互电隔离以结合到下一级封装。所暴露的底面(145’)可通过浸锡浸渍或化学镀镍电镀使用任何数目的可焊材料来毛刺修整。具有用于电连接的阵列图案(145’)的ELGA封装的底面(111’)在图24b中示出。
焊料凸块可以是诸如铜柱凸块之类的金属柱凸块的形式，其中每个凸块由约75微米高，且具有焊料(或无铅)帽而导致约100微米总高度的Cu杆状物构成。在使用铜柱凸块时，“焊料凸块”可以是“焊料帽”。铜柱的使用给予芯片表面UBM与板触点之间大于50微米的间隙，并且能使塑料密封材料自由地流动并覆盖倒装芯片下面的裂缝。
因为形成ELP、ELPF或ELGA封装中任何一个的部分蚀刻方法在各制造步骤期间提供鲁棒性，所以其它形式的电子封装也是可能的。一种这样的形式包括本发明的引线框封装到下一级封装的引线接合。因为引线本身的脆性超声接合技术不能用于常规的引线框，除非它们附连到固体基板以提供稳定性和强度。相反，部分蚀刻引线框依靠它们的蹼状结构是稳定的。部分图案化的引线框的未蚀刻和预电镀底面(120’)提供固体接合区域或柱，以有效地将超声能量用于ELP或ELPF的块或条上的铝线楔接合。因此，根据本发明的另一方面，铝线(121)如图25a所示地超声附连到一块或条部分蚀刻引线框的底面。线直径范围在约0.001英寸到0.020英寸之间，且后一直径表示带(ribbon)而非线。条然后被封装、背部图案化并且单片化以形成各近似CSP。超声接合是合乎需要的，因为它避免暴露到由焊球栅阵列型封装经历的球焊接合温度，因此有改进的可靠性。如图25b所示，还可应用铜线球焊接合。将理解，图25a和25b所示的CSP可以是ELP和ELPF中的任何一个。
本发明促成电子封装制造工艺中的多个附加优点。例如，在背部蚀刻之后以及单片化之前，封装块将固有地为拉伸测试作好准备而封装仍排列成块。这与将封装处理成各个单元相比提供显著优点。在封装排列成块时拉伸测试它们改进测试的可靠性。
本发明还能使制造商生产具有可倍增给定封装的I/O容量的两或三行交错引线的封装。引线框的平坦连续底面使通用组装设备能使用，其不需要对每一应用改装，并且其对自动化是完全灵活的。例如，在2x2到12x12封装块之间的处理不需要任何机械上的变化。此外，本发明容易地促进对每个引脚具有“间隙”的封装的构造(例如，在引脚的表面模制体的底部之间为2密耳)。芯片封装连接到诸如板之类的下一级封装时，该间隙提供附加的优点。
图26a和26b示出本发明的一方面的实施例，其中两个芯片(505，510)管芯叠装在引线框(500)的芯片焊盘(515)上。下芯片(505)(即附着于芯片焊盘容纳区域(515)的芯片)电连接到围绕芯片焊盘区域(515)的内组(520)电引线。上芯片(510)(即附着于下芯片(505)的顶部的芯片)电连接到围绕芯片焊盘面积(515)的最外组(525)引线。芯片用密封材料(530)封装，其保护芯片和线以防损伤。虽然图26a和26b中的芯片(505、510)是引线接合芯片，但是与本发明一致，芯片中的一个或多个还可以是倒装芯片。下管芯叠装芯片(505)在尺寸上大于上芯片(510)。虽然下芯片和上芯片在图示中相互不电连接，但是在某些实施例中，这些芯片可例如通过从一个芯片到另一个的线进行电连接。形成电连接的步骤可以通过将各种芯片的端子连接到从引线框延伸的电引线的端部实现。
图27a-27c示出本发明的实施例，其中芯片焊盘区域(550)凹入以允许改进的管芯叠装以及封装高度的降低。在图27a-27c中，三个芯片(555、560、565)管芯叠装以形成芯片封装。如可从图27a所见，芯片焊盘区域(550)的内部已被去除使得只有正方形的外环。芯片(555)被放入并且附连到此芯片焊盘区域。虽然在图27a-27c中示出了三个管芯叠装芯片(555，560，565)，但是与本发明一致，可以有任何数目的管芯叠装芯片。在图27a中，凹入芯片焊盘区域(550)的内部被示为引线框的顶面。即，仅芯片焊盘区域的外正方形环(575)已被沉积在引线框的顶部，并且芯片焊盘区域的整个内部(550)没有被沉积或者从引线框去除。在本发明的替换实施例中，薄材料层被沉积在芯片焊盘区域的内部、或者芯片焊盘内部区域的一部分被去除。在这些实施例中，芯片焊盘区域的内部将高于引线框衬垫，但仍然低于芯片焊盘区域的外部，从而为芯片的附连提供凹入的芯片焊盘区域。
虽然在图27a-27c中，最大的芯片(555)位于管芯叠层的底部，且最小的芯片(565)位于顶部，但是芯片可放置成使最大的在顶部且最小的在底部。最顶层的芯片(565)被示为连接到中间芯片(560)，并且连接到引线框(570)上的电引线(580、585)。中间芯片(560)被示为连接到最顶层的芯片(565)，并且连接到引线框上的电引线。覆盖管芯叠装芯片(555、560、565)的密封材料(590)防止芯片封装的线在操作或安装期间被损坏。各种芯片使用诸如导电或不导电环氧树脂之类的粘合剂或使用绝缘材料附连到引线框(550)或者相互附连。
图28a和28b是具体化本发明的若干方面的引线框的立体图。图28a示出在芯片被附连到引线框之前的具有四个芯片焊盘区域(605，610，615，620)的引线框(600)。图28b示出在芯片(625，630，635，640)已附连到芯片焊盘区域(605，610，615，620)并且电连接到引线框之后的同一引线框(600)。
图28a将引线框(600)示为具有用于引线接合芯片的三个芯片焊盘区域(610，615，620)以及用于倒装芯片的一个芯片焊盘区域(605)。用于引线接合芯片的三个芯片焊盘区域中的两个(615，620)没有凹入而剩余的芯片焊盘区域(610)是凹入的。这些芯片焊盘区域(610，615，620)在芯片焊盘区域的外周边上包括形状为“T”的锁定区域形式的交替可变体(645)。这些锁定部件为密封材料(650)粘附提供附加的表面积，并且提供一种用于保持密封材料而不使密封材料侧向移动的方法。
在图28b中，没有凹入的芯片焊盘区域(615、620)的每一个支承经由电引线连接到引线框的单个芯片(635、640)。用于倒装芯片(625)的芯片焊盘区域(605)通过电引线床形成，并且倒装芯片(625)被放置在这些引线的顶部以形成电连接。与引线接合芯片(630，635，640)相比，倒装芯片(625)从而在引线框(600)上节省空间。虽然为清楚起见，仅单个芯片被示为附连到引线框上的两个没有凹入的芯片焊盘区域(615、620)，但是在本发明的其它实施例中，可以有一个或多个芯片被放置在这些引线接合芯片或倒装芯片的顶部上。
在图28b中，引线框上的凹入芯片焊盘区域(610)支承多个管芯叠装的引线接合芯片(总称为630)。这些芯片使用诸如导电或不导电粘合剂(例如环氧树脂)之类的粘合剂或者使用绝缘层附连到芯片焊盘区域(610)。凹入芯片焊盘区域(610)的外围包括形状为“T”的锁定区域形式的交替可变体(645)。
图28a和28b中的引线框(600)还具有位于倒装芯片焊盘区域(605)与凹入芯片焊盘区域(610)之间的电引线(通常655)，其还可用于除了计算机芯片之外的其它元件。例如，这些电引线可以是诸如半导体元件、无源组件、电阻器、以及电容器之类的元件，或者其它用来补充芯片封装中芯片功能的非芯片组件。在图28b中，电容器或电阻器被附连到这些电引线。
芯片可逐个地管芯叠装到芯片焊盘区域上并且然后在下一芯片被管芯叠装并电连接之前电连接到引线框。替换地，所有的芯片可被管芯叠装且然后整个管芯叠装组的芯片可以电连接到引线框。在另一实施例中，芯片可以与芯片焊盘区域分离地管芯叠装，并且然后整个管芯叠装组的芯片可以附连并电连接到引线框。
图29a-29c示出可应用于芯片焊盘区域的各种类型的交替可变体的各实施例。在图29a中，交替可变体(705)在芯片焊盘区域(720)的外侧边缘上采用“T”形凹口的形式。在图29b中，交替可变体(710)是位于沿芯片焊盘区域(725)的外周边的空穴或穿孔的形式。图29c示出沿芯片焊盘区域(730)的外周边的凹口的形式的交替可变体(715)。这些交替可变体为封装的芯片封装提供增大的强度和改进的稳定性。
虽然图29a-29c中的交替可变体或锁定部件位于相应芯片焊盘区域(720，725，730)的外围，但是交替可变体还可被置于芯片焊盘区域的其它部分。例如，交替可变体可以在芯片焊盘区域的内部，该芯片焊盘区域的内部将不被芯片覆盖且因此可用密封材料填充。
在图29a-29c中，交替可变体已被示为位于芯片焊盘区域上。在本发明的附加实施例中，诸如在图30a-32f所示的那些，交替可变体可位于位于引线框上的、并且芯片可与其电连接的电引线上。交替可变体还可被同时放置在芯片焊盘区域和引线上。
图30a-31b示出具有交替可变体的电引线的若干实施例的顶视图和侧视图。图30a-30d示出各种类型的引线(735、740、745、750)以及这些引线中的一部分的横截面。图30b示出交替可变体可具有位于引线(740)的内表面(755)中的可接合材料。图31a和31b示出引线(760，765)的表面(770，775)可被粗糙化以供密封材料的改进保留。
图32a-32f示出图30a-31b的各实施例的立体图，这些立体图例示具有交替可变体的电引线的若干实施例。图32a示出具有芯片焊盘区域(805)的引线框(800)。附图的圆圈部分(810)示出具有交替可变体的电引线(815)。图32b-32f例示这些类型的引线。图32b-32d示出与图30a、30c以及30d中示出的那些大致相似的引线(820、825、830)的实施例。图32e示出与图30b所示的大致相似的引线(835)。图32f示出具有沿引线外围的水平凹口形式的表面粗糙化的引线(840)，从而给予引线台阶式的外观。化学或其它类型的工艺可用来获得图32f中所示的表面粗糙化。此表面粗糙化可与引线与芯片和焊盘交替可变体组合应用。
图33a-33b示出本发明的进一步实施例的一方面的截面图，其中线夹(925)被用来代替引线接合以向芯片级封装(935)供电并且从而改进其功率能力。图33a示出使用引线接合芯片(905和910)的实施例，并且图33b示出用于倒装芯片(示为单个芯片907)的实施例。线夹相比引线接合提供显著大量的电力，并且结果使所得芯片封装(935)能有改进的可靠性。线夹还帮助从芯片散热。当使用线夹时，最顶层的芯片将包含用于将电信号传输到印刷电路板的引线。
在图33a中，引线接合芯片(905和910)被放置在芯片焊盘区域(900)上并且经由线(920)电连接到引线(915)。多个线(920)被用来将芯片(910)连接到多行电引线(915)，虽然电连接的数目和类型将取决于具体实施例。在图33b中，倒装芯片(907)被放置在从引线框凸出的电引线(诸如915)上。为便于说明，仅单个倒装芯片(907)在图33b中示出，虽然实际上可以有形成芯片级封装(935)的倒装芯片与引线接合芯片的任何组合。
最高芯片(907和910)的顶面通过线夹(925)电连接到引线框(900)上的一个或多个电引线(917)。在芯片已附连到引线框之后，线夹(925)接合到芯片的顶部。任何便利的手段可用来将线夹接合到芯片。在图33a-33b所示的示例中，导电胶或焊料(930)被用来将线夹(925)附着于芯片(907和910)。线夹(925)可由诸如金属或金属合金之类的导电物质制造。适当导电物质的示例包括铜和银。根据具体实施例，各个线夹可附着于特定芯片，或者整个导电条或板可使用组合方法附着于多个芯片。在后一实施例中，单片化的动作切开导电条或板以有效地获得各个芯片封装。
根据本发明，叠装芯片随后被密封材料覆盖并且在单片化之后获得芯片级封装(935)。
暴露的管芯焊盘通常用来提供芯片级封装与印刷电路板(PCB)之间的电隔离。然而，在某些示例中，暴露的管芯焊盘或芯片焊盘区域不利于芯片或芯片级封装的适当功能。例如，一些印刷电路板设计具有在芯片级封装下面的有源电路，并且如果封装具有暴露的芯片焊盘则这些电路可发生故障。虽然在这些情况中QFN(方型扁平无引线封装)封装的使用可以给出可能的解决方案，但是设计成使用QFN封装的引线框具有多个相关联的组装难点。例如，很难或者不可能使用现有技术生产用于无焊盘引线框的QFN封装，这些方法即是(a)用带，其中引线框通常是地图(模阵列工艺)形式，或(b)不用带，其中引线框是矩阵形式。
为了克服这些困难，用户(a)具有从底部半蚀刻的引线框以使焊盘可在模制期间被嵌入或者(b)在管芯焊盘上有翻转。然而，对于有带地图引线框，存在执行引线接合的问题，因为带将防止加热部件(用于在将半导体引线接合到引线框之前预加热引线框)与焊盘接触。在引线接合之后执行贴带对生产成品率具有负面影响。对于矩阵引线框，加热部件可被设计成具有基架以在引线接合期间支承芯片焊盘区域。然而，此引线框设计具有低容量，并且因此将影响每小时单位产量并且增大生产成本。
在这些情况下，无焊盘ELP可以提供改进的功能性以及降低的故障的可能性。无焊盘ELP可维持高密度设计并且提供更鲁棒的组装工艺。无焊盘ELP实施例具有与ELP芯片焊盘实施例大致类似的构造，但是无需对底部的蚀刻保护。因此，无焊盘ELP实施例不需要对生产线进行剧烈改变。
无焊盘引线框具有半蚀刻的管芯容纳区域而无需底部蚀刻掩模或电镀层。管芯容纳区域相比其它引线框能够容纳更大的管芯大小，并且可以给出需要管芯完全隔离的器件。因为管芯容纳区域是凹入的，所以所得芯片级封装可具有非常低的外形，从而最小化其安装所需的高度。管芯附连材料(或粘合剂)因此将是不导电的以防止短路，并且通常将与模制化合物是同一颜色以提供一致的外观。此外，管芯附连材料或粘合剂应该在背部蚀刻期间是稳定的，以便于防止对芯片级封装的损伤。管芯附连材料可以是本领域已知的任何物质，诸如可固化环氧树脂或诸如聚酰亚胺粘合带之类的带。
图34a-34f示出部分图案化的引线框的实施例，其中芯片焊盘区域或芯片容纳区域不存在、并且芯片被直接附着于将形成引线框的蚀刻膜的底部。在管芯附连、封装以及背部图案化之后，芯片的底部被暴露在芯片级封装中。如图34a所示，部分蚀刻膜不具有凸起的芯片焊盘区域以容纳半导体芯片。
图34a示出已在前侧被部分蚀刻的金属膜(1000)。该膜(1000)可使用将便于诸如引线接合之类的稍后加工的物质来预电镀一侧或两侧。例如，膜的顶部可用诸如NiPdAu、或诸如浸Ag之类的银(Ag)之类的引线可接合物质进行预电镀，并且膜的底部可以是裸露的并且使用相同或另一引线可接合物质进行预电镀。在其它实施例中，有机材料可被用作蚀刻掩模。
膜(1000)在其正面被蚀刻以制备集成电路芯片将稍后与之附连的电引线部分(1005)。膜具有隔离引线框的各部分的芯片间隔区域(1035)，并且经封装的引线框将通过这些芯片间隔区域(1035)单片化以获得各个芯片级封装。芯片安装区域(1010)被蚀刻到膜的正面。这些芯片安装区域(1010)在高度上比引线低。换言之，膜(1000)在引线的区域(1005)中被蚀刻得最少，并且将在引线框的其它部分被蚀刻得最多。
在膜(1000)已制备并且适当蚀刻之后，半导体或集成电路芯片(1020)将被管芯附连到膜，如图34b所示。芯片(1020)可用管芯附连材料、或粘合剂(1015)之类的任何便利物质附连，这些物质将通常是不导电的以避免电信号的传播。
在一实施例中，芯片(1020)可用不导电的环氧树脂(1015)附连。该粘合剂可应用为流体或粘性液体，其然后将硬化或形成内部交联以形成坚固、耐用的接合。粘合剂或管芯附连材料(1015)将是可见的并且暴露在所得芯片级封装(1040)的底部，并且因此将需要具有长期的热力学和机械稳定性。在其它实施例中，粘合剂可以是诸如聚酰亚胺粘合带之类的带的形式。带通常由在两侧上涂覆有诸如热塑聚合物之类的粘合物质的基带膜组成，并且带可以是粘性的或不剥落的。在进一步的实施例中，粘合剂是固态塑料物质，其在原位固化或凝固以提供芯片与引线框之间的坚固附连。各种类型的粘合剂、带、以及其它管芯附连材料是已知且可购得的。
在一实施例中，粘合剂(1015)以及围绕的密封材料(1030)都是黑色的，因此对整个芯片级封装(1040)呈现出一致的着色。在其它实施例中，粘合剂和密封材料是不同颜色的。在进一步的实施例中，制造商例如可希望为粘合剂和密封材料选择特定互补或对比的颜色，从而提供特别的商业外观。
粘合剂(1015)的厚度不是关键的，虽然它将不得不足够厚以具有机械稳定性并且耐受引线框的背部蚀刻。粘合剂(1015)将通常覆盖集成电路芯片(1020)的整个底面以避免在随后的背部蚀刻或背部图案化进程期间对芯片的化学或机械损伤。
一旦芯片(1020)已被管芯附连到膜(1000)，芯片就例如使用引线(1025)连接到电引线(1005)，如图34c所示。芯片(1020)和引线(1025)使用密封材料(1030)密闭密封(图34d)。如以上所讨论地，密封材料(1030)可以是本领域已知的任何物质。行业中使用的通常密封材料的非限制列表包括硅土微粒填充环氧树脂以及液体环氧树脂。密封材料通常作为液体或粘性液体涂敷到安装在或附着于引线框的各种元件。固化密封材料获得坚硬的、可固化的涂层，其保护芯片级封装中的下面元件不受损坏。
在密封材料(1030)已固化之后，引线框(1000)然后被背部蚀刻以隔离电引线(1005)，如图34e所示。引线框(1000)的在芯片(1020)下面的各部分(即原始芯片安装区域)在背部蚀刻期间被基本或完整去除，直到芯片粘合剂(1015)为止。
引线框然后沿芯片间隔部分(1035)被单片化以获得适于后续应用的各个封装的芯片级封装(1040)，诸如用于附连到计算机电路板。制造商可以选择在完成的芯片级封装上印刷或丝网印刷标志、批号、或者其它类型的标记用于标识目的。
图35和36a分别示出经由图34a-34f所示的工序制备的芯片级封装(1040)的俯视图和截面视图。在图35者，固化粘合剂(1015)在芯片级封装(1040)的中心示为较浅颜色的不规则正方形。围绕固化粘合物质(1015)是密封材料(1030)，如较深颜色所示。密封材料(1030)覆盖并包封集成电路芯片(1020)、布线(1025)、引线(1005)、以及可以附着于或安装到引线框上的任何其它组件。
图36b示出本发明的另一实施例，其中多个集成电路芯片(1020、1050)被管芯叠装在经修整的无焊盘的芯片级封装中(1070)。虽然图26b和36b示出具有管芯叠装芯片的本发明的各实施例，但是图26b中的实施例具有芯片焊盘(515)并且图36b中的实施例采用无焊盘技术。图26b和36b的比较显示芯片焊盘的不存在降低所得芯片级封装的高度，从而使得能制备具有较低外形的芯片级封装。
图36b中所示的实施例可以使用本发明公开的方法制备。简言之，第一、下芯片(1020)被放置在不具有芯片焊盘的部分图案化的引线框上(在此附图中未示出)，并且该芯片(1020)使用诸如粘合剂或环氧树脂之类的管芯附连材料(1015)附着于引线框。上芯片(1050)然后使用诸如导电或不导电的环氧树脂或绝缘材料之类的粘合物质被放置在下芯片(1020)的顶部并且附着于该下芯片。芯片(1020、1050)使用引线接合被电连接到引线框。
电连接(1025)可在每个芯片被放置在引线框上之后顺序地进行。即，第一芯片(1020)可以被放置在引线框上并且电连接到该引线框，并且然后第二芯片(1050)可以被放置在第一芯片(1020)上并且电连接到引线框。在其它实施例中，芯片(1020、1050)首先在原位被管芯叠装，并且然后进行电连接(1025)。这些叠装以及电连接步骤的各种组合是可能的并且在本发明的范围之内。
在芯片(1020、1050)被管芯叠装并且电连接(1025)到引线框之后，引线框然后使用密封材料(1030)封装以永久地将芯片和电线安装在引线框上。引线框的背部然后按需进行背部图案化、蚀刻以及修整以隔离电引线(1005)。在此背部图案化工艺期间，引线框在管芯叠装芯片下面的部分被完整去除，并且仅引线(1005)从经修整的芯片级封装中“凸出”。一般而言，在背部图案化之后保留的原始引线框的仅有部分是电引线(1005)。最后，芯片级封装在芯片间隔区域中被单片化以获得各个芯片级封装(1070)用于后续应用。
根据本发明的另一方面，引线框的顶面和底面可在管芯附连之前被部分图案化或部分蚀刻。如图37a所示，引线框(1100)可以在组装芯片级封装之前在两侧上被蚀刻。引线框的两侧上的蚀刻可以是一致深度的。替换地，蚀刻可以是不均匀的，并且一侧相比另一侧可被图案化得更深。例如，顶部(例如，区域1160)相比底部(例如，区域1165)可被图案化得更深。
双侧蚀刻允许将最终被去除的引线框的膜的各部分具有减小的厚度。从而，蚀刻将进行得更快，并且因而增大生产速度并且降低成本。部分图案化可以减小膜的蚀刻部分的厚度达任何便利量。例如，引线框的部分图案化分段可以在蚀刻区域中去除25-90％的原始膜厚度。
引线框材料可用抗蚀膜材料进行预图案化。抗蚀膜可以是诸如有机抗蚀膜之类的金属或非金属，并且可烘烤固化或UV固化。这些预图案化工艺在本领域中是已知的。
代替使用金属预电镀引线框，引线框可用诸如环氧树脂墨或制版墨之类的可印刷墨印刷、或者诸如聚酰亚胺树脂之类的有机材料作为背部蚀刻之前的蚀刻掩模印刷。可印刷墨或此技术有利地使成本能降低并且能够流线型制造。从材料角度看，将可印刷墨或者有机物质用作蚀刻掩模使制造商能从许多制造商那里获得引线框，因为不是所有的供应商可以在两侧上预电镀引线框。在这一示例中，引线框供应商将仅在顶部蚀刻和电镀引线框，而留下底部未加工。例如，引线框的底部可以是诸如铜之类的裸金属。使用可印刷墨或有机物质进行掩蔽通常相比使用已用于预电镀引线框的诸如钯、金、铂、铑、银、或钌、或其合金之类的贵金属进行掩蔽较便宜。此外，在蚀刻之后去除墨通常比去除贵金属容易些。
引线框还可以在蚀刻之前被预电镀。预电镀材料在引线框的顶面和底面上可以是相同或不同的。适当的预电镀材料的示例包括诸如Ni/Pd/Au底板镀层和银(Ag)之类的可引线接合材料、以及诸如Sn/Pb、无铅焊料、浸锡化学镀镍、或Au(金)底板镀层之类的可焊材料。在本发明的实施例中，正面使用可接合材料预电镀，并且背面使用可焊材料预电镀。在另一实施例中，正面可以使用可引线接合材料进行预电镀，并且背面可以预电镀并且用抗蚀膜覆盖。在进一步的实施例中，有机材料可以被印刷或涂敷在引线框上以供用作光致抗蚀剂。
图36a示出已被蚀刻以形成芯片焊盘(1110)以及多个电引线(1105)的膜(1100)。膜的顶部相比膜的底部已被蚀刻到更大的程度。图36b示出经由引线接合(1125)电连接到图36a所示的引线框的芯片(1120)。在图36b中，集成电路芯片(1120)已经使用粘合剂(1115)附着于引线框(1100)，并且芯片封装已使用环氧密封材料(1130)进行覆盖。芯片间隔区域(1135)使得电连接且被封装的芯片(1120)隔离。
在芯片(1120)已被附着于引线框的芯片焊盘(1110)并被封装之后，引线框的背面可以被背部图案化并蚀刻以隔离电引线(1105)和芯片焊盘(1110)，或者电隔离引线框的各部分以产生期望部件。由于背面已被部分蚀刻，所以此背部蚀刻工艺将更快速地进行并且因而有利地改进每小时单位(UPU)容量并降低成本。
先前引线框的底部管芯焊盘通常是平面的。具有平面的底部管芯焊盘的引线框的示例在图37b中示出。然而，在某些示例中，这些平面的管芯焊盘倾向于在将芯片级封装安装到印刷电路板时导致焊料空隙问题。不受理论束缚，应相信焊料空隙主要是由封装溶剂的除气引起的现象。虽然焊料空隙降低电接触的效率、并且因而可以引起二级可靠性问题，但是焊料空隙可以通常仅由X射线显微镜方法或破坏性微分割检测。
根据本发明的另一方面，引线框可具有开口的底部管芯焊盘。这样的管芯焊盘的实施例在图38中示出。开口(1255)可以在管芯焊盘(1210)上形成通道，并且减小管芯焊盘与印刷表面板之间的接触的表面积，从而有利地减少焊料空隙的量。开口或通道(1255)起气孔的作用，以使在重熔期间没有夹带空气。
开口的底部焊盘(1210)通过在引线框的底侧上的焊盘下面制作小阵列的电镀掩模获得。在蚀刻期间，此电镀掩模的阵列将在底部管芯焊盘上产生半蚀刻通道。掩模将在蚀刻工艺期间起抗蚀膜作用。
蚀刻掩模可以是镍/钯/金合成物(NiPdAu)、银(Ag)、锑(Sn)、镍(Ni)、或其混合物，或者任何可涂敷或印刷到引线框上的非金属或有机材料或墨。蚀刻掩模可按需被烘烤或UV固化。其它适当的掩模和光致抗蚀剂物质对本领域的那些技术人员是已知的。掩蔽和蚀刻的工艺可以如先前所讨论地执行。
图38示出具有多个集成电路芯片(1220、1250)安装到其上的开口底部管芯焊盘(1210)的芯片级封装(1240)。下芯片(1220)经由粘合剂(1215)附着于开口管芯焊盘，而上芯片(1250)经由粘合剂(1245)附着于下芯片(1220)。芯片(1220、1250)经由引线接合(1225)电连接到电引线(1205)，尽管在其它实施例中芯片(1220、1250)还可相互电连接。使用可以是环氧树脂或另一物质的密封材料(1230)封装芯片。
虽然图38示出包括两个管芯叠装的集成电路芯片的芯片级封装，但是在本发明的其它实施例中可仅有单个芯片，而在进一步实施例中可以有三个或更多个管芯叠装芯片。所有这些实施例都在本发明的范围之内。还可以有附着于引线框上的不同芯片焊盘的不同数目芯片。例如，引线框的一个芯片焊盘可具有单个管芯安装芯片，然而同一引线框上的另一芯片焊盘可以是三个管芯安装芯片。因此，本发明可用来在单个引线框上制备多个不同且不一样的芯片。
本发明的各种所述的实施例不是相互排斥的，并且可以任意地组合以制备所公开的引线框的变体。例如，图37a所示的不均匀蚀刻的引线框的管芯焊盘的底部可交叉开口并且用来制备图38所示的具有底部通道的芯片级封装。其它变体也是可能的并且在本发明的范围之内。
虽然已特别示出并参考各特定实施例描述本发明，但是本领域的技术人员将理解可作形式或细节上的各种改变而不背离本发明的精神和范围。

Claims (15)

1.一种形成电子封装的方法，所述方法包括以下步骤：
形成具有选择性预电镀顶面和底面的一块部分蚀刻引线框，所述引线框包括蹼状部分、芯片焊盘区域、电引线部分，其中所述电引线部分与芯片焊盘区域电分离，并且所述引线框通过芯片间隔部分相互分离；
将第一芯片附连到所述引线框上的相应的芯片焊盘区域；
将至少一个第二芯片管芯叠装到相应的第一芯片的顶部；
在所述第一芯片的每一个的一个或多个端子与所述相应的引线框的一个或多个电引线部分之间形成电连接；
形成与所述第二芯片的电连接；
通过在所述引线框和分离所述引线框的所述芯片间隔部分上涂敷密封材料来封装所述引线框；
背部图案化所述引线框的背面以去除所述蹼状部分和所述芯片间隔部分；以及
单片化置于所述芯片间隔部分上的所述密封材料以形成各个芯片级封装。
2.如权利要求1所述的方法，其特征在于，所述至少一个第二芯片使用导电粘合剂或绝缘材料管芯叠装到相应的第一芯片的顶部上。
3.如权利要求1所述的方法，其特征在于，所述第一或第二芯片中的任一个分别是引线接合芯片或倒装芯片。
4.如权利要求1所述的方法，其特征在于，所述芯片焊盘区域被凹入以降低所得封装的高度。
5.如权利要求1所述的方法，其特征在于，进一步包括沿所述芯片焊盘、引线部分或它们两者的周边施加交替可变体，用于改进应力状况期间所述封装的可靠性。
6.如权利要求1所述的方法，其特征在于，还包括将从由无源组件、隔离焊盘、电源环、接地环、布线及其组合组成的组中选出的一个或多个附加的元件直接或间接地电连接到所述引线框。
7.如权利要求1所述的方法，其特征在于，形成到第一和第二芯片的电连接的步骤通过将第一和第二芯片上的端子连接到从所述引线框伸出的电引线部分的端部来完成。
8.如权利要求1所述的方法，其特征在于，预电镀材料在背部图案化之后从所述引线框的底部去除。
9.如权利要求1所述的方法，其特征在于，在背部图案化之后在所述引线框的底部获得的隔离图案使用化学镀Ni/浸Au、浸Ag或浸Sn电镀，或者使用可焊材料或有机表面防护剂(OSP)涂覆。
10.如权利要求1所述的方法，其特征在于，进一步包括将线夹接合到一个或多个第二芯片的顶面以向所述芯片级封装提供改进的能流。
11.一种形成芯片级封装的方法，所述方法包括以下步骤：
形成一块部分蚀刻引线框，所述引线框包括蹼状部分、芯片安装区域、多个电引线部分、以及芯片间隔部分；
将集成电路芯片附连到所述芯片安装区域；
在所述芯片的一个或多个端子与所述引线框的一个或多个电引线部分之间形成电连接；
通过在所述引线框和芯片间隔部分上涂敷密封材料来封装所述引线框；
经由蚀刻来背部图案化所述引线框的底面以去除所述蹼状部分、芯片间隔部分、以及所述芯片安装区域，藉此所述引线框在所述集成电路芯片下面的所有部分被去除；以及
单片化置于所述引线框的所述芯片间隔部分上的密封材料以形成各个芯片级封装。
12.如权利要求11所述的方法，其特征在于，在封装之前，所述引线框在它们的顶侧、底侧、或它们两者上用预电镀材料选择性地预电镀或者用掩模材料掩蔽。
13.如权利要求11所述的方法，其特征在于，还包括：
将至少一个第二芯片管芯叠装到附着于所述引线框的集成电路芯片的顶部；以及
将所述至少一个第二芯片电连接到所述引线框、附着于所述引线框的所述集成电路芯片、或它们两者。
14.一种用于形成芯片级封装的方法，所述方法包括：
提供部分图案化的引线框，所述引线框具有(a)从所述引线框的顶面部分图案化但不完全穿到所述引线框的底面的第一区域，以及(b)不从所述顶面部分图案化的第二区域，所述第二区域形成用于支承集成电路芯片的芯片焊盘区域以及用于提供与所述集成电路芯片的电连接的多个电引线，所述芯片焊盘区域以及多个电引线经由所述第一区域连接但不完全通过所述顶面连接；
将集成电路芯片附连到所述引线框的所述第一区域的所述芯片焊盘区域；
在所述芯片上的一个或多个端子与所述引线框上的一个或多个电引线部分之间形成电连接；
通过在所述引线框和芯片间隔部分上涂敷密封材料来封装所述引线框；
背部图案化所述引线框的所述底面以去除所述蹼状部分和芯片间隔部分，以及去除所述芯片焊盘区域的底面的一部分以形成通过其的一个或多个通道；以及
单片化置于所述引线框的所述芯片间隔部分上的密封材料以形成各个芯片级封装。
15.如权利要求14所述的方法，其特征在于，所述芯片焊盘区域的一个或多个通道跨整个芯片焊盘区域的长度延伸。
CN2007800398623A 2006-10-27 2007-10-24 部分图案化的引线框以及在半导体封装中制造和使用其的方法 Expired - Fee Related CN101601133B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/553,664 US7799611B2 (en) 2002-04-29 2006-10-27 Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US11/553,664 2006-10-27
US11/877,732 US7790500B2 (en) 2002-04-29 2007-10-24 Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US11/877,732 2007-10-24
PCT/US2007/082423 WO2008057770A2 (en) 2006-10-27 2007-10-24 Partially patterned lead frames and methods of making and using the same in semiconductor packaging

Publications (2)

Publication Number Publication Date
CN101601133A CN101601133A (zh) 2009-12-09
CN101601133B true CN101601133B (zh) 2011-08-10

Family

ID=39365193

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800398623A Expired - Fee Related CN101601133B (zh) 2006-10-27 2007-10-24 部分图案化的引线框以及在半导体封装中制造和使用其的方法

Country Status (5)

Country Link
US (2) US7790500B2 (zh)
EP (1) EP2084744A2 (zh)
CN (1) CN101601133B (zh)
TW (1) TWI337775B (zh)
WO (1) WO2008057770A2 (zh)

Families Citing this family (142)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG106050A1 (en) * 2000-03-13 2004-09-30 Megic Corp Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby
US8236612B2 (en) 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20040058478A1 (en) 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
US7462317B2 (en) 2004-11-10 2008-12-09 Enpirion, Inc. Method of manufacturing an encapsulated package for a magnetic device
US7426780B2 (en) 2004-11-10 2008-09-23 Enpirion, Inc. Method of manufacturing a power module
US7688172B2 (en) 2005-10-05 2010-03-30 Enpirion, Inc. Magnetic device having a conductive clip
US8139362B2 (en) 2005-10-05 2012-03-20 Enpirion, Inc. Power module with a magnetic device having a conductive clip
US8701272B2 (en) 2005-10-05 2014-04-22 Enpirion, Inc. Method of forming a power module with a magnetic device having a conductive clip
US8631560B2 (en) 2005-10-05 2014-01-21 Enpirion, Inc. Method of forming a magnetic device having a conductive clip
US8004069B2 (en) * 2005-12-21 2011-08-23 Freescale Semiconductor, Inc. Lead frame based semiconductor package and a method of manufacturing the same
US8460970B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8461694B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
WO2008057770A2 (en) 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
KR101391924B1 (ko) * 2007-01-05 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지
US8937372B2 (en) * 2007-03-21 2015-01-20 Stats Chippac Ltd. Integrated circuit package system with molded strip protrusion
MY154596A (en) * 2007-07-25 2015-06-30 Carsem M Sdn Bhd Thin plastic leadless package with exposed metal die paddle
US7955868B2 (en) 2007-09-10 2011-06-07 Enpirion, Inc. Method of forming a micromagnetic device
US8018315B2 (en) * 2007-09-10 2011-09-13 Enpirion, Inc. Power converter employing a micromagnetic device
US7920042B2 (en) 2007-09-10 2011-04-05 Enpirion, Inc. Micromagnetic device and method of forming the same
US7952459B2 (en) 2007-09-10 2011-05-31 Enpirion, Inc. Micromagnetic device and method of forming the same
US8133529B2 (en) 2007-09-10 2012-03-13 Enpirion, Inc. Method of forming a micromagnetic device
JP5265183B2 (ja) * 2007-12-14 2013-08-14 新光電気工業株式会社 半導体装置
US8110905B2 (en) * 2007-12-17 2012-02-07 Stats Chippac Ltd. Integrated circuit packaging system with leadframe interposer and method of manufacture thereof
US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
US7968981B2 (en) * 2008-04-11 2011-06-28 Stats Chippac Ltd. Inline integrated circuit system
US8692532B2 (en) 2008-04-16 2014-04-08 Enpirion, Inc. Power converter with controller operable in selected modes of operation
US8686698B2 (en) 2008-04-16 2014-04-01 Enpirion, Inc. Power converter with controller operable in selected modes of operation
US8541991B2 (en) 2008-04-16 2013-09-24 Enpirion, Inc. Power converter with controller operable in selected modes of operation
US9246390B2 (en) 2008-04-16 2016-01-26 Enpirion, Inc. Power converter with controller operable in selected modes of operation
TWI368983B (en) * 2008-04-29 2012-07-21 Advanced Semiconductor Eng Integrated circuit package and manufacturing method thereof
US7646089B2 (en) * 2008-05-15 2010-01-12 Fujitsu Limited Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US8659131B2 (en) * 2008-09-25 2014-02-25 Lg Innotek Co., Ltd. Structure for multi-row lead frame and semiconductor package capable of minimizing an under-cut
US8339802B2 (en) 2008-10-02 2012-12-25 Enpirion, Inc. Module having a stacked magnetic device and semiconductor device and method of forming the same
US8266793B2 (en) 2008-10-02 2012-09-18 Enpirion, Inc. Module having a stacked magnetic device and semiconductor device and method of forming the same
US9054086B2 (en) * 2008-10-02 2015-06-09 Enpirion, Inc. Module having a stacked passive element and method of forming the same
US8153473B2 (en) 2008-10-02 2012-04-10 Empirion, Inc. Module having a stacked passive element and method of forming the same
US8106502B2 (en) * 2008-11-17 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with plated pad and method of manufacture thereof
US8089145B1 (en) * 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8698463B2 (en) 2008-12-29 2014-04-15 Enpirion, Inc. Power converter with a dynamically configurable controller based on a power conversion mode
US9548714B2 (en) 2008-12-29 2017-01-17 Altera Corporation Power converter with a dynamically configurable controller and output filter
TWM357705U (en) * 2008-12-30 2009-05-21 Lingsen Precision Ind Ltd Lead frame for quad flat leadless package
JP2010171181A (ja) * 2009-01-22 2010-08-05 Renesas Technology Corp 半導体装置
SG172749A1 (en) 2009-03-06 2011-08-29 Kaixin Inc Leadless integrated circuit package having high density contacts
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
KR101753416B1 (ko) 2009-04-03 2017-07-19 카이씬, 인코포레이티드 Ｉｃ 패키지용 리드프레임 및 제조방법
US8383962B2 (en) * 2009-04-08 2013-02-26 Marvell World Trade Ltd. Exposed die pad package with power ring
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8133759B2 (en) * 2009-04-28 2012-03-13 Macronix International Co., Ltd. Leadframe
US8673687B1 (en) * 2009-05-06 2014-03-18 Marvell International Ltd. Etched hybrid die package
US8133763B2 (en) * 2009-05-22 2012-03-13 Texas Instruments Incorporated Method for semiconductor leadframes in low volume and rapid turnaround
US7875970B2 (en) * 2009-06-10 2011-01-25 Green Arrow Asia Limited Integrated circuit package having a castellated heatspreader
US20100314728A1 (en) * 2009-06-16 2010-12-16 Tung Lok Li Ic package having an inductor etched into a leadframe thereof
JP5178648B2 (ja) 2009-06-30 2013-04-10 キヤノン株式会社 パッケージの製造方法、及び半導体装置
US9362138B2 (en) 2009-09-02 2016-06-07 Kaixin, Inc. IC package and method for manufacturing the same
US8502357B2 (en) * 2009-10-01 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with shaped lead and method of manufacture thereof
US8586414B2 (en) * 2010-12-14 2013-11-19 Alpha & Omega Semiconductor, Inc. Top exposed package and assembly method
US8564110B2 (en) * 2009-10-27 2013-10-22 Alpha & Omega Semiconductor, Inc. Power device with bottom source electrode
CN102054717A (zh) * 2009-11-10 2011-05-11 飞思卡尔半导体公司 半导体芯片栅格阵列封装及其制造方法
US8093714B2 (en) 2009-12-10 2012-01-10 Semtech Corporation Chip assembly with chip-scale packaging
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
TWI404187B (zh) 2010-02-12 2013-08-01 矽品精密工業股份有限公司 能避免電磁干擾之四方形扁平無引腳封裝結構及其製法
US8138595B2 (en) * 2010-03-26 2012-03-20 Stats Chippac Ltd. Integrated circuit packaging system with an intermediate pad and method of manufacture thereof
US8203201B2 (en) * 2010-03-26 2012-06-19 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
US8329509B2 (en) * 2010-04-01 2012-12-11 Freescale Semiconductor, Inc. Packaging process to create wettable lead flank during board assembly
US20110316163A1 (en) * 2010-06-24 2011-12-29 Byung Tai Do Integrated circuit packaging system with molded interconnects and method of manufacture thereof
US8669654B2 (en) * 2010-08-03 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with die paddle and method of manufacture thereof
TWI420630B (zh) 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
US8936971B2 (en) * 2010-09-16 2015-01-20 Stats Chippac Ltd. Integrated circuit packaging system with die paddles and method of manufacture thereof
US8519518B2 (en) * 2010-09-24 2013-08-27 Stats Chippac Ltd. Integrated circuit packaging system with lead encapsulation and method of manufacture thereof
US8669649B2 (en) * 2010-09-24 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with interlock and method of manufacture thereof
US8912046B2 (en) 2010-10-28 2014-12-16 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
TWI419290B (zh) 2010-10-29 2013-12-11 Advanced Semiconductor Eng 四方扁平無引腳封裝及其製作方法
US9029991B2 (en) * 2010-11-16 2015-05-12 Conexant Systems, Inc. Semiconductor packages with reduced solder voiding
US8377750B2 (en) * 2010-12-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with multiple row leads and method of manufacture thereof
US8867295B2 (en) 2010-12-17 2014-10-21 Enpirion, Inc. Power converter for a memory module
TWI397964B (zh) * 2011-01-19 2013-06-01 Unisem Mauritius Holdings Ltd 部分圖案化之引線框架及其在半導體封裝中製作與使用的方法
CN102651360B (zh) * 2011-02-24 2015-03-11 万国半导体股份有限公司 一种可铜线键接的封装体结构及其制作方法
US20120241926A1 (en) * 2011-03-23 2012-09-27 Zigmund Ramirez Camacho Integrated circuit packaging system with leveling standoff and method of manufacture thereof
US8399997B2 (en) * 2011-06-10 2013-03-19 Shanghai Kalhong Electronic Company Limited Power package including multiple semiconductor devices
US8957509B2 (en) 2011-06-23 2015-02-17 Stats Chippac Ltd. Integrated circuit packaging system with thermal emission and method of manufacture thereof
US8502363B2 (en) 2011-07-06 2013-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with solder joint enhancement element and related methods
TW201304092A (zh) * 2011-07-08 2013-01-16 矽品精密工業股份有限公司 半導體承載件暨封裝件及其製法
US10522452B2 (en) * 2011-10-18 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates
JP5953703B2 (ja) * 2011-10-31 2016-07-20 ソニー株式会社 リードフレームおよび半導体装置
CN102683315B (zh) * 2011-11-30 2015-04-29 江苏长电科技股份有限公司 滚镀四面无引脚封装结构及其制造方法
US9576873B2 (en) * 2011-12-14 2017-02-21 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with routable trace and method of manufacture thereof
US8674487B2 (en) 2012-03-15 2014-03-18 Advanced Semiconductor Engineering, Inc. Semiconductor packages with lead extensions and related methods
US9653656B2 (en) 2012-03-16 2017-05-16 Advanced Semiconductor Engineering, Inc. LED packages and related methods
US9312194B2 (en) * 2012-03-20 2016-04-12 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8637974B2 (en) * 2012-06-14 2014-01-28 Stats Chippac Ltd. Integrated circuit packaging system with tiebar-less design and method of manufacture thereof
US9196504B2 (en) * 2012-07-03 2015-11-24 Utac Dongguan Ltd. Thermal leadless array package with die attach pad locking feature
CN103545268B (zh) * 2012-07-09 2016-04-13 万国半导体股份有限公司 底部源极的功率器件及制备方法
TWI503929B (zh) * 2012-07-09 2015-10-11 萬國半導體股份有限公司 底部源極的功率裝置及製備方法
US9059379B2 (en) 2012-10-29 2015-06-16 Advanced Semiconductor Engineering, Inc. Light-emitting semiconductor packages and related methods
TWI497670B (zh) * 2012-12-21 2015-08-21 Alpha & Omega Semiconductor 基於鋁合金引線框架的半導體元件及製備方法
CN103226725B (zh) * 2013-03-27 2016-06-22 上海东方磁卡工程有限公司 一种能测量焊点拉力值的智能卡及其焊点拉力值测量方法
CN103413766B (zh) * 2013-08-06 2016-08-10 江阴芯智联电子科技有限公司 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法
CN103456645B (zh) * 2013-08-06 2016-06-01 江阴芯智联电子科技有限公司 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法
CN103400771B (zh) * 2013-08-06 2016-06-29 江阴芯智联电子科技有限公司 先蚀后封芯片倒装三维系统级金属线路板结构及工艺方法
US9263419B2 (en) 2013-08-30 2016-02-16 Infineon Technologies Ag Lead frame strips with electrical isolation of die paddles
US9252089B2 (en) * 2014-04-17 2016-02-02 Infineon Technologies Ag Universal lead frame for flat no-leads packages
CN104658929A (zh) * 2014-04-22 2015-05-27 柯全 倒装芯片的封装方法及装置
US20160056095A1 (en) * 2014-08-25 2016-02-25 Infineon Technologies Ag Leadframe Strip with Sawing Enhancement Feature
KR102150111B1 (ko) * 2014-10-01 2020-08-31 에스케이하이닉스 주식회사 반도체 적층 패키지
US9324640B1 (en) * 2014-11-04 2016-04-26 Texas Instruments Incorporated Triple stack semiconductor package
US9659843B2 (en) 2014-11-05 2017-05-23 Infineon Technologies Ag Lead frame strip with molding compound channels
US9780018B2 (en) * 2014-12-16 2017-10-03 Infineon Technologies Americas Corp. Power semiconductor package having reduced form factor and increased current carrying capability
US9966326B2 (en) 2015-03-16 2018-05-08 Unisem (M) Berhad Lead frames with wettable flanks
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US9509217B2 (en) 2015-04-20 2016-11-29 Altera Corporation Asymmetric power flow controller for a power converter and method of operating the same
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
US9978720B2 (en) * 2015-07-06 2018-05-22 Infineon Technologies Ag Insulated die
CN105161424A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
CN105161425A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
CN204991696U (zh) * 2015-09-11 2016-01-20 深圳市汇顶科技股份有限公司 传感芯片封装组件和具有该传感芯片封装组件的电子设备
JP6608672B2 (ja) * 2015-10-30 2019-11-20 新光電気工業株式会社 半導体装置及びその製造方法、リードフレーム及びその製造方法
US9922908B2 (en) * 2015-12-18 2018-03-20 Texas Instruments Incorporated Semiconductor package having a leadframe with multi-level assembly pads
CN110637364B (zh) * 2016-04-22 2022-10-28 德州仪器公司 改进的引线框系统
US9728492B1 (en) 2016-05-24 2017-08-08 Infineon Technologies Ag Strip testing of semiconductor devices
CN109983591B (zh) * 2016-11-11 2022-10-04 亮锐控股有限公司 制造引线框的方法
US9917040B1 (en) * 2016-12-12 2018-03-13 Stmicroelectronics, Inc. Stress relieved thermal base for integrated circuit packaging
TWI619224B (zh) * 2017-03-30 2018-03-21 矽品精密工業股份有限公司 電子封裝件及其製法
US10529672B2 (en) * 2017-08-31 2020-01-07 Stmicroelectronics, Inc. Package with interlocking leads and manufacturing the same
US11031350B2 (en) * 2017-12-26 2021-06-08 Stmicroelectronics, Inc. Leadframe with pad anchoring members and method of forming the same
US11398417B2 (en) 2018-10-30 2022-07-26 Stmicroelectronics, Inc. Semiconductor package having die pad with cooling fins
DE102019112778B4 (de) * 2019-05-15 2023-10-19 Infineon Technologies Ag Batchherstellung von Packages durch eine in Träger getrennte Schicht nach Anbringung von elektronischen Komponenten
JP7134137B2 (ja) * 2019-05-31 2022-09-09 三菱電機株式会社 半導体装置
TWI747308B (zh) * 2019-06-14 2021-11-21 日商索尼半導體解決方案公司 半導體裝置
TWI719866B (zh) * 2020-03-25 2021-02-21 矽品精密工業股份有限公司 電子封裝件及其支撐結構與製法
US11742253B2 (en) * 2020-05-08 2023-08-29 Qualcomm Incorporated Selective mold placement on integrated circuit (IC) packages and methods of fabricating
CN114171485A (zh) * 2020-09-10 2022-03-11 恩智浦美国有限公司 Qfn半导体封装、半导体封装及引线框架
US20220199500A1 (en) * 2020-12-18 2022-06-23 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, component for use therein and corresponding semiconductor device
US20230063278A1 (en) * 2021-08-27 2023-03-02 Texas Instruments Incorporated Laser-cut lead-frame for integrated circuit (ic) packages
CN117712079B (zh) * 2024-02-02 2024-04-16 合肥中航天成电子科技有限公司 一种用于sop封装及封装件生产设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127199A (ja) * 1999-10-29 2001-05-11 Matsushita Electronics Industry Corp 樹脂封止型半導体装置およびその製造方法
US6316727B1 (en) * 1999-10-07 2001-11-13 United Microelectronics Corp. Multi-chip semiconductor package
US6906423B1 (en) * 2001-06-05 2005-06-14 Kabushiki Kaisha Toshiba Mask used for exposing a porous substrate

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038488A (en) 1975-05-12 1977-07-26 Cambridge Memories, Inc. Multilayer ceramic multi-chip, dual in-line packaging assembly
US4368168A (en) 1978-07-17 1983-01-11 Dusan Slepcevic Method for encapsulating electrical components
JPH06232305A (ja) * 1993-02-05 1994-08-19 Toshiba Corp リ−ドフレ−ムの製造方法
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5923538A (en) 1994-10-17 1999-07-13 Lsi Logic Corporation Support member for mounting a microelectronic circuit package
JPH08222681A (ja) 1995-02-14 1996-08-30 Toshiba Corp 樹脂封止型半導体装置
KR0183645B1 (ko) 1996-03-26 1999-03-20 이대원 다층 구조의 도금층을 구비한 반도체 리드 프레임
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US5847458A (en) 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
JP2811170B2 (ja) * 1996-06-28 1998-10-15 株式会社後藤製作所 樹脂封止型半導体装置及びその製造方法
EP0977251B1 (en) 1997-02-10 2011-11-16 Panasonic Corporation Resin sealed semiconductor device and method for manufacturing the same
JPH1154658A (ja) 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
JPH11186294A (ja) 1997-10-14 1999-07-09 Sumitomo Metal Smi Electron Devices Inc 半導体パッケージ及びその製造方法
JPH11195742A (ja) 1998-01-05 1999-07-21 Matsushita Electron Corp 半導体装置及びその製造方法とそれに用いるリードフレーム
JPH11312749A (ja) 1998-02-25 1999-11-09 Fujitsu Ltd 半導体装置及びその製造方法及びリードフレームの製造方法
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6635957B2 (en) 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6933594B2 (en) 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6989294B1 (en) 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6872661B1 (en) 1998-06-10 2005-03-29 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP3436159B2 (ja) 1998-11-11 2003-08-11 松下電器産業株式会社 樹脂封止型半導体装置の製造方法
JP2000188309A (ja) 1998-12-22 2000-07-04 Hitachi Cable Ltd スティフナ及びスティフナ付きｔａｂテープ
US6355199B1 (en) 1999-02-12 2002-03-12 St. Assembly Test Services Pte Ltd Method of molding flexible circuit with molded stiffener
KR100618541B1 (ko) 1999-07-06 2006-08-31 삼성전자주식회사 다층 반도체 칩 패키지 제작 방법
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
JP2001068586A (ja) 1999-08-25 2001-03-16 Fujitsu Ltd 半導体装置
US6451627B1 (en) 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP3371867B2 (ja) 1999-10-05 2003-01-27 日本電気株式会社 半導体装置
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP3883784B2 (ja) 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
TW506236B (en) 2000-06-09 2002-10-11 Sanyo Electric Co Method for manufacturing an illumination device
TW507482B (en) 2000-06-09 2002-10-21 Sanyo Electric Co Light emitting device, its manufacturing process, and lighting device using such a light-emitting device
US6348399B1 (en) 2000-07-06 2002-02-19 Advanced Semiconductor Engineering, Inc. Method of making chip scale package
KR100347706B1 (ko) 2000-08-09 2002-08-09 주식회사 코스타트반도체 이식성 도전패턴을 포함하는 반도체 패키지 및 그 제조방법
KR100414479B1 (ko) 2000-08-09 2004-01-07 주식회사 코스타트반도체 반도체 패키징 공정의 이식성 도전패턴을 갖는 테이프 및그 제조방법
US6545364B2 (en) 2000-09-04 2003-04-08 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same
JP3600131B2 (ja) 2000-09-04 2004-12-08 三洋電機株式会社 回路装置の製造方法
JP3639514B2 (ja) 2000-09-04 2005-04-20 三洋電機株式会社 回路装置の製造方法
US6762118B2 (en) 2000-10-10 2004-07-13 Walsin Advanced Electronics Ltd. Package having array of metal pegs linked by printed circuit lines
US6576539B1 (en) 2000-10-13 2003-06-10 Charles W.C. Lin Semiconductor chip assembly with interlocked conductive trace
TW464053U (en) 2000-12-29 2001-11-11 Chipmos Technologies Inc Tape bearing encapsulation structure
JP2003204027A (ja) 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
EP1500130A1 (en) 2002-04-29 2005-01-26 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 (en) 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20040058478A1 (en) 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
US6936929B1 (en) 2003-03-17 2005-08-30 National Semiconductor Corporation Multichip packages with exposed dice
US7451539B2 (en) 2005-08-08 2008-11-18 Rf Micro Devices, Inc. Method of making a conformal electromagnetic interference shield
US7342303B1 (en) 2006-02-28 2008-03-11 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
WO2008057770A2 (en) 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7576415B2 (en) 2007-06-15 2009-08-18 Advanced Semiconductor Engineering, Inc. EMI shielded semiconductor package
US20090230524A1 (en) 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316727B1 (en) * 1999-10-07 2001-11-13 United Microelectronics Corp. Multi-chip semiconductor package
JP2001127199A (ja) * 1999-10-29 2001-05-11 Matsushita Electronics Industry Corp 樹脂封止型半導体装置およびその製造方法
US6906423B1 (en) * 2001-06-05 2005-06-14 Kabushiki Kaisha Toshiba Mask used for exposing a porous substrate

Also Published As

Publication number Publication date
TWI337775B (en) 2011-02-21
US20080258278A1 (en) 2008-10-23
CN101601133A (zh) 2009-12-09
US20110057298A1 (en) 2011-03-10
WO2008057770A9 (en) 2008-08-21
WO2008057770A2 (en) 2008-05-15
EP2084744A2 (en) 2009-08-05
US7790500B2 (en) 2010-09-07
WO2008057770A3 (en) 2008-06-26
TW200834859A (en) 2008-08-16

Similar Documents

Publication Publication Date Title
CN101601133B (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
CN102386106B (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
JP4032063B2 (ja) 半導体装置の製造方法
US7439097B2 (en) Taped lead frames and methods of making and using the same in semiconductor packaging
US8236612B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN100380614C (zh) 部分构图的引线框架及其制造方法以及在半导体封装中的使用
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
US7977161B2 (en) Method of manufacturing a semiconductor package using a carrier
US9966326B2 (en) Lead frames with wettable flanks
KR20030051222A (ko) 반도체 장치 및 그 제조 방법
US8076181B1 (en) Lead plating technique for singulated IC packages
US20050189627A1 (en) Method of surface mounting a semiconductor device
US20110163430A1 (en) Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
CN101383301B (zh) 形成倒装芯片突起载体式封装的方法
US20030006501A1 (en) Semiconductor device, method of manufacturing semiconductor device, lead frame, method of manufacturing lead frame, and method of manufacturing semiconductor device with lead frame
KR101674537B1 (ko) 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지
CN109390237A (zh) 侧面可焊接无引线封装
US9805956B2 (en) Lead frame and a method of fabrication thereof
KR101036354B1 (ko) 다열 리드프레임 및 반도체 칩 패키지 및 그 제조방법
CN100456442C (zh) 具有支撑部的半导体封装结构及其制法
CN101740410B (zh) 芯片封装结构的制程
KR20100104112A (ko) 반도체 패키지용 회로기판, 그의 제조 방법 및 이를 적용한반도체 패키지
JP2001127196A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法
JP3059007U (ja) 半導体パッケージ
JP2001127227A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110810

Termination date: 20141024

EXPY Termination of patent right or utility model