CN101447443B - Method for manufacturing high-frequency integrated circuit encapsulation structure - Google Patents
Method for manufacturing high-frequency integrated circuit encapsulation structure Download PDFInfo
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- CN101447443B CN101447443B CN2008101804175A CN200810180417A CN101447443B CN 101447443 B CN101447443 B CN 101447443B CN 2008101804175 A CN2008101804175 A CN 2008101804175A CN 200810180417 A CN200810180417 A CN 200810180417A CN 101447443 B CN101447443 B CN 101447443B
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2924/151—Die mounting substrate
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention relates to a method for manufacturing a high-frequency integrated circuit encapsulation structure. The method comprises the steps as follows: a baseplate is provided with a first surface, a second surface and a plurality of projection containing holes; a plurality of inscribed gaskets are arranged corresponding to the projection containing holes; a chip is provided and is arranged onthe first surface of the baseplate; the chip is provided with an active surface; a plurality of heightened projections are arranged on the active surface of the chip and are contained in the projection containing holes to be adjacent to the inscribed gaskets; a plurality of flatted projections are combined with the heightened projections and are connected with the inscribed gaskets in electric connection; and a plurality of external terminals are arranged on the second surface of the baseplate. Therefore, the flatted projections are combined with the projections of the chip and can be in electric connection with the inscribed gaskets, so that the high-frequency integrated circuit encapsulation structure has the advantages of short electrical conduction route and light and small size.
Description
The application is an original application application number 2006101112387, and on August 15 2006 applying date, denomination of invention is divided an application for " high-frequency integrated circuit encapsulation structure and manufacture method thereof ".
Technical field
The present invention relates to a kind of integrated circuit encapsulation technology, particularly relate to a kind of manufacture method with high-frequency integrated circuit encapsulation structure of short electrical conducting path and compactization advantage.
Background technology
Current integrated circuit (IC) chip is towards the development of high-frequency transmission speed, if the chip and the electrical interconnects between the carrier of chip encapsulation construction inside are continued to use traditional routing encapsulation technology, then electrically conducting path can be long, loses the meaning of high frequency design.For example, early stage synchronous DRAM (Synchronous Dynamic Random Access Memory, SDRAM) memory body promptly is to adopt thin-type small-size encapsulation (Thin Small Outline Package, TSOP) encapsulated type, its chip carrier is for having the lead frame of outer pin, and the bonding wire that forms with routing is electrically connected to chip.The second generation Double Data Rate in modern age (Double Data Rate 2, DDR2) (200～533MHz) then must use bismaleimide-3 pyridine (Bismaleimide Triazine instead to the memory body chip, BT) circuit board, otherwise have the problem of signal delay, but still be to electrically connect chip and substrate with the bonding wire that routing forms.Yet, when the transmission frequency of chip further promotes, third generation Double Data Rate (Double Data Rate 3 particularly, DDR3) the memory body chip of SDRAM (or claim DDR III) (its frequency is between 400～800MHz) and high-frequency integrated circuit chip 800MHz more than, bonding wire seem long understand influence transmission speed.In addition, wish can be lighter, thinner, shorter and littler for the outward appearance of more advancing the high-frequency integrated circuit encapsulation structure of a generation.
Seeing also shown in Figure 1ly, is the schematic cross-section of existing known IC circuit packing structure.The existing known IC circuit packing structure 100 in order to encapsulation DDR2 memory body (internal memory) chip comprises BT substrate 110, a chip 120, an adhesive body 130 and several bonding wires 140 with line layer 114.This chip 120 is the upper surfaces 111 that are bonded to this substrate 110 by a sticking crystal layer 150, and the weld pad 122 on the active surface 121 of this chip 120 is in the long and narrow slotted eye 113 in alignment with this substrate 110.By this long and narrow slotted eye 113, an end of those bonding wires 140 is bonded to those weld pads 122, the other end be bonded to this substrate 110 in connect finger; And form this adhesive body 130 with compression molding techniques, to seal this chip 120 and those bonding wires 140.Several soldered balls 160 are the lower surfaces 112 that are arranged at this substrate 110, engage (SMT) for outer surface.
Except the routing technology, knownly can use chip bonding (flip-chip bonding) to reach the inner short electrical interconnects of encapsulation.Yet, so-called chip bonding technology is that chip is manufactured with projection in advance, and upset and this chip to one substrate of hot pressing can't be continued to use existing encapsulation procedure equipment such as sticking brilliant machine, wire bonder, new equipment like this is the cost height not only, and the tolerable error of process parameter is very little.
This shows that above-mentioned existing integrated circuits packaging structure and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new high-frequency integrated circuit encapsulation structure and manufacture method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing integrated circuits packaging structure and manufacture method thereof exist, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new high-frequency integrated circuit encapsulation structure and manufacture method thereof, can improve general existing integrated circuits packaging structure and manufacture method thereof, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective that the existing integrated circuits packaging structure exists, and provide a kind of new high-frequency integrated circuit encapsulation structure, technical problem to be solved is to make it except having the effect that electrical conducting path is short, product is compact, more can continue to use existing encapsulation procedure equipment and can promote processing procedure efficient, thereby be suitable for practicality more.
Of the present invention time a purpose is that a kind of new high-frequency integrated circuit encapsulation structure is provided, and technical problem to be solved is to make it can encapsulate the memory body chip of frequency more than 400MHz, thereby is suitable for practicality more.
Another object of the present invention is to, a kind of new high-frequency integrated circuit encapsulation structure is provided, technical problem to be solved is to make it can reach chip size packages (CSP, Chip Scale Package), thereby is suitable for practicality more.
A further object of the present invention is, a kind of new high-frequency integrated circuit encapsulation structure is provided, technical problem to be solved is to make its interior connection pad change of shape by flexible base plate, and can guarantee the electric connection of projection and interior connection pad, thereby is suitable for practicality more.
An also purpose of the present invention is, a kind of new high-frequency integrated circuit encapsulation structure is provided, technical problem to be solved be make its utilize wire bonder make projection with to external terminal, and can simplify processing procedure, thereby be suitable for practicality more, and have industrial utilization.
A further object of the present invention is, a kind of new high-frequency integrated circuit encapsulation structure is provided, technical problem to be solved be make its by flexible base plate and resilient coating between to external terminal and chip, and can absorb thermal stress, thereby be suitable for practicality more, and have the value on the industry.
An also purpose of the present invention is, overcome the defective of the manufacture method existence of existing integrated circuits packaging structure, and provide a kind of manufacture method of new high-frequency integrated circuit encapsulation structure, technical problem to be solved is to continue to use the existing IC circuit packing structure that the electrical conducting path of encapsulation procedure device fabrication is short, product is compact, and can promote processing procedure efficient, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of high-frequency integrated circuit encapsulation structure that the present invention proposes, it comprises: a substrate, have a first surface, a second surface and several projection containing holes, and be provided with connection pad in several corresponding to those projection containing holes; One chip, it is arranged on this first surface of this flexible base plate, and this chip has an active surface towards this flexible base plate; Several increase projection, and it is arranged on this active surface of this chip and is placed in those corresponding projection containing holes, to be adjacent to connection pad in those; Several flattening projections, its be bonded to those increase projection and with those in connection pad for electrically connecting; And several are to external terminal, and it is arranged at this second surface of this flexible base plate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those interior connection pads are the air ring of hollow.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those flattening projections are balling ends of being formed by routing or are formed by electroplating.
Aforesaid high-frequency integrated circuit encapsulation structure, the Deformation Height of wherein said those flattening projections be those balling ends before routing below 1/2nd.
Aforesaid high-frequency integrated circuit encapsulation structure, it includes an adhesive body in addition, and it is formed on this second surface of this flexible base plate, to coat those flattening projections.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those comprise soldered ball to external terminal.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of high-frequency integrated circuit encapsulation structure that the present invention proposes, it comprises: a flexible base plate has a first surface, a second surface and at least one opening, and is provided with connection pad in several; One chip, it is arranged on this first surface of this flexible base plate, and this chip has active surface and several weld pads towards this flexible base plate; Several flattening projections, it is arranged in this opening, those flattening projections be bonded to those weld pads and with those in connection pad for electrically connecting; And several are to external terminal, and it is arranged on this second surface of this flexible base plate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those interior connection pads are the air rings for hollow.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those flattening projections are balling ends of being formed by routing or are formed by electroplating.
Aforesaid high-frequency integrated circuit encapsulation structure, the Deformation Height of wherein said those flattening projections be those balling ends before routing below 1/2nd.
Aforesaid high-frequency integrated circuit encapsulation structure, it includes an adhesive body in addition, and it is formed on this second surface of this flexible base plate, to coat those flattening projections.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein said those comprise soldered ball to external terminal.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.The manufacture method of a kind of high-frequency integrated circuit encapsulation structure that proposes according to the present invention, it comprises the steps: to provide a substrate, it is to have a first surface, a second surface and several projection containing holes, is provided with connection pad in several corresponding to those projection containing holes; One chip is provided, and it is arranged on this first surface of this substrate, and this chip has an active surface towards this substrate; Several are set increase projection on this active surface of this chip and be placed in those corresponding projection containing holes, to be adjacent to connection pad in those; Increase projection in conjunction with several flattening projections to those, and make those flattening projections and those interior connection pads for electrically connecting; And several are set to external terminal this second surface in this substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said those interior connection pads are the air rings for hollow.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said those flattening projections are to form by routing or by electroplating.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, the Deformation Height of wherein said those flattening projections be before routing below 1/2nd.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, it comprises in addition: form an adhesive body on this second surface of this substrate, to coat those flattening projections.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said adhesive body more are formed on this first surface of this substrate, to cover at least a portion of this chip.
The manufacture method of aforesaid high-frequency integrated circuit encapsulation structure, wherein said those comprise soldered ball to external terminal.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above, in order to achieve the above object, according to the present invention's one specific embodiment, a kind of high-frequency integrated circuit encapsulation structure mainly comprises a flexible base plate, a chip, several increase projection, several flattening projections and several are to external terminal.This flexible base plate has a first surface, a second surface and several projection containing holes, is provided with connection pad in several corresponding to those projection containing holes.This chip is arranged on this first surface of this flexible base plate, and this chip has an active surface towards this flexible base plate.Those are increased on this active surface that projection is arranged at this chip and are placed in those corresponding projection containing holes, to be adjacent to connection pad in those.Those flattening projections be bonded to those increase projection and with those in connection pad for electrically connecting.Those are to be arranged on this second surface of this flexible base plate to external terminal.
According to another specific embodiment of the present invention, another kind of high-frequency integrated circuit encapsulation structure mainly comprises a flexible base plate, a chip, several flattening projections and several are to external terminal.This flexible base plate has a first surface, a second surface and at least one opening, and is provided with connection pad in several.This chip is arranged on this first surface of this flexible base plate, and this chip has active surface and several weld pads towards this flexible base plate.Those flattening projections are arranged in this opening, those flattening projections be bonded to those weld pads and with those in connection pad for electrically connecting.Those are to be arranged on this second surface of this flexible base plate to external terminal.
Aforesaid high-frequency integrated circuit encapsulation structure, wherein this chip is to be the memory body chip of frequency more than 400MHz.Aforesaid high-frequency integrated circuit encapsulation structure, wherein this chip is to be third generation Double Data Rate synchronous DRAM (DDR3 SDRAM) chip.Aforesaid high-frequency integrated circuit encapsulation structure, wherein the size of this chip is approximately identical to this flexible base plate, to become chip size packages (CSP).Aforesaid high-frequency integrated circuit encapsulation structure, wherein those interior connection pads are the air rings for hollow.Aforesaid high-frequency integrated circuit encapsulation structure, wherein those flattening projections are formed by the balling end that routing forms.Aforesaid high-frequency integrated circuit encapsulation structure, wherein the Deformation Height of those flattening projections be those balling ends before routing below 1/2nd.Aforesaid high-frequency integrated circuit encapsulation structure, wherein those are to comprise the balling end that routing forms to external terminal.Aforesaid high-frequency integrated circuit encapsulation structure, other includes a resilient coating, and it is arranged between this first surface of this active surface of this chip and this flexible base plate.Aforesaid high-frequency integrated circuit encapsulation structure, other includes an adhesive body, and it is formed on this second surface of this flexible base plate, to coat those flattening projections.Aforesaid high-frequency integrated circuit encapsulation structure, wherein those are to comprise soldered ball to external terminal.Aforesaid high-frequency integrated circuit encapsulation structure, wherein those to increase projection be by electroplating or the routing mode forms.
By technique scheme, high-frequency integrated circuit encapsulation structure of the present invention and manufacture method thereof have following advantage at least:
1, high-frequency integrated circuit encapsulation structure of the present invention except having the effect that electrical conducting path is short, product is compact, more can be continued to use existing encapsulation procedure equipment, and can promote processing procedure efficient, thereby be suitable for practicality more.
2, high-frequency integrated circuit encapsulation structure of the present invention can encapsulate the memory body chip of frequency more than 400MHz, thereby is suitable for practicality more.
3, high-frequency integrated circuit encapsulation structure of the present invention can reach chip size packages (CSP, ChipScale Package), thereby is suitable for practicality more.
4, high-frequency integrated circuit encapsulation structure of the present invention by the interior connection pad change of shape of flexible base plate, and can be guaranteed the electric connection of projection and interior connection pad, thereby be suitable for practicality more.
5, high-frequency integrated circuit encapsulation structure of the present invention, its utilize wire bonder make projection with to external terminal, and can simplify processing procedure, thereby be suitable for practicality more, and have industrial utilization.
6, high-frequency integrated circuit encapsulation structure of the present invention between to external terminal and chip, and can absorb thermal stress by flexible base plate and resilient coating, thereby be suitable for practicality more, and have the value on the industry.
7, the manufacture method of high-frequency integrated circuit encapsulation structure of the present invention, technical problem to be solved is that to make its technical problem to be solved be to make it except having the effect that electrical conducting path is short, product is compact, more can continue to use existing encapsulation procedure equipment and can promote processing procedure efficient, thereby be suitable for practicality more.
In sum, the present invention is relevant a kind of high-frequency integrated circuit encapsulation structure and manufacture method thereof.This high-frequency integrated circuit encapsulation structure mainly comprises one and has flexible base plate, a projection chip, several flattening projections of projection containing hole and several are to external terminal.Wherein those are arranged at this flexible base plate another surface with respect to this projection chip to external terminal.This flexible base plate is provided with connection pad in several, and when several projections of this projection chip are placed in those projection containing holes, connection pads are to be adjacent to those chip lugs in those.Therefore, those flattening projections are when being bonded to chip lug, can electrically connect connection pad in those, and have the advantage of short electrical conducting path and compactization.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on structure or function, be a significant progress in technology, and produced handy and practical effect, and has the outstanding effect of enhancement than existing integrated circuits packaging structure and manufacture method thereof, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section that has known IC circuit packing structure now.
Fig. 2 is according to first specific embodiment of the present invention, a kind of schematic cross-section of high-frequency integrated circuit encapsulation structure.
Fig. 3 A to Fig. 3 C is that this packaging structure is at the schematic cross-section of the electrical connection procedure in inside according to first specific embodiment of the present invention.
Fig. 4 figure is according to first specific embodiment of the present invention, this packaging structure projection in conjunction with the time schematic perspective view.
Fig. 5 is according to second specific embodiment of the present invention, the schematic cross-section of another kind of high-frequency integrated circuit encapsulation structure.
Fig. 6 is according to the 3rd specific embodiment of the present invention, the schematic cross-section of another kind of high-frequency integrated circuit encapsulation structure.
Fig. 7 A to Fig. 7 D is according to the 3rd specific embodiment of the present invention, the processing procedure of this packaging structure and structural section schematic diagram wherein.
10: pressure welding syringe needle 20: bonding wire
21: balling end 100: IC circuit packing structure
110: substrate 111: upper surface
112: lower surface 113: long and narrow slotted eye
114: line layer 120: chip
121: active surface 122: weld pad
130: mould adhesive body 140: bonding wire
150: sticking crystal layer 160: soldered ball
200: high-frequency integrated circuit encapsulation structure 210: flexible base plate
211: first surface 212: second surface
213: projection containing hole 214: interior connection pad
214A: hollow part 215: outer connection pad
216: welding resisting layer 220: chip
221: active surface 222: the back side
223: weld pad 230: increase projection
231: end face 240: the flattening projection
250: to external terminal 260: adhesive body
270: resilient coating 300: high-frequency integrated circuit encapsulation structure
310: flexible base plate 311: first surface
312: second surface 313: opening
314: interior connection pad 320: chip
321: active surface 322: weld pad
330: flattening projection 340: to external terminal
360: the second adhesive bodies of 350: the first adhesive bodies
400: high-frequency integrated circuit encapsulation structure 410: substrate
411: first surface 412: second surface
413: projection containing hole 414: interior connection pad
415: outer connection pad 420: chip
421: active surface 422: weld pad
430: increase projection 440: the flattening projection
450: to external terminal 460: adhesive body
470: sticking crystal layer
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to high-frequency integrated circuit encapsulation structure and its embodiment of manufacture method, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Seeing also shown in Figure 2ly, is the schematic cross-section according to first specific embodiment of the present invention a kind of high-frequency integrated circuit encapsulation structure.At a kind of high-frequency integrated circuit encapsulation structure 200 of first specific embodiment of the present invention, mainly comprise a flexible base plate 210, a chip 220, several increase projection 230, several flattening projections 240 and several are to external terminal 250.
This flexible base plate 210, it is the circuit film that before encapsulation, can repeat to bend for a kind of, for example membrane of flip chip encapsulates (COF) film, the material of its core layer can be poly-green onion imines (polyimide, PI), PETG (polyethylene terephthalate, PET) etc. and have the metallic circuit layer of one deck at least, its gross thickness is about below 70 microns, is below 1/10th of traditional B T substrate.This flexible base plate 210 has a first surface 211, a second surface 212 and several projection containing holes 213, and be provided with connection pad 214 and several outer connection pads 215 in several, connection pad 214 is corresponding to those projection containing holes 213 in those, and those outer connection pads 215 are to be the trellis array; And cover the circuit pack that these metallic circuit layers connect connection pad 214 and those outer connection pads 215 in those with a welding resisting layer 216.
This chip 220 is to be arranged on this first surface 211 of this flexible base plate 210.And those are to be arranged on this second surface 212 of this flexible base plate 210 to external terminal 250.This chip 220 has active surface 221, an opposing backside surface 222 towards this flexible base plate 210.This active surface 221 is formed with several weld pads 223, can be central authorities, periphery or arranged.This chip 220 can be a Dynamic Random Access Memory chip, surpasses the high frequency memory body chip of 400MHz as DDR2 SDRAM, DDR3 SDRAM, Rambus equifrequent.In the present embodiment, this chip 220 is to be third generation Double Data Rate synchronous DRAM (DDR3 SDRAM) chip.Preferably, the size of this chip is approximately identical to this flexible base plate 210, its active surface 221 areas be not less than this flexible base plate 210 first surface 211 70 percent, to become chip 220 sizes encapsulation (CSP).Because the line-spacing of integrated circuit package continues to dwindle at present, must take into account the fixed size of this chip 220 again, to reach desirable cutting efficiency and the encapsulation outward appearance and the external terminal setting (Layout) that meet international standard, can increase the integrated circuit package quantity and the complexity of this chip 220.In the present embodiment, the memory body capacity of single chips 220 can be more than 256MB.
In addition, in the present embodiment, those comprise soldered ball (solder ball) to external terminal 250, and it is those outer connection pads 215 that are arranged at this flexible base plate 210, for surface engagement to an external printed circuit board (figure does not draw).
In addition, those increase projection 230, be to be arranged on this active surface 221 of this chip 220 and to be placed in those corresponding projection containing holes 213, being adjacent to connection pad 214 in those, its be provided with the electrode that purpose is to reduce this chip 220 (be weld pad 223 add increase projection 230) with those in both differences in height of connection pad 214.Wherein the adjacent gap that connection pads 214 and corresponding those are increased projection 230 in those should be comprised in the bonding area of those flattening projections 240.It is to be pre-formed on those weld pads 223 of this chip 220 that common those are increased projection 230, can be the tie lines projection (stud bump) that routing forms, and also can be to electroplate golden projection or other conductive projection that forms.In addition, those height of increasing projection 230 are between 40～100 microns.
See also shown in Figure 4, be according to this packaging structure of first specific embodiment of the present invention projection in conjunction with the time schematic perspective view.Those end faces 231 of increasing projection 230 are approximately to be aligned in connection pad 214 in those, can protrude in connection pad 214 in those recessed slightly or slightly, be beneficial to those flattening projections 240 when being bonded to those end faces of increasing projection 230 231, can electrically connect connection pad 214 in those.So-called " flattening projection " be meant in conjunction with the maximum gauge of the surface coverage face of back projection 240 greater than the height of projection 240, promptly projection 240 is subjected to hot pressing to have obvious distortion to cause the phenomenon of collapsing and loosing and enlarging.Usually those flattening projections 240 and those marriage relations of increasing between the projection 230 are metal bondings such as Jin-Jin, Jin-Xi, those flattening projections 240 with those in the electrical connection of connection pads 214 can be metal and press and contact, according to the hot compression parameters difference, also able to produce metal bonding phenomenon.
Please consult shown in Figure 2ly again, preferably, this high-frequency integrated circuit encapsulation structure 200 also includes a resilient coating 270 in addition, and it is arranged between this first surface 211 of this active surface 221 of this chip 220 and this flexible base plate 210.Usually this resilient coating 270 is to be the silica gel of low modulus, multistage curing glue, poly-green onion imines viscosity glued membrane or one of them of epoxy viscose or above-mentioned combination.By this resilient coating 270 and cooperate this flexible base plate 210, between those are to external terminal 250 and this chip 220, produce good stress buffer effect, and can absorb thermal stress, even this chip 220 and the packaging structure external printed circuit board (figure does not draw) below surface engagement has the difference of tangible thermal coefficient of expansion, level still can not directly act on this chip 220 to flexible thermal stress.
In product structure more specifically, also include an adhesive body 260 in addition, can utilize glue to scrawle on this second surface 212 that mode is formed at this flexible base plate 210, to coat those flattening projections 240.This adhesive body 260 can more be formed at this first surface 211 (figure does not draw) of this flexible base plate 210, and it can prevent that aqueous vapor intrusion to this resilient coating 270 from producing hydrolysis around this chip 220; In different embodiment, when this resilient coating 270 has water proofing property, then can not need this adhesive body 260 is formed on this first surface 211 of this flexible base plate 210.
Therefore, in the above-mentioned high-frequency integrated circuit encapsulation structure 200 of the present invention, have the effect that electrical conducting path is short, product is compact, more can continue to use existing encapsulation procedure equipment, and can also promote processing procedure efficient, existing details are as follows with it.
Seeing also shown in Fig. 3 A to Fig. 3 C, is according to the schematic cross-section of this packaging structure of first specific embodiment of the present invention at the electrical connection procedure in inside.See also shown in Fig. 3 A, those increase projection 230 and this resilient coating 270 can be pre-formed on this active surface 221 of this chip 220, aim at those modes of increasing projection 230 with those projection containing holes 213 and locate this flexible base plate 210 and this chip 220.
See also shown in Fig. 3 B, the pressure welding syringe needle 10 of a wire bonder is provided, can derive the bonding wire 20 as elongated gold thread through its inside, the outer end of bonding wire 20 sinters a balling end 21 into, and it is to be those flattening projections 240 before engaging formation.Those balling ends 21 are to increase end face 231 pressings of projection 230 toward those, and under the condition of suitable heating-up temperature and ultrasonic waves friction, those balling ends 21 become the flattening projection 240 that can increase projection 230 in conjunction with those.
It is shown in Figure 4 to see also figure, since in those connection pads 214 be adjacent to those increase projection 230 and with its end face 231 roughly on same routing horizontal plane, so those flattening projections 240 can be bonded to those smoothly and increase projection 230, and those flattening projections 240 with respect to the deflection of those balling ends 21 can make those flattening projections 240 with those in connection pad 214 for electrically connecting, usually the Deformation Height of those flattening projections 240 be those balling ends before routing below 1/2nd.Preferably, connection pads 214 are the air rings (shown in the 4th figure) for hollow in those, with guarantee those flattening projections 240 with those in the electric connection of connection pad 214.Those flattening projections 240 are that the hollow part 214A by connection pad in those 214 is engaged to those and increases projection 230.
According to second specific embodiment of the present invention, please cooperate and consult shown in Figure 5ly, be schematic cross-section according to the another kind of high-frequency integrated circuit encapsulation structure of second specific embodiment of the present invention.Another kind of high-frequency integrated circuit encapsulation structure 300 mainly comprises a flexible base plate 310, a chip 320, several flattening projections 330 and several are to external terminal 340.
This flexible base plate 310 has a first surface 311, a second surface 312 and at least one opening 313, and is provided with connection pad 314 in several.
This chip 320 is arranged on this first surface 311 of this flexible base plate 310, and this chip 320 has an active surface 321 and several weld pads 322 towards this flexible base plate 310.Wherein, line layer of connection pad 314 and connection thereof can be formed at these first surface 311 places of this flexible base plate 310 in those, with close those weld pads 322, to omit the projection of increasing of above-mentioned first embodiment.
Those flattening projections 330 are to be arranged in this opening 313.Because these flexible base plate 310 suitable approaching, and connection pads 314 more are adjacent to those weld pads 322 in those, the electric connection that those flattening projections 330 can directly be bonded to those weld pads 322 and connection pads 314 reach both in those.Usually the height of those flattening projections 330 is between 20～50 microns.
In addition, those are to be arranged on this second surface 312 of this flexible base plate 310 to external terminal 340.In the present embodiment, those can comprise the balling end that routing forms to external terminal 340, and those flattening projections 330 are formed by the balling end that routing forms, so can implement according to this in same routing step, and can simplify processing procedure, but also can form by electroplating.
In addition, one first adhesive body 350 can be formed on this second surface 312 of this substrate, to cover those flattening projections 330;
One second adhesive body 360 can be formed on this first surface 311 of this substrate, and it is positioned at the periphery of this chip 320, can prevent the aqueous vapor intrusion.So this high-frequency integrated circuit encapsulation structure 300 has the effect that meets high frequency encapsulation, compact and low cost of manufacture.
In addition, seeing also shown in Figure 6ly, is the schematic cross-section according to the another kind of high-frequency integrated circuit encapsulation structure of the 3rd specific embodiment of the present invention.The another kind of high-frequency integrated circuit encapsulation structure 400 that the present invention's the 3rd specific embodiment discloses, mainly comprise a substrate 410, a chip 420, several increase projection 430, several flattening projections 440 and several to external terminal 450, and can more include an adhesive body 460.
This substrate 410 has a first surface 411, a second surface 412 and several projection containing holes 413, and is provided with connection pad 414 and several outer connection pads 415 in several.
This chip 420 is to be arranged on this first surface 411 of this substrate 410, and this chip 420 is to have an active surface 421 and several weld pads 422 towards this substrate 410.
In the present embodiment, this substrate 410 can be the BT circuit board, and this chip 420 can be the memory body chip of high frequency.By the active surface 421 of sticking crystal layer 470 bonding these chips 420 and the first surface 411 of this substrate 410.
Those increase projection 430, are arranged on this active surface 421 of this chip 420 being electrically connected to those corresponding weld pads 422, and make those increase projection 430 to be placed in those corresponding projection containing holes 413, to be adjacent to connection pad 414 in those.In the present embodiment, those increase projection 430 is the tie lines projections that form for routing, can be lower than connection pad 414 in those slightly.
Those flattening projections 440, be bonded to those increase projection 430 and with those in connection pad 414 for electrically connecting.In the present embodiment, the tie lines projection that those flattening projections 440 also form for routing, but size is increased projection 430 greater than those, the degree of its flattening can make simultaneously those flattening projections 440 be engaged to those increase projection 430 with those in connection pad 414.
Those are arranged on this second surface 412 of this substrate 410 external terminal 450.
In addition, this adhesive body 460, be can by pressing mold (molding) mode be formed on this first surface 411 of this substrate 410 with this second surface 412 on, with at least a portion and those flattening projections 440 that covers this chip 420.
Therefore, can make to be positioned to engage those simultaneously than upper strata and larger area flattening projection 440 and increase projection 430 and those connection pads 414 that this high-frequency integrated circuit encapsulation structure 400 has the effect that meets high frequency encapsulation, compact and low cost of manufacture by the stack manner of many projections.
Seeing also shown in Fig. 7 A to Fig. 7 D, is according to the processing procedure of the 3rd this packaging structure of specific embodiment of the present invention and structural section schematic diagram wherein.The manufacture method of the above-mentioned high-frequency integrated circuit encapsulation structure 400 that the present invention proposes, its manufacture process may further comprise the steps:
At first, shown in Fig. 7 A, provide this substrate 410 and this chip 420, this sticking crystal layer 470 can print or be attached at the first surface 411 of this substrate 410 in advance.
Shown in Fig. 7 B, after sticking brilliant processing procedure, this substrate 410 mutually combines with this chip 420.At this moment, those weld pads 422 should be aimed at and be revealed in those projection containing holes 413.
Afterwards, shown in Fig. 7 C, in the routing mode several of reduced size are increased on this active surface 421 that projection 430 is arranged at this chip 420, and be placed in those corresponding projection containing holes 413, to be adjacent to connection pad 414 in those.
Afterwards, shown in Fig. 7 D, in the routing mode several flattening projections 440 of large-size are bonded to those and increase projection 430, and make those flattening projections 440 with those in connection pad 414 for electrically connecting, in the present embodiment, those flattening projections 440 are the sections that can have nearly T shape.
At last, can form this adhesive body 460 with those to external terminal 450.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (7)
1. the manufacture method of a high-frequency integrated circuit encapsulation structure is characterized in that it may further comprise the steps:
One substrate is provided, and it has a first surface, a second surface and several projection containing holes, is provided with connection pad in several corresponding to those projection containing holes;
One chip is provided, and it is arranged on this first surface of this substrate, and this chip has an active surface towards this substrate;
Several are set increase projection on this active surface of this chip and be placed in those corresponding projection containing holes, to be adjacent to connection pad in those;
Increase projection in conjunction with several flattening projections to those, and make those flattening projections and those interior connection pads for electrically connecting; And
Several are set to external terminal this second surface in this substrate.
2. the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said those interior connection pads are the air ring of hollow.
3. the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said those flattening projections are to form by routing or by electroplating.
4. the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 3, the Deformation Height that it is characterized in that wherein said those flattening projections be before routing below 1/2nd.
5. the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that it comprises in addition: form an adhesive body on this second surface of this substrate, to coat those flattening projections.
6. the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 5 is characterized in that wherein said adhesive body more is formed on this first surface of this substrate, to cover at least a portion of this chip.
7. the manufacture method of high-frequency integrated circuit encapsulation structure according to claim 1 is characterized in that wherein said those comprise soldered ball to external terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101804175A CN101447443B (en) | 2006-08-15 | 2006-08-15 | Method for manufacturing high-frequency integrated circuit encapsulation structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101804175A CN101447443B (en) | 2006-08-15 | 2006-08-15 | Method for manufacturing high-frequency integrated circuit encapsulation structure |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101112387A Division CN100499096C (en) | 2006-08-15 | 2006-08-15 | Encapsulation structure for high frequency integrated circuit and its making method |
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| Publication Number | Publication Date |
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| CN101447443A CN101447443A (en) | 2009-06-03 |
| CN101447443B true CN101447443B (en) | 2010-06-02 |
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| CN2008101804175A Expired - Fee Related CN101447443B (en) | 2006-08-15 | 2006-08-15 | Method for manufacturing high-frequency integrated circuit encapsulation structure |
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| US8564954B2 (en) * | 2010-06-15 | 2013-10-22 | Chipmos Technologies Inc. | Thermally enhanced electronic package |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195422A (en) * | 1996-06-07 | 1998-10-07 | 松下电器产业株式会社 | Method for mounting semiconductor chip |
| US6316830B1 (en) * | 1998-12-17 | 2001-11-13 | Charles Wen Chyang Lin | Bumpless flip chip assembly with strips and via-fill |
| CN1340857A (en) * | 2000-08-31 | 2002-03-20 | 株式会社日立制作所 | Electronic device and method for manufacturing this device |
-
2006
- 2006-08-15 CN CN2008101804175A patent/CN101447443B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195422A (en) * | 1996-06-07 | 1998-10-07 | 松下电器产业株式会社 | Method for mounting semiconductor chip |
| US6316830B1 (en) * | 1998-12-17 | 2001-11-13 | Charles Wen Chyang Lin | Bumpless flip chip assembly with strips and via-fill |
| CN1340857A (en) * | 2000-08-31 | 2002-03-20 | 株式会社日立制作所 | Electronic device and method for manufacturing this device |
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| CN101447443A (en) | 2009-06-03 |
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