CN101308697B - FIFO burst buffer with large capacity based on SDRAM and data storage method - Google Patents
FIFO burst buffer with large capacity based on SDRAM and data storage method Download PDFInfo
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Abstract
Disclosed are an FIFO burst buffer memory with large capacity based on SDRAM and a data storage method, relating to burst buffer memory. The invention solves the problems of small capacity and high cost on FIFO burst buffer memories and avoids the defect on SDRAM storages that reading and writing operations can not be done at the same time and the defect of low operation efficiency. The SDRAM controller of the invention is a module used to control the SDRAM storage; the master controller is the control center of the whole system, with the responsibility for attempering the whole system; the input buffer memory and the output buffer memory, two FIFOs with small capacity, are respectively used as cushions for input data and output data; the input data first enters the input buffer memory and when the data in the input buffer memory is added up to certain number, the master controller transmits part of the data in the input buffer memory to the SDRAM storage. When the data in the output buffer memory is deficient, the master controller transmits part of the data in the SDRAM storage to the output buffer memory. The FIFO burst buffer memory is low in cost and has a data read-write speed of 75MHz.
Description
Technical field
The present invention relates to a kind of field of the buffer memory that happens suddenly.
Background technology
The burst buffer memory is mainly used in the data transmission between different clock zones or the different pieces of information width interface, and the speed data width different or input data and output data of promptly importing data and output data is different.Mainly contain three kinds of buffer memorys at present.
It is up to a hundred million that first kind of dual-port SRAM, speed can reach soon, can read while write, and address wire may command access site is arranged, and its shortcoming is that capacity is less, generally less than 1MB, can't satisfy jumbo memory requirement, and price is also very high.
Second kind is " table tennis " SDRAM, and so-called " table tennis " just is meant that one is carried out read operation with two SDRAM, and one is carried out write operation, so just can carry out read-write operation simultaneously, and read or write speed can reach 166MHz, and cost is low.Its operation control of shortcoming is very complicated, and area occupied is big on circuit board.
At last a kind of is FIFO burst buffer memory, and FIFO burst buffer memory is a kind of simple to operate reading while write, the memory device of first in first out, and its storage speed is very fast, can reach up to a hundred million.When transfer rate is very high, need jumbo FIFO burst buffer memory, but the burst of FIFO in the market buffer memory capacity is less, generally less than 1MB, and price is very high, is difficult to competent high-speed high capacity metadata cache, utilizes SDRAM to design a FIFO burst buffer memory for memory bank based on this, can be used as the metadata cache of high-speed high capacity, and greatly reduce cost.
The SDRAM storer needs refreshing with the data of being deposited in the assurance SDRAM storer of timing not lose, the effective storage life of data of electric capacity is 64ms in the memory bank at present, that is to say that the cycle period that each row refreshes is 64ms, as the interior 4096 Refresh Cycles/64ms that save as, the line number of each L-BANK in the 4096 expression chips here, that is to say to send and be spaced apart 15.625 μ s, suppose that for convenience of description the clock period that we adopt is 100M, that is to say at most and will refresh every 1562 cycles, all L-BANK quit work in refresh process, need take the regular hour and refresh at every turn, just can enter normal duty afterwards, that is to say that during this period of time all working instruction can only be waited for and can't carry out.Then once more same row is refreshed after the 64ms, so going round and beginning again circulates refreshes.The method that generally adopts is exactly a periodic refreshing now, just stopping other operations through fixing all after date refreshes at once, adopting this method is inappropriate in the design, such as, when the column address figure place is more, when being 11, there are 2048 row in delegation, supposing to read or write a number needs one-period (in fact to affirm more than one-period, because except reading and writing, precharge, operations such as initialization also will occupy some cycles), like this when carrying out a read or write, because burst-length is that delegation just reads or writes 2048 numbers continuously, but when delegation has not has not also read or write fully, will not refresh (otherwise data can be lost) in the middle of the process of writing, thereby this process that reads or writes is not finished.
General read/write operation in buffer memory, all be once a storage unit to be carried out addressing, if read/write just also will be carried out addressing to the next unit of current memory cell continuously, just to constantly send column address and read/write command (row address is constant, so need not be again to the row addressing).Though since read/write postpone identical can allow data to be transmitted in the I/O end be continuous, it has taken a large amount of internal memory controlling resource, can't import new order when data are transmitted continuously, efficient is very low.
Summary of the invention
The present invention is in order to solve little, the problem of ultra-high price of FIFO burst buffer memory capacity, and adopt that the SDRAM storer brought can't finish read-write operation and the low shortcoming of operating efficiency simultaneously, and a kind of FIFO burst buffer with large capacity and date storage method based on SDRAM proposed.
FIFO burst buffer with large capacity based on SDRAM is made up of master controller, sdram controller, input buffer and output state; The data input pin of input buffer is the external data input end, the input buffer control end of reading control end connection master controller of input buffer, and the SDRAM memory data output terminal of input buffer connects the data input pin of sdram controller; The direct output terminal of the data of input buffer connects the direct input end of data of output state; The output state control end of writing control end connection master controller of output state, the SDRAM memory data input end of output state connects the data output end of sdram controller, and the data output end of output state is the external data output terminal; The SDRAM read-write control end of master controller connects the read-write control end of sdram controller.
Date storage method based on the FIFO burst buffer with large capacity of SDRAM:
The course of work of master controller is:
In idle condition s_idle, if satisfy data volume in the input buffer more than or equal to M, and the SDRAM storer is non-when full; Then enter and write state sd_w; Otherwise, enter the s_idle1 state;
In the s_idle1 state, if satisfy in the output state data volume more than or equal to M; Then enter idle condition s_idle; Otherwise, judge further whether the SDRAM storer is empty; If empty, then enter I/O state s_io; If non-NULL then enters read states sd_r;
In I/O state s_io, if satisfy data are arranged in the input buffer, and the data volume in the output state is less than M, then the data in the input buffer are write direct in the output state, and repeat described write operation, no datat in input buffer, perhaps the data volume in the output state more than or equal to M till, return the s_idle state;
In read states sd_r, send out a read request to sdram controller, if receive an effective instruction of sdram controller, then read data from the SDRAM storer enables writing of output state to be changed to effectively then, enters the sd_r1 state; Otherwise, will continue to wait for effective instruction;
In the sd_r1 state, return idle condition s_idle after from the SDRAM storer, reading the data of one page;
In writing state sd_w, send out a write request to sdram controller, if receive an effective instruction of sdram controller, write data in the SDRAM storer then, then with input buffer read enable to be changed to effectively, enter the sd_w1 state, otherwise will continue the wait effective instruction;
In the sd_w1 state, return idle condition s_idle after in the SDRAM storer, writing the data of one page;
The course of work of sdram controller is:
Under the idle condition of sdram controller, if receive the read request that master controller sends, and during SDRAM storer non-NULL, then enter the whole page or leaf burst read data state of sdram controller, run through rebound idle condition behind the whole page data;
Under the idle condition of sdram controller, if receive the write request that master controller sends, and the SDRAM storer less than the time, then enter the whole page or leaf burst write data state of sdram controller, write one and put in order rebound idle condition behind the page data;
Under the idle condition of sdram controller, if both do not have write request also not have read request, the self-refresh state that then enters sdram controller carries out refresh operation, the idle condition of rebound sdram controller after finishing.
Sdram controller of the present invention is the module that is used for controlling the SDRAM storer, and master controller is the control core of total system, is responsible for whole scheduling.Input buffer and output state are the FIFO of two low capacities, respectively as the buffering of input data and the buffering of output data, the input data at first enter input buffer, after the data in the input buffer reach some, by master controller with data importing SDRAM storer in the part input buffer; When in the output state during data deficiencies, data in the part SDRAM storer are exported to output state by master controller.Data write speed reaches as high as 75MHz, cost is low.Buffer of the present invention can be encapsulated in the fpga chip, buffer of the present invention takies resource seldom in described fpga chip, for example, when selecting EP1K10TC100-1 type fpga chip for use, the shared resource of the present invention as shown in Figure 4, taken 85% logical resource, but this chip is a FPGA low side chip, making of FPGA in the middle of the system of control, all use low and middle-end chip at least, the resource that this moment, design took will seldom not need in the application system of reality for use the present invention adds a fpga chip separately, thereby reduce cost.
Description of drawings
Fig. 1 is the structural representation based on the FIFO burst buffer with large capacity of SDRAM; Fig. 2 is the structural representation of embodiment three; Fig. 3 is the workflow diagram based on master controller 1 in the date storage method of the FIFO burst buffer with large capacity of SDRAM; Fig. 4 is the synoptic diagram of the shared resource of system of the present invention.
Embodiment
Embodiment one: in conjunction with Fig. 1 present embodiment is described, it is formed based on FIFO burst buffer with large capacity master controller 1, sdram controller 2, input buffer 3 and the output state 4 of SDRAM; The data input pin of input buffer 3 is the external data input end, the input buffer control end of reading control end connection master controller 1 of input buffer 3, and the SDRAM memory data output terminal of input buffer 3 connects the data input pin of sdram controller 2; The direct output terminal of the data of input buffer 3 connects the direct input end of data of output state 4; The output state control end of writing control end connection master controller 1 of output state 4, the SDRAM memory data input end of output state 4 connects the data output end of sdram controller 2, and the data output end of output state 4 is the external data output terminal; The SDRAM read-write control end of master controller 1 connects the read-write control end of sdram controller 2.
Embodiment two: present embodiment and embodiment one difference are that input buffer 3 and output state 4 are FIFO storeies of two low capacities.Other composition is identical with embodiment one with connected mode.
Embodiment three: present embodiment is described in conjunction with Fig. 2, present embodiment and embodiment one difference are that the total system of present embodiment realizes in FPGA, realize that as the input buffer 3 of data buffering and the small-capacity FIFO module that output state 4 all uses FPGA inside sdram controller 2 adopts the SDRAM storer of SDRAM storer, DDR or the DDRII series of FPGA inside; Other composition is identical with embodiment one with connected mode.
Present embodiment is to adopt VHDL language to write to be applied on the Quartus II software, before using this system, to determine the SDRAM that will adopt, according to selected SDRAM databook, determine some important parameters, the bit wide DSIZE of data, the line number ROWSIZE of each BANK address and columns COLSIZE, BANK counts BANKSIZE, core clock speed clk_core, refresh command duration t
RFC, precharge t effective time
RP, the time interval t of row read write command and row effective order
RCD, read CL in latent period, the time t of mode register is set
MRDThis SDRAM just can be applied in this system after setting these parameters, next step work is the size that input buffer and output state are set in Quartus II, guarantee that input buffer is consistent with SDRAM with the output state data bit width, and they want to store the data volume of SDRAM one whole page or leaf down.Peripheral interface illustrates that in conjunction with Fig. 2 each interface function is described as shown in table 1.
The functional description of table 1 system interface
| Title | Input and output | Bit wide | Functional | |
| clk_core | Input | |||
| 1 | System core clock is with SDRAM frequency together | |||
| reset_n | |
1 | System reset, low level is | |
| wr_req | Input | |||
| 1 | Write signal, flank speed are clk_core/2.2 | |||
| | Input | 1 | Read signal, flank speed are clk_core/2.2 | |
| data_i | Input | Can set | The input data, with the SDRAM data with wide | |
| data_o | Output | Can set | Output data, with the SDRAM data with wide | |
| | Output | 1 | Empty sign, no datat among ' 1 ' the expression | |
| half_full | Output | |||
| 1 | Half-full sign, data are half-full among ' 1 ' the expression FIFO | |||
| | Output | 1 | Full scale will, data are full among ' 1 ' the expression FIFO | |
| usedw_sd | Output | Can set | Sign SDRAM uses the space | |
| Sdram interface | ———— | ———— | Link to each other with SDRAM port of the same name |
Wherein clk_core is the core clock of system, and this clock is used for inputing to SDRAM, with the clock of 166M; Clk_wr is the write data clock, and its flank speed is 75M, is like this to guarantee that data have the time enough transmission in internal system; Clk_rd is for reading clock, and same flank speed is 75M; Reset_n is a reset key, if put low then total system full recovery original state; Data_i is a data input pin; Data_o is a data output end; Empty is empty sign, if among the Big_fifo during no datat, then it puts height, otherwise puts low; Full puts height, otherwise puts low for full zone bit when data are full among the Big_fifo; Half_full is half-full sign, and when data were half-full among the Big_fifo, it put height, otherwise puts low; How many data usedw_sd represents to have stored among the Big_fifo.Other ports are to link to each other with the SDRAM storer, are used for controlling the SDRAM storer.
Chip is selected IS42S16400B (SDRAM), some important parameters is set, DSIZE=16, ROWSIZE=12, COLSIZE=8, BANKSIZE=2, clk_core=166, t earlier
RFC=63, t
RP=16, t
RCD=16, CL=3 (3 clock period), t
MRD=2 (2 clock period).The data bit width of input buffer and output state all is made as 16, because COLSIZE=8, the data volume of one page is 256*16bit, so the degree of depth of input buffer and output state all is made as 512, to guarantee to store the data volume of one page, also to read Enable Pin and write Enable Pin, clear terminal.Set up and use in the middle of just it can being downloaded to FPGA after these parameters.
Embodiment four: present embodiment and embodiment one difference are that input buffer and output state adopt external FIFO storer (can select low-cost small-capacity FIFO for use), remaining control section realizes that in CPLD or FPGA sdram controller 2 adopts the SDRAM storer of SDRAM storer, DDR or the DDRII series of FPGA inside; Other composition is identical with embodiment one with connected mode.
Embodiment five: present embodiment and embodiment one difference are all parts of buffer storage are integrated in the middle of the chip, make the chip of a FIFO.Other composition is identical with embodiment one with connected mode.
Embodiment six: in conjunction with Fig. 3 present embodiment is described, the date storage method based on the FIFO burst buffer with large capacity of SDRAM of present embodiment is: master controller 1 is divided into eight state: s_idle, s_idle1, sd_w, sd_w1, sd_r, sd_r1, s_wait, s_io.Set the capacity (M=2 that M represents SDRAM storer one page
Column address width).
The course of work of master controller 1 is:
In idle condition s_idle, if satisfy data volume in the input buffer 3 more than or equal to M, and the SDRAM storer is non-when full; Then enter and write state sd_w; Otherwise, enter the s_idle1 state;
In the s_idle1 state, if satisfy in the output state 4 data volume more than or equal to M; Then enter idle condition s_idle; Otherwise, judge further whether the SDRAM storer is empty; If empty, then enter I/O state s_io; If non-NULL then enters read states sd_r;
In I/O state s_io, if satisfy in the input buffer 3 data are arranged, and the data volume in the output state 4 is less than M, then the data in the input buffer 3 are write direct in the output state 4, and repeat described write operation, no datat in input buffer 3, perhaps the data volume in the output state 4 more than or equal to M till, return the s_idle state;
In read states sd_r, to 2 read requests of sdram controller, if receive an effective instruction of sdram controller 2, then read data from the SDRAM storer enables writing of output state 4 to be changed to effectively then, enters the sd_r1 state; Otherwise, will continue to wait for effective instruction;
In the sd_r1 state, return idle condition s_idle after from the SDRAM storer, reading the data of one page;
In writing state sd_w, to 2 write requests of sdram controller, if receive an effective instruction of sdram controller 2, write data in the SDRAM storer then, then with input buffer 3 read enable to be changed to effectively, enter the sd_w1 state, otherwise will continue the wait effective instruction;
In the sd_w1 state, return idle condition s_idle after in the SDRAM storer, writing the data of one page;
The course of work of sdram controller 2 is:
Under the idle condition of sdram controller 2, if receive the read request that master controller 1 sends, and during SDRAM storer non-NULL, then enter the whole page or leaf burst read data state of sdram controller 2, run through rebound idle condition behind the whole page data;
Under the idle condition of sdram controller 2, if receive the write request that master controller 1 sends, and the SDRAM storer less than the time, then enter the whole page or leaf burst write data state of sdram controller 2, write one and put in order rebound idle condition behind the page data;
Under the idle condition of sdram controller 2, if both do not have write request also not have read request, the self-refresh state that then enters sdram controller 2 carries out refresh operation, the idle condition of rebound sdram controller 2 after finishing.
Embodiment seven: present embodiment and embodiment six differences are that the read/write operation in the read/write state of sdram controller 2 adopts the burst transfer of SDRAM storer.The burst transfer of SDRAM storer is as long as specify initial column address and burst-length, and internal memory will in turn carry out read/write operation and no longer need controller that column address is provided continuously the storage unit of back respective numbers automatically.Like this, except the transmission of the first stroke data needed several cycles, each data only needs can obtaining of one-period thereafter.Adopt the pattern of full page in the present invention,, can make read or write speed reach maximization like this as long as given initial column address just can be operated a full line.
Embodiment eight: present embodiment is that with embodiment six differences the self-refresh state of sdram controller 2 is to adopt identical at interval time or non-identical time to refresh 4096 times in 64ms.The SDRAM storer that present embodiment adopts refreshes in 64ms 4096 times the requirement that refreshes in fact with exactlying, but is not to refresh identical time of must being separated by, but say need only in 64ms, finish refresh for 4096 times just passable.Therefore in embodiment three, when reading or writing order, read or write, and in the process that reads or writes, do not refresh, in case do not have read write command then once refresh every 20 (this number can as required oneself set) cycles, before owe refresh all and fill, and in 64ms, finish 4096 times and refresh, refreshing each time needed with 58 cycles, here think that the clock of SDRAM storer is 133MHz (clock of SDRAM storer is generally 133MHz and 166MHz), then refreshing for 4096 times needs to use 1.78ms, the time of as seen refreshing consumption is considerably less, can satisfy the requirement that refreshes fully, be reliable through multiple authentication the method.
| Speed | Capacity | Performance | Cost | |
| The present invention | Maximal value can reach 75 MHz | The capacity that depends on SDRAM, SDRAM can be up to last gigabit | Can read while write, first in first out, simple to operate identical with FIFO | Low, the SDRAM price of 1Gb is 120 yuan |
| FIFO | 166MHz | Very little, mainly contain 128K*9bit, 16K*18bit, 64K*9bit etc. now on the market | Can read while write, first in first out, simple to operate, but can't satisfy the storage of high-speed high capacity | Very high, the FIFO price of 64K*18bit is 178 yuan |
| Dual-port SRAM | 166MHz | Very little, mainly contain 128K*9bit, 16K*18bit, 64K*9bit etc. now on the market | Can read while write, storage is simple to operate at random, can't satisfy the storage of high-speed high capacity | Very high, the 16K*36bit price is 183 yuan |
| " table tennis " RAM | 166MHz | The capacity that depends on SDRAM, SDRAM can be up to last gigabit | Can't read while write, control complexity | Low |
Claims (5)
1. based on the FIFO burst buffer with large capacity of SDRAM, it is characterized in that it is made up of master controller (1), sdram controller (2), input buffer (3) and output state (4); The data input pin of input buffer (3) is the external data input end, the input buffer control end of reading control end connection master controller (1) of input buffer (3), the SDRAM memory data output terminal of input buffer (3) connects the data input pin of sdram controller (2); The direct output terminal of the data of input buffer (3) connects the direct input end of data of output state (4); The output state control end of writing control end connection master controller (1) of output state (4), the SDRAM memory data input end of output state (4) connects the data output end of sdram controller (2), and the data output end of output state (4) is the external data output terminal; The SDRAM read-write control end of master controller (1) connects the read-write control end of sdram controller (2).
2. the FIFO burst buffer with large capacity based on SDRAM according to claim 1 is characterized in that input buffer (3) and output state (4) are the FIFO storeies of two low capacities.
3. based on the date storage method of the FIFO burst buffer with large capacity of SDRAM, it is characterized in that
The course of work of master controller (1) is:
In idle condition s_idle, if satisfy data volume in the input buffer (3) more than or equal to M, and the SDRAM storer is non-when full; Then enter and write state sd_w; Otherwise, enter the s_idle1 state;
In the s_idle1 state, if satisfy the middle data volume of output state (4) more than or equal to M; Then enter idle condition s_idle; Otherwise, judge further whether the SDRAM storer is empty; If empty, then enter I/O state s_io; If non-NULL then enters read states sd_r;
In I/O state s_io, if satisfy in the input buffer (3) data are arranged, and the data volume in the output state (4) is less than M, then the data in the input buffer (3) are write direct in the output state (4), and repeat described write operation, no datat in input buffer (3), perhaps the data volume in the output state (4) more than or equal to M till, return the s_idle state;
In read states sd_r, send out a read request to sdram controller (2), if receive an effective instruction of sdram controller (2), then read data from the SDRAM storer enables writing of output state (4) to be changed to effectively then, enters the sd_r1 state; Otherwise, will continue to wait for effective instruction;
In the sd_r1 state, return idle condition s_idle after from the SDRAM storer, reading the data of one page;
In writing state sd_w, send out a write request to sdram controller (2), if receive an effective instruction of sdram controller (2), write data in the SDRAM storer then, then with input buffer (3) read enable to be changed to effectively, enter the sd_w1 state, otherwise will continue to wait for effective instruction;
In the sd_w1 state, return idle condition s_idle after in the SDRAM storer, writing the data of one page;
The course of work of sdram controller (2) is:
Under the idle condition of sdram controller (2), if receive the read request that master controller (1) sends, and during SDRAM storer non-NULL, then enter the whole page or leaf burst read data state of sdram controller (2), run through rebound idle condition behind the whole page data;
Under the idle condition of sdram controller (2), if receive the write request that master controller (1) sends, and the SDRAM storer less than the time, then enter the whole page or leaf burst write data state of sdram controller (2), write one and put in order rebound idle condition behind the page data;
Under the idle condition of sdram controller (2), if both do not have write request also not have read request, the self-refresh state that then enters sdram controller (2) carries out refresh operation, the idle condition of rebound sdram controller (2) after finishing.
4. the date storage method of the FIFO burst buffer with large capacity based on SDRAM according to claim 3 is characterized in that read/write operation in the read/write state of sdram controller (2) adopts the burst transfer of SDRAM storer.
5. the date storage method of the FIFO burst buffer with large capacity based on SDRAM according to claim 3, the self-refresh state that it is characterized in that sdram controller (2) are to adopt that identical time or the non-identical time refreshes in 64ms 4096 times at interval.
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| US5640515A (en) * | 1993-10-28 | 1997-06-17 | Daewoo Electronics Co., Ltd. | FIFO buffer system having enhanced controllability |
| EP0926684B1 (en) * | 1997-12-24 | 2004-02-25 | THOMSON multimedia | Synchronisation device for synchronous dynamic random-access memory |
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2008
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640515A (en) * | 1993-10-28 | 1997-06-17 | Daewoo Electronics Co., Ltd. | FIFO buffer system having enhanced controllability |
| EP0926684B1 (en) * | 1997-12-24 | 2004-02-25 | THOMSON multimedia | Synchronisation device for synchronous dynamic random-access memory |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2007-87436A 2007.04.05 |
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