CN100595917C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN100595917C CN100595917C CN200610079485A CN200610079485A CN100595917C CN 100595917 C CN100595917 C CN 100595917C CN 200610079485 A CN200610079485 A CN 200610079485A CN 200610079485 A CN200610079485 A CN 200610079485A CN 100595917 C CN100595917 C CN 100595917C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 230000008878 coupling Effects 0.000 claims description 20
- 238000010168 coupling process Methods 0.000 claims description 20
- 238000005859 coupling reaction Methods 0.000 claims description 20
- 230000037361 pathway Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 230000013011 mating Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 2
- 235000017060 Arachis glabrata Nutrition 0.000 description 1
- 241001553178 Arachis glabrata Species 0.000 description 1
- 235000010777 Arachis hypogaea Nutrition 0.000 description 1
- 235000018262 Arachis monticola Nutrition 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 235000020232 peanut Nutrition 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005136659A JP4577688B2 (ja) | 2005-05-09 | 2005-05-09 | 半導体チップ選択方法、半導体チップ及び半導体集積回路装置 |
JP2005136659 | 2005-05-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1862810A CN1862810A (zh) | 2006-11-15 |
CN100595917C true CN100595917C (zh) | 2010-03-24 |
Family
ID=37390186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200610079485A Active CN100595917C (zh) | 2005-05-09 | 2006-05-09 | 半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (5) | US7745919B2 (zh) |
JP (1) | JP4577688B2 (zh) |
CN (1) | CN100595917C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104183276B (zh) * | 2013-05-28 | 2019-03-19 | 爱思开海力士有限公司 | 集成电路芯片和包括其的多芯片系统 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4577688B2 (ja) * | 2005-05-09 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体チップ選択方法、半導体チップ及び半導体集積回路装置 |
US7327592B2 (en) | 2005-08-30 | 2008-02-05 | Micron Technology, Inc. | Self-identifying stacked die semiconductor components |
US7352602B2 (en) * | 2005-12-30 | 2008-04-01 | Micron Technology, Inc. | Configurable inputs and outputs for memory stacking system and method |
FR2947948B1 (fr) * | 2009-07-09 | 2012-03-09 | Commissariat Energie Atomique | Plaquette poignee presentant des fenetres de visualisation |
US9160349B2 (en) * | 2009-08-27 | 2015-10-13 | Micron Technology, Inc. | Die location compensation |
US8400781B2 (en) * | 2009-09-02 | 2013-03-19 | Mosaid Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
JP5559507B2 (ja) | 2009-10-09 | 2014-07-23 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びこれを備える情報処理システム |
JP5448698B2 (ja) | 2009-10-09 | 2014-03-19 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びそのテスト方法 |
US8437163B2 (en) * | 2010-02-11 | 2013-05-07 | Micron Technology, Inc. | Memory dies, stacked memories, memory devices and methods |
KR20110112707A (ko) | 2010-04-07 | 2011-10-13 | 삼성전자주식회사 | 층간 연결 유닛을 갖는 적층 메모리 장치, 이를 포함하는 메모리 시스템, 및 전송선의 지연시간 보상 방법 |
JP2012083243A (ja) | 2010-10-13 | 2012-04-26 | Elpida Memory Inc | 半導体装置及びそのテスト方法 |
JP5654855B2 (ja) | 2010-11-30 | 2015-01-14 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP5647014B2 (ja) | 2011-01-17 | 2014-12-24 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP5684590B2 (ja) * | 2011-01-28 | 2015-03-11 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
US8546946B2 (en) * | 2011-04-20 | 2013-10-01 | Nanya Technology Corp. | Chip stack package having spiral interconnection strands |
JP2013004601A (ja) | 2011-06-14 | 2013-01-07 | Elpida Memory Inc | 半導体装置 |
KR101843184B1 (ko) * | 2011-06-16 | 2018-03-29 | 삼성전기주식회사 | 적층형 칩 소자 및 그 제조방법 |
TWI449143B (zh) * | 2011-08-03 | 2014-08-11 | 矽品精密工業股份有限公司 | 用於3d積體電路的電性互連機構 |
JP5657499B2 (ja) | 2011-09-30 | 2015-01-21 | 株式会社東芝 | 半導体装置及びその製造方法、並びに半導体装置の管理システム |
JP2013131534A (ja) * | 2011-12-20 | 2013-07-04 | Elpida Memory Inc | 半導体装置 |
US9240381B2 (en) * | 2013-09-24 | 2016-01-19 | Nanya Technology Corporation | Chip package and method for forming the same |
US10438929B2 (en) * | 2014-09-17 | 2019-10-08 | Toshiba Memory Corporation | Semiconductor device |
US9337146B1 (en) * | 2015-01-30 | 2016-05-10 | Qualcomm Incorporated | Three-dimensional integrated circuit stack |
JP6736441B2 (ja) * | 2016-09-28 | 2020-08-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN115799230B (zh) * | 2023-02-08 | 2023-10-20 | 深圳时识科技有限公司 | 堆叠芯片及电子设备 |
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JPH04112209A (ja) * | 1990-09-03 | 1992-04-14 | Fuji Electric Co Ltd | プログラマブルコントローラ |
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JP3980807B2 (ja) * | 2000-03-27 | 2007-09-26 | 株式会社東芝 | 半導体装置及び半導体モジュール |
JP2002176137A (ja) * | 2000-09-28 | 2002-06-21 | Toshiba Corp | 積層型半導体デバイス |
KR100364635B1 (ko) * | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
JP2003060053A (ja) * | 2001-08-10 | 2003-02-28 | Fujitsu Ltd | 半導体チップ及びそれを用いた半導体集積回路装置及び半導体チップ選択方法 |
JP3959264B2 (ja) * | 2001-09-29 | 2007-08-15 | 株式会社東芝 | 積層型半導体装置 |
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KR100621992B1 (ko) * | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지 |
JP4441328B2 (ja) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
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JP4577688B2 (ja) * | 2005-05-09 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体チップ選択方法、半導体チップ及び半導体集積回路装置 |
JP4507101B2 (ja) * | 2005-06-30 | 2010-07-21 | エルピーダメモリ株式会社 | 半導体記憶装置及びその製造方法 |
JP2007036104A (ja) * | 2005-07-29 | 2007-02-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7772116B2 (en) * | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Methods of forming blind wafer interconnects |
JP4708176B2 (ja) * | 2005-12-08 | 2011-06-22 | エルピーダメモリ株式会社 | 半導体装置 |
JP4753725B2 (ja) * | 2006-01-20 | 2011-08-24 | エルピーダメモリ株式会社 | 積層型半導体装置 |
JP4828251B2 (ja) * | 2006-02-22 | 2011-11-30 | エルピーダメモリ株式会社 | 積層型半導体記憶装置及びその制御方法 |
US7663232B2 (en) * | 2006-03-07 | 2010-02-16 | Micron Technology, Inc. | Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems |
KR100807050B1 (ko) * | 2006-08-23 | 2008-02-25 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
US8492905B2 (en) * | 2009-10-07 | 2013-07-23 | Qualcomm Incorporated | Vertically stackable dies having chip identifier structures |
-
2005
- 2005-05-09 JP JP2005136659A patent/JP4577688B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-05 US US11/418,094 patent/US7745919B2/en active Active
- 2006-05-09 CN CN200610079485A patent/CN100595917C/zh active Active
-
2010
- 2010-04-13 US US12/759,198 patent/US7952201B2/en active Active
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2011
- 2011-04-26 US US13/094,214 patent/US8907463B2/en active Active
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2013
- 2013-01-14 US US13/740,689 patent/US9048239B2/en active Active
-
2015
- 2015-06-01 US US14/727,108 patent/US9640243B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104183276B (zh) * | 2013-05-28 | 2019-03-19 | 爱思开海力士有限公司 | 集成电路芯片和包括其的多芯片系统 |
Also Published As
Publication number | Publication date |
---|---|
US20060267212A1 (en) | 2006-11-30 |
US20100193962A1 (en) | 2010-08-05 |
JP2006313607A (ja) | 2006-11-16 |
US9640243B2 (en) | 2017-05-02 |
US7745919B2 (en) | 2010-06-29 |
CN1862810A (zh) | 2006-11-15 |
US8907463B2 (en) | 2014-12-09 |
US9048239B2 (en) | 2015-06-02 |
US20150262645A1 (en) | 2015-09-17 |
JP4577688B2 (ja) | 2010-11-10 |
US20130187294A1 (en) | 2013-07-25 |
US20110201154A1 (en) | 2011-08-18 |
US7952201B2 (en) | 2011-05-31 |
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