CN100565443C - A kind of adiabatic fifo circuit based on CTGAL - Google Patents

Abstract

The invention discloses a kind of adiabatic fifo circuit based on CTGAL, mainly by memory circuit, read/write operation control circuit and sky/full scale will produces circuit and forms, characteristics are that the read/write operation control circuit comprises the write address low counter, read the address low counter, write address high-positioned counter and read the address high-positioned counter, sky/full scale will produces the full signal of circuit and the designature output terminal of spacing wave is connected with the power clock source input end of reading the address low counter with the write address low counter respectively, the write address low counter is connected with the power clock source input end of reading the address high-positioned counter with the write address high-positioned counter through one-level CTGAL impact damper respectively with the carry signal output terminal of reading the address low counter, advantage is can not produce the metastable state phenomenon, do not need read/write signal is carried out Synchronization Design, compare with the adiabatic fifo circuit based on ECRL, average power consumption saving of the present invention can reach 71%.

Description

A kind of adiabatic fifo circuit based on CTGAL

Technical field

The present invention relates to a kind of fifo circuit, especially relate to a kind of adiabatic fifo circuit based on CTGAL.

Background technology

In the VLSI (very large scale integrated circuit) of existing deep submicron process, one of target of overriding concern when low-power consumption has become chip design.Low-power Technology research has become field more and more important in the integrated circuit (IC) design.Because the adiabatic cmos circuit adopts alternative energy sources, break through traditional disposable energy use-pattern by power supply → electric capacity → ground, realization is by the novel energy reset mode of power supply → electric capacity → power supply, reclaim the energy that is housed on the electric capacity effectively, reduce electric current simultaneously, make the very little pressure drop of maintenance on passive device-resistance, reach the purpose of remarkable reduction power consumption.Various insulating unit circuit particularly based on the insulating unit of cross-couplings type structure, have been realized the recycling of energy effectively, have greatly reduced the power consumption of circuit.First in first out storage stack (first in first out, FIFO) be a kind of data buffer that is used for handling the data transmission problems between the different frequency read/write operation, but adopt the FIFO of traditional cmos circuit design, using more is to be operated in 2 asynchronous FIFOs between the different clocks system, because many big capacitance bus are by frequent access, the power consumption of circuit is very big, and can run into difficult problems such as processing inevitably, be difficult to apply it to complete Circuits System metastable state and asynchronous signal.

Clock transmission gate adiabatic logic (the clocked transmission gate adiabatic logic of our invention, CTGAL) basic circuit as shown in Figure 1, it is a kind of adiabatic circuits with extremely low power dissipation that adopts two-phase not have the overlapping power clock, the operation of CTGAL is divided into 2 grades, and the first order is managed (N by 2 clock NMOS under the control of clock clock Φ ₁, N ₂) (in) samples to input signal; The second level is by the NMOS pipe (N of bootstrapping operation ₃, N ₄) and the P that forms the CMOS-latch structure ₁, N ₅, P ₂, N ₆To load charge-discharge, make output waveform complete, greatly reduced the power consumption of circuit.NMOS pipe (the N that replaces the bootstrapping operation of CTGAL basic circuit among Fig. 1 with the NMOS logical block of complementation ₃, N ₄), can obtain selecting 1 data selector with door, CTGAL or door and CTGAL 2 as Fig. 2, Fig. 3 and CTGAL shown in Figure 4.

Summary of the invention

Technical matters to be solved by this invention provides a kind of adiabatic fifo circuit based on CTGAL, not only has correct logic functions and significant low-power consumption characteristic, and can avoid metastable state and phenomenon such as signal asynchronous effectively.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of adiabatic fifo circuit based on CTGAL, mainly by memory circuit, read/write operation control circuit and sky/full scale will produces circuit and forms, described memory circuit comprises into 16 memory modules of four lines four column distributions, described read/write operation control circuit comprises the write address low counter, read the address low counter, the write address high-positioned counter, read the address high-positioned counter and write and select circuit bank and read to select circuit bank, the designature output terminal that described sky/full scale will produces the full signal of circuit is connected with the power clock source input end of described write address low counter, the designature output terminal that described sky/full scale will produces the spacing wave of circuit is connected with the described power clock source input end of reading the address low counter, the carry signal output terminal of described write address low counter is connected with the power clock source input end of described write address high-positioned counter through one-level CTGAL impact damper, the described carry signal output terminal of reading the address low counter is connected with the described power clock source input end of reading the address high-positioned counter through one-level CTGAL impact damper, the described address low counter of reading connects with corresponding memory module in the described memory circuit through one-level CTGAL impact damper by reading behind the address column code translator, described write address low counter is by the corresponding memory module connection in write address column decoder and the described memory circuit, the described address high-positioned counter of reading connects with corresponding memory module in the described memory circuit through one-level CTGAL impact damper by reading behind the address line code translator, described write address high-positioned counter is by the corresponding memory module connection in write address line decoder and the described memory circuit, described writing selects circuit bank to read to select circuit bank to be connected with corresponding memory module in the described memory circuit respectively with described, the output terminal of described write address column decoder selects the power clock source input end of circuit bank to be connected through one-level CTGAL impact damper with described writing, and the described output terminal of reading the address column code translator reads to select the selection signal input part of circuit bank to be connected through nine grades of CTGAL impact dampers with described.

Described memory module comprises eight dual-ported memories, described storer comprises storage unit and sense amplifier, described dual port memory unit is made of phase inverter and two pairs of access transistors that two head and the tail serial connections form, described storage unit is connected with direct supply, described sense amplifier is the CTGAL basic circuit, and the described output terminal of reading the address column code translator is connected with the power clock source input end of described sense amplifier through nine grades of CTGAL impact dampers.

Described write address low counter and the described address low counter of reading are respectively by seven CTGAL and door, two CTGAL or door and two CTGAL basic circuits compositions, described write address high-positioned counter and the described address high-positioned counter of reading are respectively by six CTGAL and door, two CTGAL or door and two CTGAL basic circuits compositions, described CTGAL in the described write address low counter is connected with the designature output terminal that described sky/full scale will produces the full signal of circuit with the power clock source input end of door and described CTGAL or door, the described described CTGAL that reads in the low counter of address is connected with the designature output terminal that described sky/full scale will produces the spacing wave of circuit with the power clock source input end of door and described CTGAL or door, described CTGAL in the described write address high-positioned counter is connected with the carry signal output terminal of described write address low counter through one-level CTGAL impact damper with the power clock source input end of door and described CTGAL or door, and the described described CTGAL that reads in the high-positioned counter of address is connected with the described carry signal output terminal of reading the address low counter through one-level CTGAL impact damper with the power clock source input end of door and described CTGAL or door.

Described sky/full scale will generation circuit comprises reads status signal circuit, write status signal circuit, the address mark circuit, empty status signal circuit and full scale will circuit, described read status signal circuit and described write status signal circuit respectively by a CTGAL with or the door and a CTGAL basic circuit form, described address mark circuit is made up of with door four CTGAL XOR gate and two CTGAL, described empty status signal circuit is made up of a CTGAL XOR gate and a CTGAL Sheffer stroke gate, described full scale will circuit by a CTGAL with or the door and a CTGAL Sheffer stroke gate form, the described input end of writing status signal circuit is connected with the highest addresses output terminal of described write address high-positioned counter, and the described input end of reading status signal circuit is connected with the described highest addresses output terminal of reading the address high-positioned counter.The output terminal of described write address low counter and the described output terminal of reading the output terminal of address low counter, described write address high-positioned counter and the described output terminal of reading the address high-positioned counter, the described output terminal of writing status signal circuit and the described output terminal of reading status signal circuit are connected with the input end of four CTGAL XOR gate of described address mark circuit respectively.

Described writing selects circuit bank to comprise that eight are write the selection circuit, described writing selects circuit to be made up of four CTGAL basic circuits arranged side by side, the output terminal of described write address column decoder selects the power clock source input end of each CTGAL basic circuit in the circuit to be connected through one-level CTGAL impact damper with described writing, describedly read to select circuit bank to comprise that eight CTGAL four select a data selector, the described output terminal of reading the address column code translator selects a Choice of data selectors signal input part to be connected through nine grades of CTGAL impact dampers with described CTGAL four.

Describedly read address column code translator, described write address column decoder, describedly read the address line code translator and described write address line decoder is made up of with door described CTGAL respectively.

Described CTGAL impact damper is the CTGAL basic circuit.

Compared with prior art, the invention has the advantages that because adiabatic signal rising and falling edges is slow, and satisfy certain phase relation between signal and the power clock, can not produce the metastable state phenomenon; Simultaneously, the read/write clock adopts same power clock, and asynchronous operation does not need read/write signal is carried out Synchronization Design by the control of read/write enable signal; Compare with the adiabatic fifo circuit based on ECRL, average power consumption saving of the present invention can reach 71%.

Description of drawings

Fig. 1 is the schematic configuration diagram and the expression symbol of CTGAL basic circuit;

Fig. 2 is the structural representation and the expression symbol of CTGAL and door;

Fig. 3 is the structural representation and the expression symbol of CTGAL or door;

Fig. 4 selects the structural representation and the expression symbol of 1 data selector for CTGAL 2;

Fig. 5 is a structural representation of the present invention, and the identical line end of all marks links together in side circuit among the figure;

Fig. 6 is the structural representation of dual-ported memory of the present invention;

Fig. 7 is a time sequential routine synoptic diagram of the present invention;

Fig. 8 is the analog result synoptic diagram of part signal when full for FIFO writes;

The analog result synoptic diagram of part signal when Fig. 9 reads sky for FIFO;

The average power consumption analog waveform comparison diagram of Figure 10 when signal " 101010... " being carried out repeatedly read-write operation based on the adiabatic fifo circuit of ECRL with based on the adiabatic fifo circuit of CTGAL.

Embodiment

Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.

A kind of adiabatic fifo circuit based on CTGAL, mainly producing circuit 3 by memory circuit 1, read/write operation control circuit 2 and sky/full scale will forms, memory circuit 1 comprises into 16 memory modules 11 of four lines four column distributions, memory module 11 comprises eight dual-ported memories 12, dual-ported memory 12 comprises storage unit 13 and sense amplifier 14, storage unit 13 is made of phase inverter and two pairs of access transistors that two head and the tail serial connections form, storage unit 13 and direct supply V _DDConnect, sense amplifier 14 is the CTGAL basic circuit; Read/write operation control circuit 2 comprises write address low counter 21, read address low counter 22, write address high-positioned counter 23, read address high-positioned counter 24 and write selection circuit bank 25, read to select circuit bank 26, write address column decoder 27, read address column code translator 28, read address line code translator 29 and write address line decoder 30, write address low counter 21 and read address low counter 22 respectively by seven CTGAL and door, two CTGAL or door and two CTGAL basic circuits compositions, write address high-positioned counter 23 and read address high-positioned counter 24 respectively by six CTGAL and door, two CTGAL or door and two CTGAL basic circuits compositions, write and select circuit bank 25 to comprise that eight are write selection circuit 251, write and select circuit 251 to form by four CTGAL basic circuits arranged side by side, read to select circuit bank 26 to comprise that eight CTGAL four select a data selector 261, write address column decoder 27, read address column code translator 28, write address line decoder 29 and read address line code translator 30 and constitute with door by CTGAL; Sky/full scale will generation circuit 3 comprises reads status signal circuit 31, write status signal circuit 32, address mark circuit 33, empty status signal circuit 34 and full scale will circuit 35, read status signal circuit 31 and write status signal circuit 32 respectively by a CTGAL with or door and a CTGAL basic circuit form, address mark circuit 33 is made up of with door four CTGAL XOR gate and two CTGAL, empty status signal circuit 34 is made up of a CTGAL XOR gate and a CTGAL Sheffer stroke gate, full scale will circuit 35 by a CTGAL with or the door and a CTGAL Sheffer stroke gate form, the input end of writing status signal circuit 32 is connected with the highest addresses output terminal of write address high-positioned counter 23, the input end of reading status signal circuit 31 is connected with the highest addresses output terminal of reading address high-positioned counter 24, the output terminal of write address low counter 21 and the output terminal of reading address low counter 22, the output terminal of write address high-positioned counter 23 and the output terminal of reading address high-positioned counter 24, the output terminal of reading status signal circuit 31 and the output terminal of writing status signal circuit 32 are connected with the input end of four CTGAL XOR gate of address mark circuit 33 respectively, the power clock source input end of each CTGAL basic circuit during the output terminal of write address column decoder 27 passes through one-level CTGAL impact damper and writes selection circuit 251 is connected, the output terminal of reading address column code translator 28 selects the selection signal input part of a data selector 261 to be connected through nine grades of CTGAL impact dampers with each CTGAL four, CTGAL in the write address low counter 21 is connected with the designature output terminal of the full signal of full scale will circuit 35 with the power clock source input end of door with CTGAL or door, the CTGAL that reads in the address low counter 22 is connected with the designature output terminal of the spacing wave of empty status signal circuit 34 with the power clock source input end of door with CTGAL or door, CTGAL in the write address high-positioned counter 23 is connected with the carry signal output terminal of write address low counter 21 through one-level CTGAL impact damper with the power clock source input end of door and CTGAL or door, the CTGAL that reads in the address high-positioned counter 24 is connected with the carry signal output terminal of reading address low counter 22 through one-level CTGAL impact damper with the power clock source input end of door and CTGAL or door, reading address low counter 22 connects with corresponding memory module 11 in the memory circuit 1 through one-level CTGAL impact damper by reading behind the address column code translator 28, write address low counter 21 is by corresponding memory module 11 connections in write address column decoder 27 and the memory circuit 1, reading address high-positioned counter 24 connects with corresponding memory module 11 in the memory circuit 1 through one-level CTGAL impact damper by reading behind the address line code translator 30, write address high-positioned counter 23 is by corresponding memory module 11 connections in write address line decoder 29 and the memory circuit 1, write and select in the circuit bank 25 each to write to select circuit 251 and read to select each CTGAL four in the circuit bank 26 to select a data selector 261 to be connected with corresponding memory module 11 in the memory circuit 1 respectively, the output terminal of reading address column code translator 28 is connected with the power clock source input end of sense amplifier 14 through nine grades of CTGAL impact dampers.In the foregoing description, the CTGAL impact damper is the CTGAL basic circuit.

Basic functional principle of the present invention is as follows: when storehouse does not have sky/full situation, read/write address is effectively and the successively increase along with the read/write enable signal, adopts two quaternary counters of the counter cascade by read/write enable signal Re/We control to produce read/write address.If reading enable signal is Re, reads the address and be designated as Q _R3Q _R2Q _R1Q _R0, Q wherein _R3Q _R2And Q _R1Q _R0Be respectively the output signal of reading address high-positioned counter 24 and reading address low counter 22.Counter adopts Gray code, utilizes map Karnaugh to obtain the Q shown in formula (1) and (2) _R1Q _R0The excitation equation (in like manner can obtain Q _R3Q _R2The excitation equation), carry signal count is by Q _R1And Q _R0With generation.

$\left.\begin{array}{c}{\mathrm{<figure-callout\; id="0"\; label="Q\; R"\; filenames="C2008100611230015H1.png"\; state="\{\{state\}\}">Q</figure-callout>}}_R^0=\stackrel{\&OverBar;}{\mathrm{reset}}(\mathrm{Re}{\stackrel{\&OverBar;}{Q}}_{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C2008100611230015H1.png,C2008100611230016H1.png"\; state="\{\{state\}\}">R</figure-callout>}1}+\stackrel{\&OverBar;}{\mathrm{Re}}{Q}_{R0}),\\ {\stackrel{\&OverBar;}{Q}}_{\mathrm{<figure-callout\; id="0"\; label="R"\; filenames="C2008100611230015H1.png"\; state="\{\{state\}\}">R</figure-callout>}0}^{+}=\mathrm{reset}+\mathrm{<figure-callout\; id="1"\; label="Re\; Q\; R"\; filenames="C2008100611230015H1.png,C2008100611230016H1.png"\; state="\{\{state\}\}">Re</figure-callout>}{Q}_R{1}_{}+\stackrel{\&OverBar;}{\mathrm{Re}}{\stackrel{\&OverBar;}{Q}}_{\mathrm{<figure-callout\; id="0"\; label="R"\; filenames="C2008100611230015H1.png"\; state="\{\{state\}\}">R</figure-callout>}0}.\end{array}\right\}---\left(1\right)$

$\left.\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="Q\; R"\; filenames="C2008100611230015H1.png,C2008100611230016H1.png"\; state="\{\{state\}\}">Q</figure-callout>}}_R^1=\stackrel{\&OverBar;}{\mathrm{reset}}(\mathrm{Re}{\mathrm{<figure-callout\; id="0"\; label="Q\; R"\; filenames="C2008100611230015H1.png"\; state="\{\{state\}\}">Q</figure-callout>}}_R+\stackrel{\&OverBar;}{\mathrm{Re}}{Q}_{R1}),\\ {\stackrel{\&OverBar;}{Q}}_{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C2008100611230015H1.png,C2008100611230016H1.png"\; state="\{\{state\}\}">R</figure-callout>}1}^{+}=\mathrm{reset}+\mathrm{Re}{\stackrel{\&OverBar;}{Q}}_{\mathrm{<figure-callout\; id="0"\; label="R"\; filenames="C2008100611230015H1.png"\; state="\{\{state\}\}">R</figure-callout>}0}+\stackrel{\&OverBar;}{\mathrm{Re}}{\stackrel{\&OverBar;}{Q}}_{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C2008100611230015H1.png,C2008100611230016H1.png"\; state="\{\{state\}\}">R</figure-callout>}1}.\end{array}\right\}---\left(2\right)$

Because reading the variation of address reads the control of enable signal Re except being subjected to, also to be subjected to the constraint of sky marking signal empty, consider phase relation, with the designature empty of empty marking signal empty as the power clock source of reading address low counter 22, reading of data no longer when guaranteeing that storehouse is empty.In addition, the carry signal count that different with common way is reads address low counter 22 is not as the input signal of reading address high-positioned counter 24, but postpones the back as the power clock source of reading address high-positioned counter 24 through the first-level buffer device.Owing to read the constraint that the generation of address current state is subjected to the pairing empty sign empty of previous state, if the sky sign empty of previous state is high, the read operation of current state is invalid, then reads the address and does not change; Otherwise read operation is effective, then reads the address and increases 1.Because the generation from previous state to corresponding empty sign empty needs 3 clock period, the generation of current state also needs a clock period, and each state of reading the address will continue four clock period.Write address Q _W3Q _W2Q _W1Q _W0Generation with to read the address similar, writing enable signal is We, with the designature full of the full scale will signal full power clock source as write address low counter 21.

Memory circuit 1 comprises into 16 memory modules 11 of four lines four column distributions, and the input signal of read/write address ranks code translator is respectively the output signal of read/write address counter.Wherein line decoder produces read/write row selection signal rh _j, wh _j(j=0～3) select corresponding row, and column decoder produces read/write array selecting signal rs _j, ws _j(j=0～3) select corresponding subarray.Row selection signal, each postpones through certain that the back is common activates a pair of corresponding word line (readout word line and write word line) array selecting signal and read/write enable signal, and has only one to be connected in this memory module 11 to word line and to be activated and to be used for carrying out read/write operation in one-period.

For the ease of the generation of the full signal of sky, need the relatively output signal of read/write address counter, promptly require their phase places identical, therefore read enable signal Re and write enable signal We homophase.But in read-write operation to memory module 11, because read-write operation can not carry out simultaneously, in scheduling, adopt and activate write word line earlier, the mode of readout word line is activated in the back, in one-period, carry out the operation of write-then-read, when producing the read/write word line, read enable signal Re than writing the enable signal We first-level buffer of manying device and come time delay.

Because memory circuit 1 every row has four memory modules 11, the bit line of the memory module 11 in the same row connects together, write circuit need realize treating that write data chooses on the bit line of respective column, because each memory module 11 has eight dual-ported memories 12, therefore for whole FIFO storage array, need write eight bit data WD (0)～WD (7) altogether, need eight to write selection circuit 251.Wherein, each is write the writing of power clock source employing memory module 11 of selecting circuit 251 and selects signal ws _jSignal wss after one-level CTGAL buffer delay _jTherefore the write bit line of the subarray that only is activated just has data to write, and all the other all are clamped on zero level, can effectively avoid the write bit line of unactivated memory module 11 is carried out unnecessary discharging and recharging.

Read to select circuit to adopt CTGAL four to select a data selector 261, wherein input signal be the signal on each memory module 11 sense bit lines, data select signal employing memory module 11 read to select signal rs _jSignal rsss after nine grades of CTGAL buffer delay _j, four select a data selector in first order operation only to the SAL of the memory module 11 that is activated _{I, j}Sample, in second level operation this SAL _{I, j}Middle data read into RD (j) end, thereby select to read the data of the memory module 11 that is activated.

Storage unit 13 is the phase inverter (N that formed by two head and the tail serial connections ₁, P ₁And N ₂, P ₂) and two couples of access transistor (N ₃, N ₄And N ₅, N ₆) constitute, as shown in Figure 6.When carrying out write operation, by w _{I, j}Activate N ₅, N ₆Thereby, write bit line wbl is gone up data is written in the storage unit 13; When carrying out read operation, by r _{I, j}Activate N ₃, N ₄Thereby, the data in the storage unit 13 are read on the sense bit line rbl.Though storage unit 13 adopts fixing direct supply V _DDPower supply, but owing to have only ability consumed energy when storage unit 13 is activated, and have only a storage unit 13 in the memory module 11 to be activated in the one-period and carry out read/write operation, can reach the purpose of low-power consumption.

Sense amplifier 14 shown in Figure 6 is the CTGAL basic circuit, uses readout word line r _{I, j}Make the clock clock, memory module 11 read to select signal rs _iSignal rsss after nine grades of CTGAL buffer delay _iAs the power clock source.14 sense datas to the memory module 11 that is activated of sense amplifier are carried out the responsive amplification of adiabatic method, and all the other un-activation memory modules 11 all keep zero level, thereby reduce unnecessary level saltus step, reduce power consumption.

In order to make FIFO energy operate as normal, promptly no longer carry out read operation behind the storehouse sky, no longer carry out write operation after expiring, need indication storehouse sky/full marking signal.Under the dummy status, the read pointer of FIFO is identical with write pointer, and dummy status may occur under the reset mode, when also may occur in read pointer and catch up with write pointer; And under the full state, the read pointer of FIFO is also identical with write pointer, and promptly write pointer just in time circulates and a week caught up with read pointer.In order to distinguish the state of FIFO when the read-write pointer is identical, need follow the tracks of the reading and writing pointer respectively with two marking signal Fr, Fw.When read/write pointer is incremented to the last address that has exceeded FIFO, marking signal Fr/Fw just becomes original designature.So, under the identical situation of read/write address,, just represent that FIFO is in full state if marking signal Fr is different with Fw; If marking signal Fr is identical with Fw, just represent that FIFO is in dummy status.Like this, just can be by relatively reading address Q _R3Q _R2Q _R1Q _R0With write address Q _W3Q _W2Q _W1Q _W0In conjunction with read/write flag signal Fr/Fw, obtain spacing wave empty and the full signal full of FIFO simultaneously.

Time sequential routine of the present invention as shown in Figure 7.T ₁～T ₃During this time, upgrade read/write address by read/write enable signal Re/We, promptly when read/write enable signal Re/We be high level and previous state when showing that storehouse does not have the situation of sky/completely, carry out corresponding read/write operation, read/write address increases progressively; When read/write enable signal Re/We is low level or previous state when showing storehouse sky/full, do not carry out any operation, read/write address is constant.T ₄During this time, carry out the decoding of read/write ranks, produce read/write row selection signal rh with read/write address _i, wh _iWith read/write array selecting signal rs _j, ws _j, begin to prepare data W D to be written simultaneously.T ₅During this time, select signal wh by writing ranks _i, ws _jWith the signal We that writes after enable signal We postpones through the first-level buffer device ₀Write word line of common activation is written to WD among the write bit line wbl of the memory module 11 that is activated, thereby is saved in corresponding storage unit 13.T ₆During this time, select signal rhh by the ranks of reading that postpone through the first-level buffer device _i, rss _jWith the signal Re that reads after enable signal Re passes through the two-stage buffer delay ₁Readout word line of common activation reads into the data in the memory module 11 that is activated on the sense bit line rbl.T ₇During this time, sense amplifier amplifies line SAL to the sensitivity of the memory module 11 that is activated _{I, j}Carry out sensitivity and amplify, simultaneously updating mark signal Fw, Fr.T ₈During this time, to the SAL of each memory module 11 _{I, j}Carry out four and select an operation, the data RD that the memory module 11 that obtains at last being activated is read.

Adopt TSMC 0.25 μ m CMOS technology device parameters, carry out functional simulation based on the adiabatic fifo circuit of CTGAL of the present invention.Fig. 8 has provided the analog result that FIFO writes part signal when full, and in order to simulate situation about writing when full, the initial position that read/write pointer is set is respectively Unit the 0th and the 12nd of FIFO.When the constant and write pointer of read pointer follow write enable signal We and carry out four write operations after, the same unit of read-write pointed i.e. Unit the 0th, this moment, full scale will full was a high level, write pointer will not increase progressively with the arrival of writing enable signal We, up to the read operation sense data is arranged, full scale will full is a low level, just can write next data.Because each state of FIFO read/write address need continue four clock period, so the minimum period of read/write operation is four clock period.

Fig. 9 has shown the situation when FIFO reads sky, and the initial position that read/write pointer is set all points to the 0th unit of FIFO (so spacing wave empty begins to be high level for some time), carries out write operation earlier, since the 0th unit data is write storehouse.When writing the enable signal arrival for second, read enable signal Re and also be provided with effectively, FIFO reads the data that write since Unit the 0th immediately.After the 4th write operation finished, it was invalid to write enable signal We, and write operation suspends, and after the 4th read operation finished, all data that write storehouse all were read out, and was shown as high level after empty sign empty postpones.Before next data write, no matter to read enable signal and whether arrive, read operation is all invalid, and up to there being data to write storehouse, empty sign empty is a low level, just can carry out read operation.

Average power consumption analog waveform when Figure 10 has provided and based on the adiabatic fifo circuit of ECRL with based on the adiabatic fifo circuit of CTGAL signal " 101010... " carried out repeatedly read-write operation.Horizontal ordinate is a simulated time, represents with t, and the energy of ordinate for consuming represented with s.At 1.2us in the time, be 81.17uW based on the average power consumption of the adiabatic FIFO of ECRL, and be 23.51uW that the power consumption saving reaches 71% based on the average power consumption of the adiabatic FIFO of CTGAL.

Claims (7)

1, a kind of adiabatic fifo circuit based on CTGAL, mainly by memory circuit, read/write operation control circuit and sky/full scale will produces circuit and forms, it is characterized in that described memory circuit comprises into 16 memory modules of four lines four column distributions, described read/write operation control circuit comprises the write address low counter, read the address low counter, the write address high-positioned counter, read the address high-positioned counter and write and select circuit bank and read to select circuit bank, the designature output terminal that described sky/full scale will produces the full signal of circuit is connected with the power clock source input end of described write address low counter, the designature output terminal that described sky/full scale will produces the spacing wave of circuit is connected with the described power clock source input end of reading the address low counter, the carry signal output terminal of described write address low counter is connected with the power clock source input end of described write address high-positioned counter through one-level CTGAL impact damper, the described carry signal output terminal of reading the address low counter is connected with the described power clock source input end of reading the address high-positioned counter through one-level CTGAL impact damper, the described address low counter of reading connects with corresponding memory module in the described memory circuit through one-level CTGAL impact damper by reading behind the address column code translator, described write address low counter is by the corresponding memory module connection in write address column decoder and the described memory circuit, the described address high-positioned counter of reading connects with corresponding memory module in the described memory circuit through one-level CTGAL impact damper by reading behind the address line code translator, described write address high-positioned counter is by the corresponding memory module connection in write address line decoder and the described memory circuit, described writing selects circuit bank to read to select circuit bank to be connected with corresponding memory module in the described memory circuit respectively with described, the output terminal of described write address column decoder selects the power clock source input end of circuit bank to be connected through one-level CTGAL impact damper with described writing, and the described output terminal of reading the address column code translator reads to select the selection signal input part of circuit bank to be connected through nine grades of CTGAL impact dampers with described.

2, a kind of adiabatic fifo circuit as claimed in claim 1 based on CTGAL, it is characterized in that described memory module comprises eight dual-ported memories, described dual-ported memory comprises storage unit and sense amplifier, described storage unit is made of phase inverter and two pairs of access transistors that two head and the tail serial connections form, described storage unit is connected with direct supply, described sense amplifier is the CTGAL basic circuit, and the described output terminal of reading the address column code translator is connected with the power clock source input end of described sense amplifier through nine grades of CTGAL impact dampers.

3, a kind of adiabatic fifo circuit as claimed in claim 1 based on CTGAL, it is characterized in that described write address low counter and the described address low counter of reading are respectively by seven CTGAL and door, two CTGAL or door and two CTGAL basic circuits compositions, described write address high-positioned counter and the described address high-positioned counter of reading are respectively by six CTGAL and door, two CTGAL or door and two CTGAL basic circuits compositions, described CTGAL in the described write address low counter is connected with the designature output terminal that described sky/full scale will produces the full signal of circuit with the power clock source input end of door and described CTGAL or door, the described described CTGAL that reads in the low counter of address is connected with the designature output terminal that described sky/full scale will produces the spacing wave of circuit with the power clock source input end of door and described CTGAL or door, described CTGAL in the described write address high-positioned counter is connected with the carry signal output terminal of described write address low counter through one-level CTGAL impact damper with the power clock source input end of door and described CTGAL or door, and the described described CTGAL that reads in the high-positioned counter of address is connected with the described carry signal output terminal of reading the address low counter through one-level CTGAL impact damper with the power clock source input end of door and described CTGAL or door.

4, a kind of adiabatic fifo circuit as claimed in claim 1 based on CTGAL, it is characterized in that described sky/full scale will produces circuit and comprises and read status signal circuit, write status signal circuit, the address mark circuit, empty status signal circuit and full scale will circuit, described read status signal circuit and described write status signal circuit respectively by a CTGAL with or the door and a CTGAL basic circuit form, described address mark circuit is made up of with door four CTGAL XOR gate and two CTGAL, described empty status signal circuit is made up of a CTGAL XOR gate and a CTGAL Sheffer stroke gate, described full scale will circuit by a CTGAL with or the door and a CTGAL Sheffer stroke gate form, the described input end of writing status signal circuit is connected with the highest addresses output terminal of described write address high-positioned counter, the described input end of reading status signal circuit is connected the output terminal of described write address low counter and the described output terminal of reading the address low counter with the described highest addresses output terminal of reading the address high-positioned counter, the output terminal of described write address high-positioned counter and the described output terminal of reading the address high-positioned counter, the described output terminal of writing status signal circuit and the described output terminal of reading status signal circuit are connected with the input end of four CTGAL XOR gate of described address mark circuit respectively.

5, a kind of adiabatic fifo circuit as claimed in claim 1 based on CTGAL, it is characterized in that the described selection circuit bank of writing comprises that eight are write the selection circuit, described writing selects circuit to be made up of four CTGAL basic circuits arranged side by side, the output terminal of described write address column decoder selects the power clock source input end of each CTGAL basic circuit in the circuit to be connected through one-level CTGAL impact damper with described writing, describedly read to select circuit bank to comprise that eight CTGAL four select a data selector, the described output terminal of reading the address column code translator selects a Choice of data selectors signal input part to be connected through nine grades of CTGAL impact dampers with described CTGAL four.

6, a kind of adiabatic fifo circuit based on CTGAL as claimed in claim 1 is characterized in that describedly reading address column code translator, described write address column decoder, describedly reading the address line code translator and described write address line decoder is made up of with door CTGAL respectively.

7, as the described a kind of adiabatic fifo circuit of each claim in the claim 1～6, it is characterized in that described CTGAL impact damper is the CTGAL basic circuit based on CTGAL.

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