CN100549898C - Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance - Google Patents

Abstract

Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance, the feedback network that adopts two-way asymmetric buffer structure to provide simultaneously to have the signals reverse function and have the signal through path of function in the same way, feedback network is used to realize the frequency compensation of LDO circuit and improves transient response performance, through path is used to offset the RHP zero point by the grid leak stray capacitance generation of LDO transfer element, thereby improve the stability of system, expand unity gain bandwidth.That this circuit has is simple in structure, low in energy consumption, can effectively eliminate advantages such as RHP zero point.

Description

Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance

Technical field

The present invention relates to a kind of LDO circuit, particularly a kind ofly utilize two-way asymmetric buffer structure effectively to eliminate RHP zero point in the low pressure difference linear voltage regulator, thereby strengthen loop stability and improve the LDO circuit of system performance.

Background technology

Usually use closed loop negative feedback system in the linear circuit.For example, in low pressure difference linear voltage regulator (LDO, Low-Dropout Voltage Regulator), obtain stable output voltage by using feedback control loop.In order to reduce input and output pressure reduction (Dropout voltage) and to strengthen current driving ability, transfer element among the LDO (be also referred to as transfer tube, adjust pipe, power tube, Pass Element, Power Device etc.) has great breadth length ratio (as 20000 μ m/1 μ m) usually, thereby its grid leak stray capacitance C _GdUsually big (as 10pF).Stray capacitance C _GdMutual conductance g with transfer element _MpForming a frequency is g _Mp/ C _GdRHP ω at zero point _ZRHP, the existence at this zero point has reduced the stability of loop, has restricted unity gain bandwidth and the response speed of LDO.For guaranteeing that closed-loop system can steady operation and realize the design object of high-performance LDO needing to eliminate RHP ω at zero point _ZRHP

Fig. 1 has provided existing first kind and has eliminated the RHP schematic block circuit diagram at zero point, comprises the grid leak stray capacitance C of gain stage 101, LDO transfer element 201, LDO transfer element 201 _Gd202 and zero suppression resistance 203.Node V _i, V ₁And V _oBe respectively the output terminal of input end, output terminal and the LDO of gain stage 101, R ₁, C ₁Be node V ₁Output impedance and lump stray capacitance, R _L, C _LBe node V _oOutput impedance (containing loaded impedance) and load capacitance.Because capacitor C _GdBe the grid leak stray capacitance, therefore can't realize the zero suppression resistance R physically _ZWith capacitor C _GdBe connected in series, this just makes circuit shown in Figure 1 can not eliminate the RHP ω at zero point among the LDO _ZRHP

Fig. 2 has provided existing second kind and has eliminated the RHP schematic block circuit diagram at zero point.This figure is the improvement structure of Fig. 1, comprises the grid leak stray capacitance C of gain stage 101, LDO transfer element 201, LDO transfer element 201 _Gd202, zero suppression resistance 203 and building-out capacitor C _f204.In the circuit shown in Figure 2, from node V _iTo node V _oTransport function be:

$\frac{V_o\left(s\right)}{V_i\left(s\right)}\≈\frac{g_{m1}{R}_1{g}_{\mathrm{mp}}{R}_L[1+s(R_f{C}_f-\frac{C_f+C_{\mathrm{gd}}}{g_{\mathrm{mp}}})-s^2{R}_f{C}_f\frac{C_{\mathrm{gd}}}{g_{\mathrm{mp}}}]}{[1+s{R}_1{g}_{\mathrm{mp}}{R}_L(C_f+C_{\mathrm{gd}})]\{1+s[\frac{C_L}{g_{\mathrm{mp}}}\frac{(C_f+C_{\mathrm{gd}}+C_1)}{(C_f+C_{\mathrm{gd}})}+R_f{C}_f\frac{C_{\mathrm{gd}}}{(C_f+C_{\mathrm{gd}})}]+s^2{R}_f{C}_f\frac{C_L}{g_{\mathrm{mp}}}\frac{(C_1+C_{\mathrm{gd}})}{(C_f+C_{\mathrm{gd}})}\}}$

By following formula as can be known, if R _fC _f＞(C _f+ C _Gd)/g _Mp, then have a left half-plane zero point and RHP zero point in the transport function; If R _fC _f＞＞(C _f+ C _Gd)/g _Mp, then resulting left half-plane zero point is 1/ (R _fC _f), and RHP zero point still be g _Mp/ C _GdTherefore, this circuit can not be eliminated RHP ω at zero point _ZRHPAlso there is following shortcoming in this circuit in addition: a little less than the capacitive load driving force, need to use the large compensation capacitor C _fThereby, increase chip area, reduce the slew rate and the transient response speed of internal node; Supply-voltage rejection ratio (Power Supply Rejection Ratio, the PSRR) performance of LDO have been reduced.

Fig. 3 has provided existing the third and has eliminated the RHP schematic block circuit diagram at zero point, comprises the grid leak stray capacitance C of gain stage 101, LDO transfer element 201, LDO transfer element 201 _Gd202, current buffering level 301, building-out capacitor C _f302 and compensating resistance R _f303.

If dominant pole is positioned at node V ₁, circuit then shown in Figure 3 is from node V _iTo node V _oTransport function be:

$\frac{V_o\left(s\right)}{V_i\left(s\right)}\&ap;\frac{g_{m1}{R}_1{g}_{\mathrm{mp}}{R}_L(1+s{R}_f{C}_f)(1-s\frac{C_{\mathrm{gd}}}{g_{\mathrm{mp}}})}{[1+s{R}_1{g}_{\mathrm{mp}}{R}_L(g_{\mathrm{mf}}{R}_f{C}_f+C_{\mathrm{gd}})][1+s\frac{C_L}{g_{\mathrm{mp}}}\frac{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C20081010600000181.png,C20081010600000182.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_{\mathrm{gd}})}{(g_{\mathrm{mf}}{R}_f{C}_f+C_{\mathrm{gd}})}]}$

By using current buffering level 301, circuit shown in Figure 3 can be blocked by current buffering level 301, building-out capacitor C _f302 and compensating resistance R _fThe through path of 303 corrective networks of forming, thus eliminate by building-out capacitor C _fThe 302 RHP zero points of introducing, but current buffering level 301 can not be eliminated original RHP ω at zero point _ZRHP

Fig. 4 has provided existing the 4th kind and has eliminated the RHP schematic block circuit diagram at zero point, comprises the grid leak stray capacitance C of gain stage 101, LDO transfer element 201, LDO transfer element 201 _Gd202 and forward direction transconductance stage 301.

Small-signal current (the i that forward direction transconductance stage 301 produces _FTS=g _MfV _i) and flow through stray capacitance C _GdSmall-signal current (i _FF=-g _M1v _i) have an opposite phases.Therefore, i _FTSCan be used for offsetting i _FF

Circuit shown in Figure 4 is from node V _iTo node V _oTransport function be:

$\frac{V_o\left(s\right)}{V_i\left(s\right)}\&ap;\frac{g_{m1}{R}_1{g}_{\mathrm{mp}}{R}_L[1+s\frac{C_{\mathrm{gd}}(g_{\mathrm{mf}}-g_{m1})}{g_{m1}{g}_{\mathrm{mp}}}]}{(1+s{R}_1{g}_{\mathrm{mp}}{R}_L{C}_{\mathrm{gd}})(1+s\frac{C_L}{g_{\mathrm{mp}}})}$

By following formula as can be known, if g _Mf=g _M1, then RHP can be eliminated zero point fully; If g _Mf＞g _M1, then can obtain left half-plane zero point.Yet this RHP elimination at zero point mechanism based on the forward direction transconductance stage has following shortcoming: at first, the forward direction transconductance stage can only provide through path, therefore can't realize feedback compensation mechanism.Generally, rely on the grid leak stray capacitance C of transfer element merely _GdBe not sufficient to guarantee loop stability.For this reason, need to add extra feedback compensation circuit, the reduction that this has just increased the complicacy of circuit and might cause response speed and PSRR performance; Secondly, forward direction transconductance stage 301 has increased the complicacy of circuit, has introduced extra offset voltage, and has increased the stray capacitance of gain stage 101 input ends; What is more important, forward direction transconductance stage are suitable for the application scenario that output stage is push-pull type (Push-Pull) or AB class (Class-AB) structure.And in the LDO circuit, output stage is a transfer element, thereby the introducing of forward direction transconductance stage increased the quiescent current of LDO, is unfavorable for low power dissipation design.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, propose a kind ofly can effectively eliminate RHP ω at zero point _ZRHPRealize that frequency compensation, the two-way asymmetric buffer structure that utilizes that feedback loop stable is good, response speed is fast, unity gain bandwidth is wide improve the LDO circuit of performance.

Technical solution of the present invention is: utilize two-way asymmetric buffer structure to improve the LDO circuit of performance, comprise buffer stage, the first backward gain level and LDO transfer element; The input end of buffer stage is a signal input part, the output terminal of buffer stage links to each other with the input end of the first backward gain level, the output terminal of the first backward gain level links to each other with the input end of LDO transfer element, the output terminal of LDO transfer element is the signal output part of LDO circuit, the grid leak stray capacitance C of LDO transfer element _GdBe parallel to the input end and the output terminal of LDO transfer element,

It is characterized in that: between the output terminal of the output terminal of buffer stage and LDO transfer element, also be parallel with two-way asymmetric impact damper, described two-way asymmetric impact damper can provide the feedback network with signals reverse function simultaneously and have the signal through path of function in the same way, and feedback network is used to realize the frequency compensation of LDO circuit and improves transient response performance; Through path is used to offset the grid leak stray capacitance C by the LDO transfer element _GdThe RHP zero point that produces, thereby improve the stability of system, expand unity gain bandwidth, the counteracting mode comprises to be eliminated described RHP zero point fully, described RHP is converted into left half-plane zero point zero point, increases the described RHP frequency at zero point.

Described two-way asymmetric impact damper comprises the second backward gain level, capacitor C _fAnd resistance R _f, second backward gain level and the resistance R _fParallel connection, the output terminal of the second backward gain level is connected to the output terminal of buffer stage, and the input end of the second backward gain level is connected to capacitor C _fAn end, capacitor C _fThe other end be connected to the output terminal of LDO transfer element.

Described feedback network is by the second backward gain level, resistance R _fAnd capacitor C _fForm, have signals reverse and enlarging function, its small-signal gain is 1-g _MfR _f, g wherein _MfBe the mutual conductance of the second backward gain level, R _fBe resistance R _fResistance.

Described through path is by resistance R _fAnd capacitor C _fForm.

The described second backward gain level is MOS transistor or bipolar transistor; When the second backward gain level was MOS transistor, the grid of MOS transistor and drain electrode be respectively as the input end and the output terminal of the second backward gain level, the source ground of MOS transistor or reference potential; When the second backward gain level was bipolar transistor, the base stage of bipolar transistor and collector be respectively as the input end and the output terminal of the second backward gain level, the grounded emitter of bipolar transistor or reference potential.

Between the output terminal of the input end of described buffer stage and LDO transfer element, also include feedback network and error amplifier, the output voltage of feedback network sampling LDO also obtains feedback voltage, and error amplifier is used to amplify the difference between described feedback voltage and the LDO reference voltage; The input end of feedback network links to each other with the output terminal of transfer element, when buffer stage has the signals reverse function, the output terminal of feedback network links to each other with the input end in the same way of error amplifier, the reverse input end of error amplifier links to each other with reference voltage, and the output terminal of error amplifier links to each other with the input end of buffer stage; When buffer stage has signal in the same way during function, the output terminal of feedback network links to each other with the reverse input end of error amplifier, and the input end in the same way of error amplifier links to each other with reference voltage, and the output terminal of error amplifier links to each other with the input end of buffer stage.

Described feedback network is the DC coupling feedback network, or feedback factor is with the feedback network of frequency change, or feedback factor is with the feedback network of frequency change.

Described error amplifier is the single-stage differential amplifier, or has the two-stage or the polystage amplifier of differential signal enlarging function.

Described buffer stage adopts the amplifier with signal differential function to realize.

Described buffer stage be have signal in the same way function buffer stage or have the buffer stage of signals reverse function, it gains less than 1, or equals 1, or greater than 1.

The present invention's advantage compared with prior art is: the two-way asymmetric buffer structure that the present invention adopts, feedback network with signals reverse function can be provided simultaneously and have the signal through path of function in the same way, feedback network is used to realize frequency compensation and improves transient response performance, and through path is used for offsetting (counteracting mode comprise eliminate described RHP zero point fully, described RHP is converted into left half-plane zero point zero point, increases the described RHP frequency at zero point) grid leak stray capacitance C by the LDO transfer element _GdThe RHP ω at zero point that produces _ZRHPThereby, under the situation that does not influence former LDO circuit performance, effectively improve system stability, expand unity gain bandwidth.Two-way asymmetric buffer structure adopts backward gain level and resistance, electric capacity connection in series-parallel can effectively eliminate RHP ω at zero point _ZRHP, the stability of raising LDO circuit has advantages such as simple in structure, low in energy consumption, that imbalance is little.The various electric capacity that relate in the LDO circuit, resistance, buffer stage, gain stage all can adopt conventional structure or circuit, and implementation is easy, and circuit constitutes versatile and flexible.

Description of drawings

Fig. 1 eliminates the RHP schematic block circuit diagram at zero point for existing first kind;

Fig. 2 eliminates the RHP schematic block circuit diagram at zero point for existing second kind;

Fig. 3 eliminates the RHP schematic block circuit diagram at zero point for existing the third;

Fig. 4 eliminates the RHP schematic block circuit diagram at zero point for existing the 4th kind;

Fig. 5 offsets the RHP schematic block circuit diagram at zero point for the present invention;

Fig. 6 eliminates the current canceling schematic diagram of mechanism zero point for RHP of the present invention;

Fig. 7 is that first kind of schematic block circuit diagram shown in Figure 5 realized circuit;

Fig. 8 is that second kind of schematic block circuit diagram shown in Figure 5 realized circuit;

Fig. 9 is the third realization circuit of schematic block circuit diagram shown in Figure 5;

Figure 10 is that the 4th kind of schematic block circuit diagram shown in Figure 5 realized circuit;

Figure 11 is that the 5th kind of schematic block circuit diagram shown in Figure 5 realized circuit;

Figure 12 is that the 6th kind of schematic block circuit diagram shown in Figure 5 realized circuit;

Figure 13 is first kind of typical LDO realization circuit based on schematic block circuit diagram shown in Figure 5;

Figure 14 is second kind of typical LDO realization circuit based on schematic block circuit diagram shown in Figure 5;

Figure 15 is the amplitude-frequency response that LDO shown in Figure 13 realizes circuit;

Figure 16 is the phase-frequency response curve that LDO shown in Figure 13 realizes circuit;

Figure 17 is the load current change curve that LDO shown in Figure 13 realizes circuit;

Figure 18 changes the output voltage change curve that causes for LDO shown in Figure 13 realizes circuit because of load current.

Embodiment

Fig. 5 has provided the present invention and has offset the RHP schematic block circuit diagram at zero point, comprises the grid leak stray capacitance C of buffer stage 401, the first backward gain level 101, LDO transfer element 201, LDO transfer element 201 _Gd202, and by the second backward gain level 301, capacitor C _f302, resistance R _fThe 303 two-way asymmetric buffer structures of forming.Node V _i, V _b, V ₂And V _oBe respectively input end, output terminal, the output terminal of the first backward gain level 101 and the output terminal of LDO of buffer stage 401, R _b, C _bBe node V _bOutput impedance and lump stray capacitance, R ₂, C ₂Be node V ₂Output impedance and lump stray capacitance, R _L, G _LBe node V _oOutput impedance (containing loaded impedance) and load capacitance.

Need to prove that the buffer stage 401 in the theory diagram shown in Figure 5 can be to have the signal buffer stage of function in the same way, also can be the buffer stage with signals reverse function.The gain of buffer stage 401 can be less than or equal to 1, also can be greater than 1.

The second backward gain level 301, resistance R _f303 and capacitor C _f302 have formed the feedback network of two-way asymmetric buffer structure, and its small-signal gain is (1-g _MfR _f), g wherein _MfBe the mutual conductance of the second backward gain level 301, R _fBe resistance R _f303 resistance.。If g _MfR _f＞＞1, then this gain can be approximately-g _MfR _fTherefore, the feedback network of two-way asymmetric impact damper has signals reverse and enlarging function.The through path of two-way asymmetric buffer structure is by resistance R _f303 and capacitor C _f302 form, and have signal function in the same way.

If g _MfR _f＞＞1, R _b＞＞R _f, C _L＞＞max (C _f, C _Gd, C ₂), C _f＞＞C _b, R ₂g _MpR _L(g _M2R _fC _f+ C _Gd(the R of)＞＞ _LC _L+ R ₂C ₂+ R ₂C _Gd), circuit then shown in Figure 5 is from node V _iTo node V _oTransport function be:

$\frac{V_o\left(s\right)}{V_i\left(s\right)}\&ap;-\frac{g_{\mathrm{mb}}{g}_{m2}{R}_2{g}_{\mathrm{mp}}{R}_L(1+\frac{s}{{\mathrm{\&omega;}}_{z1}})(1+\frac{s}{{\mathrm{\&omega;}}_{z2}})}{g_{\mathrm{mf}}(1+\frac{s}{{\mathrm{\&omega;}}_{p-3\mathrm{dB}}})(1+\frac{s}{{\mathrm{\&omega;}}_{p2}})}$

Wherein, ${\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="C20081010600000181.png,C20081010600000182.png"\; state="\{\{state\}\}">z</figure-callout>}1}\&ap;-\frac{g_{\mathrm{mp}}}{(C_2+C_{\mathrm{gd}})/\left(g_{m2}{R}_f\right)-C_{\mathrm{gd}}},$ ${\mathrm{\&omega;}}_{z2}\&ap;-\frac{1}{R_f{C}_f},$

${\mathrm{\&omega;}}_{p-3\mathrm{dB}}\&ap;-\frac{1}{R_2{g}_{\mathrm{mp}}{R}_L(g_{m2}{R}_f{C}_f+C_{\mathrm{gd}})},$ ${\mathrm{\&omega;}}_{p2}\&ap;-\frac{g_{\mathrm{mp}}}{C_L}\frac{(g_{m2}{R}_f{C}_f+C_{\mathrm{gd}})}{(C_2+C_{\mathrm{gd}})},$

By the expression formula of transport function as can be known, two-way asymmetric impact damper has two main effects:

(1) realizes feedback compensation mechanism.The feedback network of two-way asymmetric impact damper has signal amplifying function, capacitor C _f302 equivalent capacitance value increases to g _MpR _Lg _M2R _fC _f, this equivalence electric capacity not only effectively reduces dominant pole frequency, and has increased the frequency of LDO output terminal limit, thereby has realized the abundant separation of two limits;

(2) not only produced left half-plane zero point, and can effectively eliminate by transfer element grid leak stray capacitance C _GdRHP zero point that produces or it is moved to left half-plane.

Fig. 6 has provided the current canceling principle.The first backward gain level 101 and stray capacitance C _GdFormed a forward signal path.Because gain stage 101 is the backward gain level, so this through path has produced from node V _bTo node V _oReverse small-signal current i _FFThereby, cause occurring among the LDO RHP ω at zero point _ZRHPAnd since the use of two-way asymmetric buffer structure, resistance R _f303 and capacitor C _f302 have formed second forward signal path.This through path can produce from node V _bTo node V _oThe i of small-signal current in the same way _{FF_BDAB}It is pointed out that 301 of the second backward gain levels in the two-way asymmetric buffer structure provide feedback network.Because small-signal current i _{FF_BDAB}With small-signal current i _FFHave opposite phases, therefore if both sizes are identical, current i so _{FF_BDAB}Can offset current i fully _FFThereby, eliminate RHP ω at zero point _ZRHPIn addition, if current i _{FF_BDAB}Greater than i _FF, then script is positioned at the ω at zero point of RHP _ZRHPTo change the zero point of left half-plane into.

The transport function expression formula of circuit shown in Figure 5 has also provided identical conclusion:

If (C ₂+ C _Gd)/(g _M2R _f)=C _Gd, then zero point ω _Z1Eliminated fully;

If (C ₂+ C _Gd)/(g _M2R _f)＞C _Gd, then zero point ω _Z1Become left half-plane zero point.

Fig. 7～Figure 10 has provided four kinds of specific implementation circuit of schematic block circuit diagram shown in Figure 5.Wherein the first backward gain level 101 is made up of transistor M2 and Mb1, and Vb1 is the bias voltage of Mb1; LDO transfer element 201 is realized by transistor Mp; The second backward gain level 301 is realized by transistor Mf; In Fig. 7 and Figure 10, buffer stage 401 is made up of transistor Mb and Mb0, and Vb0 is the bias voltage of Mb0; And in Fig. 8 and Fig. 9, buffer stage 401 is realized by transistor Mb.It is pointed out that the active load of the second backward gain level 301, be positioned at from node V as buffer stage 401 _iTo node V _oThrough path in, thereby have advantages such as not increasing extra power consumption, do not introduce imbalance, simplify feedback network.

Need to prove the capacitor C that the present invention mentioned _f, can be any type of electric capacity that integrated circuit fabrication process can be realized, for example mos capacitance, poly-poly electric capacity, metal capacitance etc.; Resistance R _f, also can be any type of resistance that integrated circuit fabrication process can be realized, for example diffusion resistance, interlayer resistance, sheet resistance, poly resistance, be operated in resistance that the metal-oxide-semiconductor of linear zone forms etc.; Load capacitance G _LIt can be the external output filter capacitor of LDO, for example ceramic condenser, electrochemical capacitor, tantalum electric capacity etc. also can be any type of output capacitances integrated on the LDO sheet, that integrated circuit fabrication process can be realized, for example mos capacitance, poly-poly electric capacity, metal capacitance etc.; Capacitor C _GdThe grid leak stray capacitance that can only comprise LDO transfer element 201 also can both comprise the grid leak stray capacitance of LDO transfer element 201, comprised any type of electric capacity that integrated circuit fabrication process can be realized again.

Figure 11 has provided the 5th kind of specific implementation circuit of schematic block circuit diagram shown in Figure 5.Wherein the first backward gain level 101 is made up of transistor M5 and M20; LDO transfer element 201 is realized by transistor Mp; The second backward gain level 301 is realized by transistor Mf; Buffer stage 401 is realized by the partial circuit of operation transconductance amplifier, comprise transistor M1～M4, Mb and bias current sources Ibias, wherein the breadth length ratio of transistor Mb, Mf be respectively transistor M1, M2 breadth length ratio k doubly, k is a positive count, for example 0.5,1,1.5,2,7 etc.

Figure 12 has provided the 6th kind of specific implementation circuit of schematic block circuit diagram shown in Figure 5.Wherein the first backward gain level 101 is made up of transistor M5, M7 and M20; LDO transfer element 201 is realized by transistor Mp; The second backward gain level 301 is realized by transistor Mf; Buffer stage 401 is realized by the partial circuit of operation transconductance amplifier, comprise transistor M1～M4, M6, Mb and bias current sources Ibias, wherein the breadth length ratio of transistor Mb, Mf be respectively transistor M1, M2 breadth length ratio k doubly, k is a positive count, for example 0.5,1,1.5,2,7 etc.

In circuit shown in Figure 11～12, the second backward gain level 301 all is positioned at from node V as the active load of buffer stage 401 _iTo node V _oThrough path in, thereby have advantages such as not increasing extra power consumption, do not introduce imbalance, simplify feedback network.

Need to prove, realize employed buffer stage of schematic block circuit diagram shown in Figure 5 or gain stage, operation transconductance amplifier or other type amplifier, can be any conventional buffer stage or gain stage, operation transconductance amplifier or other type amplifier well known to those of ordinary skill in the art, be not limited to the cited circuit structure of Fig. 7～Figure 12.

First kind of LDO that Figure 13 has provided based on Fig. 5 theory diagram realizes circuit.This LDO circuit is based on circuit structure shown in Figure 7, and difference is: for forming feedback loop, increased feedback network 501 and error amplifier 601 among Figure 13.Wherein, the input end of feedback network 501 and output terminal V _FbBe respectively the output terminal V of LDO _oWith the input end in the same way of error amplifier 601, the reverse input end of error amplifier 601 is connected to fixed reference voltage V _Ref, this reference voltage is provided by voltage reference source circuit usually.The output voltage of feedback network 501 sampling LDO also obtains feedback voltage V _Fb, error amplifier 601 amplifies the output signal V of feedback network 501 _FbWith reference voltage V _RefBetween difference, and the signal after will amplifying exports the input end V of buffer stage 401 to _i If buffer stage 401 has signal function in the same way, then the input end in the same way of error amplifier 601 is connected to fixed reference voltage V _Ref, reverse input end is connected to the output terminal V of feedback network 501 _Fb

Need to prove, error amplifier 601 can be conventional single-stage differential amplifier, for example simple differential amplifier, collapsible (Folded-Cascode) differential amplifier, telescopic (Telescopic-Cascode) differential amplifier etc. also can be two-stage or the polystage amplifier structures with differential signal enlarging function; Feedback network 501 can be DC coupling feedback network (that is the output terminal V of feedback network _FbDirectly and its input end V _oLink to each other), also can be that feedback factor is not with the feedback network of frequency change, feedback network that forms by feedback resistance etc. for example, can also be the feedback network of feedback factor with frequency change, for example at the feedback resistance two ends feedback capacity in parallel, feedback factor not with the output terminal series connection frequency compensated circuit of the feedback network of frequency change, at feedback factor not with the two ends capacitive feedback network in parallel of the feedback network of frequency change etc.

Second kind of typical LDO that Figure 14 has provided based on Fig. 5 theory diagram realizes circuit.This LDO circuit is based on the circuit structure among Figure 12, and difference is: be to form feedback loop, increased feedback network 501 among Figure 14 and with the grid end V of transistor Mb _iOutput terminal V with feedback network 501 _FbLink to each other, and the output terminal V of the input end of feedback network 501 and LDO _oLink to each other.The operation transconductance amplifier of being made up of transistor M1～M7, Mb, Mf, M20 is by amplifying the output signal V of feedback network 501 _FbWith reference voltage V _RefBetween difference, and the signal after will amplifying exports the input end Vb of the first backward gain level 101 and the input end V2 of LDO transfer element 201 to, thus the duty of control transmission element 201, to guarantee the output voltage V of LDO _oBe nominal value.

Need to prove that the typical LDO that Figure 13～14 provide realizes that the just a lot of possible LDO of circuit realize two kinds in the circuit.In fact, according to different circuit design and application conditions, employed buffer stage or gain stage, error amplifier, operation transconductance amplifier or other type amplifier in the LDO circuit, can be buffer stage or gain stage, error amplifier, operation transconductance amplifier or other type amplifier of the known any routine of those of ordinary skill in the art, and be not limited to the cited circuit structure of the present invention.

Eliminate the RHP effect at zero point for further setting forth the present invention, Figure 15～16 have provided the frequency response curve of typical LDO circuit shown in Figure 13 respectively.Simulated conditions is: input voltage VDD is 1.5V, output voltage V _oBe 1.0V, reference voltage V _RefBe 0.3V, resistance R _fBe 20k Ω, capacitor C _fBe 5pF, C _LIntegrated output capacitance on the sheet for 100pF.

In amplitude-frequency response shown in Figure 15, curve 1 corresponding idle condition (that is the load current of LDO is zero), curve 2 corresponding full load conditions (this moment, the load current of LDO was 50mA), the A point is represented the unity gain bandwidth (being about 1.7MHz) of LDO.By curve 1,2 as can be known, the RHP in the loop has obtained effective elimination zero point, and amplitude-frequency response shows as the one-pole system characteristic of approximate ideal.

In phase-frequency response curve shown in Figure 16, curve 3,4 is corresponding idle condition and full load conditions respectively, on behalf of the LDO loop, the B point (be about 125 ° in the phase shift at unity gain bandwidth place, that is phase margin is 55 °), illustrate and use the principle of the invention to eliminate RHP after zero point, loop has advantages of higher stability.

Figure 17～18 have provided the load transient response curve of typical LDO circuit shown in Figure 13.Wherein, Figure 17 has provided the change curve of load current, and Figure 18 has provided the situation of change that load current changes the LDO output voltage that causes.As can be seen from the figure, when load current between 0mA and 50mA during with the speed transients of 50mA/ μ s, the overshoot of output voltage and owe to dash respectively less than 100mV and 80mV.In addition, because LDO has higher unity gain bandwidth, thereby only be 2 μ s Time Created.

Need to prove, though specific implementation circuit and concrete LDO to related counteracting RHP zero point in the specific embodiment of the invention realize that circuit is described, and only are to be used for illustrating content of the present invention to the description that these physical circuits carried out.Under the prerequisite that does not break away from the principle of the invention, can also make the variation and the modification of various equivalences to embodiments of the invention, but its modification will drop in the scope of claim of the present invention all, so the present invention is widely.

Claims (7)

1, utilizes two-way asymmetric buffer structure to improve the LDO circuit of performance, comprise buffer stage (401), the first backward gain level (101) and LDO transfer element (201); The input end of buffer stage (401) is a signal input part, the output terminal of buffer stage (401) links to each other with the input end of the first backward gain level (101), the output terminal of the first backward gain level (101) links to each other with the input end of LDO transfer element (201), the output terminal of LDO transfer element (201) is the signal output part of LDO circuit, the grid leak stray capacitance C of LDO transfer element (201) _Gd(202) be parallel to the input end and the output terminal of LDO transfer element (201),

It is characterized in that: between the output terminal of the output terminal of buffer stage (401) and LDO transfer element (201), also be parallel with two-way asymmetric impact damper, described two-way asymmetric impact damper can provide the feedback network with signals reverse function simultaneously and have the signal through path of function in the same way, and feedback network is used to realize the frequency compensation of LDO circuit and improves transient response performance; Through path is used for offsetting the grid leak stray capacitance C by LDO transfer element (201) _Gd(202) the RHP zero point of Chan Shenging, thereby improve the stability of system, expand unity gain bandwidth, the counteracting mode comprises to be eliminated described RHP zero point fully, described RHP is converted into left half-plane zero point zero point, increases the described RHP frequency at zero point; Described two-way asymmetric impact damper comprises the second backward gain level (301), capacitor C _f(302) and resistance R _f(303), second backward gain level (301) and the resistance R _f(303) parallel connection, the output terminal of the second backward gain level (301) is connected to the output terminal of buffer stage (401), and the input end of the second backward gain level (301) is connected to capacitor C _f(302) a end, capacitor C _f(302) the other end is connected to the output terminal of LDO transfer element (201); Described feedback network is by the second backward gain level (301), resistance R _f(303) and capacitor C _f(302) form, have signals reverse and enlarging function, its small-signal gain is 1-g _MfR _f, g wherein _MfBe the mutual conductance of the second backward gain level (301), R _fBe resistance R _f(303) resistance; Described through path is by resistance R _f(303) and capacitor C _f(302) form.

2, the LDO circuit that utilizes two-way asymmetric buffer structure raising performance according to claim 1, it is characterized in that: the described second backward gain level (301) is MOS transistor or bipolar transistor; When the second backward gain level (301) was MOS transistor, the grid of MOS transistor and drain electrode be respectively as the input end and the output terminal of the second backward gain level (301), the source ground of MOS transistor or reference potential; When the second backward gain level (301) was bipolar transistor, the base stage of bipolar transistor and collector be respectively as the input end and the output terminal of the second backward gain level (301), the grounded emitter of bipolar transistor or reference potential.

3, the LDO circuit that utilizes two-way asymmetric buffer structure raising performance according to claim 1, it is characterized in that: between the output terminal of the input end of described buffer stage (401) and LDO transfer element (201), also include feedback network (501) and error amplifier (601), the output voltage of feedback network (501) sampling LDO also obtains feedback voltage, and error amplifier (601) is used to amplify the difference between described feedback voltage and the LDO reference voltage; The input end of feedback network (501) links to each other with the output terminal of transfer element (201), when buffer stage (401) has the signals reverse function, the output terminal of feedback network (501) links to each other with the input end in the same way of error amplifier (601), the reverse input end of error amplifier (601) links to each other with reference voltage, and the output terminal of error amplifier (601) links to each other with the input end of buffer stage (401); When buffer stage (401) has signal in the same way during function, the output terminal of feedback network (501) links to each other with the reverse input end of error amplifier (601), the input end in the same way of error amplifier (601) links to each other with reference voltage, and the output terminal of error amplifier (601) links to each other with the input end of buffer stage (401).

4, the LDO circuit that utilizes two-way asymmetric buffer structure raising performance according to claim 3, it is characterized in that: described feedback network (501) is the DC coupling feedback network, or feedback factor is with the feedback network of frequency change, or feedback factor is with the feedback network of frequency change.

5, the LDO circuit that utilizes two-way asymmetric buffer structure raising performance according to claim 3, it is characterized in that: described error amplifier (601) is the single-stage differential amplifier, or has the two-stage or the polystage amplifier of differential signal enlarging function.

6, the LDO circuit that utilizes two-way asymmetric buffer structure raising performance according to claim 1, it is characterized in that: described buffer stage (401) adopts the amplifier with signal differential function to realize.

7, the LDO circuit that utilizes two-way asymmetric buffer structure raising performance according to claim 1, it is characterized in that: described buffer stage (401) for have signal in the same way function buffer stage or have the buffer stage of signals reverse function, it gains less than 1, or equals 1, or greater than 1.

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