CN100517677C - Multiple chip packaged conductor frame, its producing method and its package structure - Google Patents
Multiple chip packaged conductor frame, its producing method and its package structure Download PDFInfo
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- CN100517677C CN100517677C CNB2004100778353A CN200410077835A CN100517677C CN 100517677 C CN100517677 C CN 100517677C CN B2004100778353 A CNB2004100778353 A CN B2004100778353A CN 200410077835 A CN200410077835 A CN 200410077835A CN 100517677 C CN100517677 C CN 100517677C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
This invention relates to a multi-chip packaged lead frame and its package structure, in which, the lead frame contains a chip snug and multiple leading pins, in which, a dielectric layer is formed on the lower surface of the snug to be etched to form a relay conductor with a joint region and an insulation layer is formed on it to expose the joint region, a chip or passive element is connected with the leading pins by the relay conductor. The manufacturing method of the frame includes: providing a lead frame set with a chip snug with up and down surfaces and many leading pins, forming a dielectric layer on the lower surface of the snug, etching the snug to become a relay conductor adhered to the dielectric layer and having a joint region, forming an insulation layer on the conductor and exposing its joint region.
Description
Technical field
The present invention is particularly to a kind of lead frame and manufacture method thereof of multicore sheet encapsulation relevant for a kind of lead frame, and comprises the multichip package structure of this lead frame.
Background technology
Multicore sheet encapsulation (multi-chip package, MCP) be at present more and more valued encapsulation technology, it is the chip with a plurality of inequality or same types, even comprise passive component and be incorporated in the semiconductor packaging structure, to reach the characteristic of telotism or Gao Rongneng, but therefore its electrical conducting path can become more complicated, so the chip bearing member of multicore sheet commonly used encapsulation is a Mulitilayer circuit board, in order to reduce packaging cost, the someone attempts in the encapsulation of multicore sheet with the Mulitilayer circuit board of lead frame replacement cheaply.
The TaiWan, China patent announcement is numbered No. 428875 " multiwafer integrated circuit package structure " announcement a kind of multichip package structure that utilizes lead frame, this lead frame includes a chip bearing and a plurality of lead foot, a plurality of chips are attached on this chip bearing, utilize a lead-in wire band (TAB tape) to connect weld pad and those lead foots of those chips, connect difficulty with the cross-line of eliminating bonding wire (bonding wire), but utilize the electric connection board of present lead frame to be wire bonder, be used in the change that will be referred to sealed in unit and bonding wire consumptive material on the lead frame with the TAB technology, in addition, lead-in wire band above the chip bearing or the extra substrate that is provided with are quite expensive at present, and impracticable.
See also shown in Figure 1, the multichip package structure of present common utilization lead frame is with a plurality of chips 30,40,50 are located on the chip bearing 10 of a lead frame, a plurality of bonding wires 61,62,63,64 in order to electrically connect those chips 30,40,50 corresponding lead foots 20 to this lead frame, wherein, those bonding wires 61 connect this chip 30 to the lead foot 20 than nearside, those bonding wires 62 connect this chip 40 to the lead foot 20 than nearside, those bonding wires 63 connect this chip 50 to the lead foot 20 than nearside, when this chip 50 need be electrically connected to lead 20 than the distally, if directly connect and then must stride across this chip 30 or 40 with bonding wire, making that bonding wire is long breasts the tape when pressing mold easily, so bonding wire 64 partly is to connect this chip 50 and this chip 30 earlier, the active surface of this chip 30 should design transit line, bonding wire 61 by other is connected to from the lead foot of this chip 50 than the distally again, therefore, chip must have special connect circuit or rosin joint pad (dummy bonding pad) design, and the semiconductor chip that can't integrate a plurality of general line design is on the chip bearing of a lead frame.
Summary of the invention
Main purpose of the present invention is to provide a kind of lead frame of multicore sheet encapsulation, it includes a chip bearing and a plurality of lead foot, this chip bearing is formed with at least one relaying conductor, one dielectric layer is formed at the lower surface of this chip bearing, to attach this relaying conductor with being electrically insulated, one electrical insulation layer is formed on this relaying conductor and appears at least one bonding land, make one be located at the passive component that chip or on this chip bearing is located on this relaying conductor can be by this relaying conductor and the electric connection of those lead foots.
Secondary objective of the present invention is to provide a kind of lead frame of multicore sheet encapsulation, one chip bearing is formed with at least one relaying conductor with a bonding land, one electrical insulation layer has an insulating surfaces, it is formed between those bonding lands of this relaying conductor, in order to attach a chip or prevent to connect passive component therein the scolder on the bonding land diffuse to other bonding land, to promote the internal wiring of lead frame, reduce the multilayer circuit board member of existing multicore sheet encapsulation.
Lead frame according to multicore sheet encapsulation of the present invention, consist predominantly of a chip bearing, a plurality of lead foots, one dielectric layer and an electrical insulation layer, this chip bearing has a upper surface, an a lower surface and a perforate, this chip bearing is formed with at least one relaying conductor, this relaying conductor is located in this perforate and is had at least one bonding land, this dielectric layer is formed at the lower surface of this chip bearing, to attach this relaying conductor with being electrically insulated, wherein this chip bearing and this relaying conductor are positioned at the same surface of this dielectric layer, this electrical insulation layer is formed on this relaying conductor and manifests this bonding land, preferably, this electrical insulation layer has an insulating surfaces, it is formed between those bonding lands of this relaying conductor, and those lead foots are located at the periphery of this chip bearing.
Comply with the manufacture method of the lead frame of a kind of multicore sheet encapsulation of the present invention, comprising step has:
One lead frame is provided, and this lead frame comprises a chip bearing and a plurality of lead foot, and wherein this chip bearing has a upper surface, a lower surface and a perforate;
Form the lower surface of a dielectric layer in this chip bearing;
This chip bearing of etching, make this chip bearing be formed with at least one relaying conductor, this relaying conductor is attached at this dielectric layer with being electrically insulated and is located in this perforate, and this relaying conductor has a bonding land, and wherein this chip bearing and this relaying conductor are positioned at the same surface of this dielectric layer;
Form the relaying conductor of an electrical insulation layer, and this electrical insulation layer manifests the bonding land of this relaying conductor in this chip bearing.
According to a kind of multichip package structure of the present invention, comprise: a chip bearing, it has a upper surface, a lower surface and a perforate, and this chip bearing is formed with at least one relaying conductor, and this relaying conductor is located in this perforate and is had a bonding land; One dielectric layer, it is formed at the lower surface of this chip bearing, and to attach this relaying conductor, wherein this chip bearing and this relaying conductor are positioned at the same surface of this dielectric layer with being electrically insulated; One electrical insulation layer, it is formed on this relaying conductor and manifests this bonding land; A plurality of lead foots, it is located at the periphery of this chip bearing; A plurality of chips, it is located at this chip bearing; A plurality of bonding wires, it connects those chips and those lead foots, and wherein at least one bonding wire connects the bonding land of wherein at least one chip to this relaying conductor; Chip on this chip bearing or the passive component of being located on the relaying conductor can electrically connect by the lead foot of this relaying conductor and this chip bearing periphery.
According to such scheme, the present invention can make one be located at the passive component that chip or on this chip bearing is located on this relaying conductor can be by this relaying conductor and the electric connection of those lead foots; And can promote the internal wiring of lead frame, reduce the multilayer circuit board member of existing multicore sheet encapsulation.
Description of drawings
Fig. 1 is the vertical view of a plurality of chips on a lead frame of existing multichip package structure.
Fig. 2 is according to first specific embodiment of the present invention, the upper surface schematic diagram of a kind of lead frame of multicore sheet encapsulation behind glutinous crystalline substance and routing.
Fig. 3 is according to first specific embodiment of the present invention, the schematic cross-section of the lead frame of this multicore sheet encapsulation behind glutinous crystalline substance and routing.
Fig. 4 A to 4G is according to first specific embodiment of the present invention, the schematic cross-section of lead frame in manufacture process of this multicore sheet encapsulation.
Fig. 5 is according to second specific embodiment of the present invention, the upper surface schematic diagram of a kind of lead frame of multicore sheet encapsulation behind glutinous crystalline substance and routing.
Fig. 6 is according to second specific embodiment of the present invention, the schematic cross-section of the lead frame of this multicore sheet encapsulation behind glutinous crystalline substance and routing.
The component symbol explanation
10 chip bearings, 20 lead foots
30,40,50 chips, 61,62,63,64 bonding wires
100 lead frames, 110 chip bearings
111 upper surfaces, 112 lower surfaces
113 first relaying conductor 113a bonding lands
114b bonding land, 114a bonding land
115 perforates, 116 nickel-gold layers
120 lead foots, 121 upper surfaces
122 lower surfaces, 130 dielectric layers
140 electrical insulation layers, 141 insulating surfaces
210 first chips, 211 viscoses
220 second chips, 231,232,233,234,235 bonding wires
240 passive components, 250 dry films
251 appear district's 300 lead frames
310 chip bearings, 311 upper surfaces
312 lower surfaces, 313 first relaying conductors
The 313a first bonding land 313b second bonding land
315 perforates of 314 second relaying conductors
320 lead foots, 330 dielectric layers
340 electrical insulation layers, 350 metallic plates
341 insulating surfaces, 411,412,413 chips
421,422 bonding wires, 431,432 passive components
450 scolders
Embodiment
Consult appended graphicly, the present invention will enumerate following embodiment explanation.
According to first specific embodiment of the present invention, see also Fig. 2, shown in 3, a kind of lead frame 100 of multicore sheet encapsulation consists predominantly of a chip bearing 110, a plurality of lead foots 120, one dielectric layer 130 and an electrical insulation layer 140, wherein, this chip bearing 110 has a upper surface 111 and a lower surface 112, those lead foots 120 are located at the periphery of this chip bearing 110, utilize etching technique this chip bearing 110 to be formed with patterning conductor layer or patterning relaying conductors such as at least one first relaying conductor 113 and one second relaying conductor 114, preferably, this chip bearing 110 has a perforate 115, and this first relaying conductor 113 is positioned at this perforate 115 with this second relaying conductor 114.
And this dielectric layer 130 is formed at the lower surface 112 of this chip bearing 110, to attach this chip bearing 110 and this first relaying conductor 113 and this second relaying conductor 114 with being electrically insulated, in the present embodiment, this first relaying conductor 113 is the circuit shape, electrically connect (shown in Fig. 2,3) as one first chip 210 and relaying than distally lead foot 120, this second relaying conductor 114 is an island, in order to engage a passive component 240, preferably, this dielectric layer 130 extends the lower surface that is attached at those lead foots 120, to promote the overall construction intensity of this lead frame.
This electrical insulation layer 140 is formed on this first relaying conductor 113 and this second relaying conductor 114, it can be a welding resisting layer, in the present embodiment, this electrical insulation layer 140 more covers on this dielectric layer 130 between this first relaying conductor 113 and this second relaying conductor 114, wherein this first relaying conductor 113 has a plurality of bonding land 113a, 113b, contiguous this first chip 210 of the bonding land 113a of this first relaying conductor 113, and the contiguous wherein lead foot 120 of a side of another bonding land 113b, and, this second relaying conductor 114 has a plurality of bonding land 114a, 114b, the bonding land 114a of this second relaying conductor 114 is for this passive component 240 of a solder bonds, another bonding land 114b of this second relaying conductor 114 can be connected to this chip 210 or be connected to corresponding lead foot 120 for a plurality of bonding wires 234 for a plurality of bonding wires 232, preferably, a nickel-gold layer 116 can be formed at the bonding land 113a of this first relaying conductor 113, the bonding land 114a of 113b and this second relaying conductor 114,114b.This electrical insulation layer 140 manifests the bonding land 113a of this first relaying conductor 113, the bonding land 114a of 113b and this second relaying conductor 114,114b, and preferably, this electrical insulation layer 140 has an insulating surfaces 141, it is formed on those bonding lands 113a of this first relaying conductor 113, between the 113b and those bonding lands 114a of this second relaying conductor 114, between the 114b, so that one second chip 220 can be attached at this electrical insulation layer 140 on this first relaying conductor 113 and make engage the bonding land 114a of this second relaying conductor 114 and the scolder of this passive component 240 is blocked and can not diffuse to another bonding land 114b of this second relaying conductor 114.
Therefore, when the above-mentioned lead frame 100 of utilization is made a multichip package structure, one first chip 210 and one second chip 220 are as be fixedly arranged on the upper surface 111 of this chip bearing 110 with a viscose 211 or other existing adhesive crystal type, wherein this second chip 220 is located at this electrical insulation layer 140 on this first relaying conductor 113 corresponding to this perforate 115, utilize the electrical isolation of this electrical insulation layer 140, can prevent this second chip 220 and these first relaying conductor, 113 electrical short circuits, perhaps, this second chip 220 can directly be located at this dielectric layer 130 (figure does not draw); One passive component 240 is with the bonding land 114b of solder bonds to those second relaying conductors 114, a plurality of bonding wires 231 connect these first chips 210 and lead foot 120 than nearside, a plurality of bonding wires 235 connect these second chips 220 and lead foot 120 than nearside, a plurality of bonding wires 232 connect this first chip 210 to the bonding land 113a of this first relaying conductor 113 and the bonding land 114b of this second relaying conductor 114, to connect this first chip 210 to this first relaying conductor 113 and this passive component 240, in addition, connect another bonding land 113b of this first relaying conductor 113 to lead foot 120 with a plurality of bonding wires 233 than the distally, and a plurality of bonding wires 234 can connect the bonding land 114b of this second relaying conductor 114 to the lead foot 120 than the distally, so this first chip 210 can utilize this chip bearing 110 to be electrically conducted lead foot 120 to correspondence fully, seal those chips 210 with an adhesive body more at last, 220 with this passive component 240 (figure do not draw), to reach the encapsulation of multicore sheet and to add passive component, can omit the required internally-arranged type Mulitilayer circuit board of existing multicore sheet encapsulation to promote the effect of electrical functionality.
About the manufacture method of this lead frame 100 also illustrate as after, as Fig. 4 A to 4G is the schematic cross-section of this lead frame in manufacture process, at first, see also Fig. 4 A, provide a lead frame 100, this lead frame 100 includes a chip bearing 110 and a plurality of lead foots 120, and this chip bearing 110 has a upper surface 111 and a lower surface 112, and those lead foots 120 have a upper surface 121 and a lower surface 122; Afterwards, see also Fig. 4 B, attach a dielectric layer 130 this lower surface 112 in this chip bearing 110, preferably, this dielectric layer 130 also is attached at this lower surface 122 of this lead foot 120 simultaneously; Afterwards, see also Fig. 4 C, attach a dry film 250 in the upper surface 111 of this chip bearing 110 and the upper surface 121 of those lead foots 120; Afterwards, see also Fig. 4 D, this dry film 250 is carried out exposure imaging, make this dry film 250 be formed with one and appear district 251, it is corresponding to above-mentioned perforate 115 positions except this first relaying conductor 113 and this second relaying conductor 114; Afterwards, see also Fig. 4 E, this chip bearing 110 of etching, forming this first relaying conductor 113 and this second relaying conductor 114 shown in Fig. 2,3, and this first relaying conductor 113 and the second relaying conductor 114 are attached at this dielectric layer 130 with being electrically insulated; Afterwards, see also Fig. 4 F, attaching mode with printing and exposure imaging mode or glued membrane is formed at this electrical insulation layer 140 on this first relaying conductor 113 and this second relaying conductor 114, this electrical insulation layer 140 has an insulating surfaces 141, it is formed between the two bonding land 113a and 113b of this first relaying conductor 113, and manifest those bonding lands 113a, 113b, in the present embodiment, this electrical insulation layer 140 also is covered between two bonding land 114a of this second relaying conductor 114 and the 114b (as shown in Figure 1); At last, see also Fig. 4 G, form a nickel-gold layer 116 in those bonding lands 113a, 113b and those bonding lands 114a and 114b (figure does not draw), in order to the connection of bonding wire with plating mode.
In addition, according to second specific embodiment of the present invention, see also Fig. 5,6, a kind of lead frame 300 of multicore sheet encapsulation consists predominantly of a chip bearing 310, a plurality of lead foots 320, one dielectric layer 330 and an electrical insulation layer 340, this chip bearing 310 has a upper surface 311 and a lower surface 312, those lead foots 320 are located at the periphery of this chip bearing 310, this chip bearing 310 is formed with a plurality of first relaying conductors 313 and at least one second relaying conductor 314, wherein those first relaying conductors 313 are located in the perforate 315 of this chip bearing 310, this second relaying conductor 314 is located at the periphery of this chip bearing 310, can be the vertical bar shape, L shaped or ㄇ shape, those first relaying conductors 313 have a plurality of bonding land 313a, 313b, in order to engage a plurality of passive components 431 and bonding wire 421,422, this dielectric layer 330 is formed at the lower surface 312 of this chip bearing 310, to attach those first relaying conductors 313 and this second relaying conductor 314 with being electrically insulated, this electrical insulation layer 340 is formed on those first relaying conductors 313 and this second relaying conductor 314, and this electrical insulation layer 340 has an insulating surfaces 341, it is formed on those bonding lands 313a of those first relaying conductors 313, between the 313b, and manifest those bonding lands 313a, 313b, do not have the two bonding land 313a that short circuit connects the same first relaying conductor 313 to intercept in order to the scolder that connects this passive component 431, the problem of 313b, preferably, one metallic plate 350 is located under this dielectric layer 330, to promote the heat radiation of a plurality of chips on this chip bearing 310.
Therefore, a plurality of chips 411,412,413 are located at the upper surface 311 of this chip bearing 310, a plurality of bonding wires 421,422 electrically connect those chips 411,412,413 to those lead foots 320, wherein at least one bonding wire 421 connects the bonding land 313a of this chip 411 to the corresponding first relaying conductor 313, this passive component 431 is engaged in a bonding land 313b of two first relaying conductors 313 with scolder 450, and this scolder 450 can not be expanded to another bonding land 313a (as shown in Figure 6) of those first relaying conductors 313 under this electrical insulation layer 340 intercepts, and at least one another bonding wire 422 connects the bonding land 313a of one first corresponding relaying conductor 313 to those lead foots 320, in the present embodiment, another passive component 432 engages the peripheral metal ring (as shown in Figure 5) of this second relaying conductor 314 and this chip bearing 310, connect with relaying as power supply or ground connection, therefore, the lead frame 300 of multicore sheet encapsulation of the present invention can be with a plurality of chips 411,412,413 with those passive components 431,432 are located at the upper surface 311 of this chip bearing 310 and utilize those first relaying conductors 313 and the relaying of this second relaying conductor 314 as chip and lead foot to be electrically conducted, and are encapsulated in the multicore sheet that reaches no substrate on the chip bearing of a lead frame.
Protection scope of the present invention is as the criterion when looking the content that claims define, and anyly knows this skill person, and any variation and the modification done without departing from the spirit and scope of the present invention all belong to protection scope of the present invention.
Claims (17)
1, a kind of lead frame of multicore sheet encapsulation is characterized in that, comprises:
One chip bearing, it has a upper surface, a lower surface and a perforate, and this chip bearing is formed with at least one relaying conductor, and this relaying conductor is located in this perforate and is had a bonding land;
One dielectric layer, it is formed at the lower surface of this chip bearing, and to attach this relaying conductor, wherein this chip bearing and this relaying conductor are positioned at the same surface of this dielectric layer with being electrically insulated;
One electrical insulation layer, it is formed on this relaying conductor and manifests this bonding land;
A plurality of lead foots, it is located at the periphery of this chip bearing.
2, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that this relaying conductor is the circuit shape.
3, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that this relaying conductor is an island.
4, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that other includes a nickel-gold layer, and it is formed at the bonding land of this relaying conductor.
5, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that this relaying conductor has a plurality of bonding lands, and this electrical insulation layer has an insulating surfaces, and it is formed between those bonding lands of this relaying conductor.
6, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that, this dielectric layer extends the lower surface that is attached at those lead foots.
7, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that other includes a metallic plate, and it is located at the below of this dielectric layer.
8, the lead frame of multicore sheet encapsulation as claimed in claim 1 is characterized in that this electrical insulation layer is a welding resisting layer.
9, a kind of manufacture method of lead frame of multicore sheet encapsulation is characterized in that, comprises following steps:
One lead frame is provided, and this lead frame comprises a chip bearing and a plurality of lead foot, and wherein this chip bearing has a upper surface, a lower surface and a perforate;
Form the lower surface of a dielectric layer in this chip bearing;
This chip bearing of etching, make this chip bearing be formed with at least one relaying conductor, this relaying conductor is attached at this dielectric layer with being electrically insulated and is located in this perforate, and this relaying conductor has a bonding land, and wherein this chip bearing and this relaying conductor are positioned at the same surface of this dielectric layer;
Form the relaying conductor of an electrical insulation layer, and this electrical insulation layer manifests the bonding land of this relaying conductor in this chip bearing.
10, the manufacture method of the lead frame of multicore sheet encapsulation as claimed in claim 9 is characterized in that this relaying conductor has a plurality of bonding lands, and this electrical insulation layer has an insulating surfaces, and it is formed between those bonding lands of this relaying conductor.
11, the manufacture method of the lead frame of multicore sheet encapsulation as claimed in claim 9 is characterized in that other installs the below of a metallic plate in this dielectric layer.
12, a kind of multichip package structure is characterized in that, comprises:
One chip bearing, it has a upper surface, a lower surface and a perforate, and this chip bearing is formed with at least one relaying conductor, and this relaying conductor is located in this perforate and is had a bonding land;
One dielectric layer, it is formed at the lower surface of this chip bearing, and to attach this relaying conductor, wherein this chip bearing and this relaying conductor are positioned at the same surface of this dielectric layer with being electrically insulated;
One electrical insulation layer, it is formed on this relaying conductor and manifests this bonding land;
A plurality of lead foots, it is located at the periphery of this chip bearing;
A plurality of chips, it is located at this chip bearing;
A plurality of bonding wires, it connects those chips and those lead foots, and wherein at least one bonding wire connects the bonding land of wherein at least one chip to this relaying conductor;
Chip on this chip bearing or the passive component of being located on the relaying conductor can electrically connect by the lead foot of this relaying conductor and this chip bearing periphery.
13, multichip package structure as claimed in claim 12 is characterized in that, other includes a passive component, and it is engaged in this relaying conductor.
14, multichip package structure as claimed in claim 12 is characterized in that, at least one chip of those chips is located at this electrical insulation layer or this dielectric layer on this relaying conductor.
15, multichip package structure as claimed in claim 12 is characterized in that, this relaying conductor has a plurality of bonding lands, and this electrical insulation layer has an insulating surfaces, and it is formed between those bonding lands of this relaying conductor.
16, multichip package structure as claimed in claim 12 is characterized in that, other includes a metallic plate, and it is located at the below of this dielectric layer.
17, a kind of multichip package structure is characterized in that, comprises:
One chip bearing, it has a upper surface and a lower surface, and this chip bearing is formed with at least one opening;
One dielectric layer, it is formed at the lower surface of this chip bearing, and covers this opening;
At least one patterning relaying conductor, it is located on this dielectric layer, and is positioned at this opening of this chip bearing, and this patterning relaying conductor has a bonding land;
One electrical insulation layer, it is formed on this patterning relaying conductor and manifests this bonding land;
A plurality of lead foots, it is located at the periphery of this chip bearing;
One first chip, it is located at the upper surface of this chip bearing;
One second chip, it is located on this electrical insulation layer;
A plurality of bonding wires, it connects those chips and those lead foots, and wherein at least one bonding wire connects the bonding land of this first chip to this patterning relaying conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100778353A CN100517677C (en) | 2004-09-15 | 2004-09-15 | Multiple chip packaged conductor frame, its producing method and its package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100778353A CN100517677C (en) | 2004-09-15 | 2004-09-15 | Multiple chip packaged conductor frame, its producing method and its package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1750259A CN1750259A (en) | 2006-03-22 |
| CN100517677C true CN100517677C (en) | 2009-07-22 |
Family
ID=36605603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100778353A Active CN100517677C (en) | 2004-09-15 | 2004-09-15 | Multiple chip packaged conductor frame, its producing method and its package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100517677C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050451A (en) * | 2012-12-17 | 2013-04-17 | 华天科技（西安）有限公司 | Double-row pin quad flat no lead packaging piece and insulating treatment method thereof |
| US9147664B2 (en) * | 2013-10-11 | 2015-09-29 | Mediatek Inc. | Semiconductor package |
| US9806053B2 (en) | 2013-10-11 | 2017-10-31 | Mediatek Inc. | Semiconductor package |
| US10163767B2 (en) | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
| CN103928441A (en) * | 2014-03-31 | 2014-07-16 | 华天科技（西安）有限公司 | FCBGA single-chip packaging piece based on adhesive film and manufacturing technology of FCBGA single-chip packaging piece |
| CN103928434A (en) * | 2014-03-31 | 2014-07-16 | 华天科技（西安）有限公司 | FCBGA single-chip package based on Flux and manufacturing process thereof |
-
2004
- 2004-09-15 CN CNB2004100778353A patent/CN100517677C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN1750259A (en) | 2006-03-22 |
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