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Publication numberCN100511594 C
Publication typeGrant
Application numberCN 03817714
PCT numberPCT/US2003/017730
Publication date8 Jul 2009
Filing date5 Jun 2003
Priority date5 Jun 2002
Also published asCN1672244A, EP1518263A1, US7135421, US7554161, US20030227033, US20050023624, WO2003105205A1
Publication number03817714.5, CN 03817714, CN 100511594 C, CN 100511594C, CN-C-100511594, CN03817714, CN03817714.5, CN100511594 C, CN100511594C, PCT/2003/17730, PCT/US/2003/017730, PCT/US/2003/17730, PCT/US/3/017730, PCT/US/3/17730, PCT/US2003/017730, PCT/US2003/17730, PCT/US2003017730, PCT/US200317730, PCT/US3/017730, PCT/US3/17730, PCT/US3017730, PCT/US317730
InventorsKY阿恩, L福尔贝斯
Applicant微米技术有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Hafnium-aluminum oxide dielectric films
CN 100511594 C
Abstract  translated from Chinese
一种含HfAlO<sub>3</sub>的介质薄膜和一种制作这一类介质薄膜的方法生产出了一种可靠的栅介质,它具有的等效氧化物厚度比采用SiO<sub>2</sub>可能得到的要薄。 A HfAlO <sub> 3 </ sub> of the dielectric film and a method of making this type of film containing medium to produce a reliable gate dielectric equivalent oxide thickness it has a specific use SiO <sub> 2 </ sub> may get thinner. 栅介质通过采用铪顺序和铝顺序的原子层沉积法形成。 Gate dielectric is formed by using aluminum and hafnium sequential order of the atomic layer deposition method. 铪顺序采用了HfCl<sub>4</sub>和水蒸气。 Hafnium order using HfCl <sub> 4 </ sub> and water vapor. 铝顺序采用了或者是三甲基铝,Al(CH<sub>3</sub>)<sub>3</sub>,或者DMEAA,一种铝烷(AlH<sub>3</sub>)和二甲基乙胺[N(CH<sub>3</sub>)<sub>2</sub>(C<sub>2</sub>H<sub>5</sub>)]的加成物,加上蒸馏水蒸气。 Aluminium order adopted or trimethyl aluminum, Al (CH <sub> 3 </ sub>) <sub> 3 </ sub>, or DMEAA, an aluminum alkyl (AlH <sub> 3 </ sub>) and dimethylethanamine [N (CH <sub> 3 </ sub>) <sub> 2 </ sub> (C <sub> 2 </ sub> H <sub> 5 </ sub>)] plus into the matter, with distilled water vapor. 这些含HfAlO<sub>3</sub>薄膜的栅介质均是热力稳定的,以致这HfAlO<sub>3</sub>薄膜在加工过程中与硅衬底或其它结构有极微弱的反应。 The gate dielectric containing HfAlO <sub> 3 </ sub> films are heat stable, so it HfAlO <sub> 3 </ sub> film in the process have a very weak reaction with the silicon substrate or other structures.
Claims(42)  translated from Chinese
1. 一种形成电子器件的方法,它包含:通过原子层沉积形成氧化铪铝层,其包括:将含铪前体脉冲输入装有衬底的反应室,在含铪前体脉冲输送期间反应室基本上没有其它反应前体,含铪前体具有不含铝的组成;和将含铝前体脉冲输入反应室,在含铝前体脉冲输送期间反应室基本上没有其它反应前体,含铝前体具有不含铪的组成,其中,脉冲输送含铪前体和脉冲输送含铝前体是在原子层沉积循环中进行的,从而形成氧化铪铝,并且在脉冲输送含铪前体后和在脉冲输送含铝前体后,反应室进行选自如下的过程:抽空反应室、用吹洗气体吹洗反应室以及抽空和吹洗反应室的结合。 A method of forming an electronic device, comprising: a hafnium aluminum oxide layer is formed by atomic layer deposition, comprising: a hafnium-containing precursor pulse input substrate containing reaction chamber during the precursor pulsing a hafnium-containing reaction The reaction chamber is substantially free of other precursors, hafnium-containing precursor having a composition free of aluminum; aluminum-containing precursor and the pulse input chamber, an aluminum-containing precursor in the reaction chamber conveyance pulse period substantially before the other reactants, comprising hafnium precursor with an aluminum-free composition, wherein pulsing a hafnium-containing precursor and pulsing the aluminum-containing precursor in atomic layer deposition cycle is carried out, thereby forming a hafnium aluminum oxide, and hafnium-containing transport body after prepulse After pulsing and process aluminum-containing precursor, the reaction chamber is selected from the following: evacuation of the reaction chamber, washed with blowing gas purge reaction chamber and a combination of evacuation and purging of the reaction chamber.
2. 权利要求l的方法,其中所述方法包括控制若干次的脉冲输送含铪前体的循环和若干次的脉冲输送含铝前体的循环以在氧化铪铝层中包括预定量的氧化铪。 2. The method of claim l, wherein said method comprises controlling a number of pulsing cycles and cycles containing several of pulsing a hafnium precursor with an aluminum-containing precursor comprises a predetermined amount of hafnium oxide layer in an aluminum hafnium oxide .
3. 权利要求1或2的方法,其中形成电子器件包括形成晶体管, 这方法包括:在衬底上形成第一和第二源/漏区,第一源/漏区和第二源/漏区被主体区分开;将含铪前体脉冲输入反应室和将含铝前体脉沖输入以便在位于在第一和第二源/漏区之间的主体上形成介质薄膜;和使栅与介质薄膜耦合。 3. The method of claim 1 or claim 2, wherein forming an electronic device includes forming a transistor, which method comprises: forming a first and second source / drain region, a first source / drain region and the second source / drain regions in the substrate separated by subject area; hafnium-containing precursor pulse input of the reaction chamber and the aluminum-containing precursor pulse input to form a thin film on the medium located between the first and second source / drain regions of the body; and the gate and the dielectric film coupling.
4. 权利要求1或2的方法,其中形成电子器件包括形成存储器, 它至少有一个这样的存取晶体管,它在位于第一和第二源/漏区之间的主体区上有含HfAI03的薄膜,其中形成这薄膜包括脉冲输送含铪前体和脉冲输送含铝前体。 Method 1 or claim 2, wherein forming an electronic device includes forming a memory, such that at least one access transistor, which is located in the body region of the first and second source / drain regions having there between HfAI03 film, wherein forming this film includes hafnium-containing precursor pulsing pulsing and aluminum-containing precursors.
5. 权利要求4的方法,其中该方法包括形成若干个存取晶体管;形成若干条字线,它们与存取晶体管数目相同的若干个栅相耦合;形成若干条源线,它们与存取晶体管数目相同的若干个第一源/漏区相耦合;形成若干条位线,它们与存取晶体管数目相同的若干个第二源/漏区相耦合。 The method of claim 4, wherein the method comprises forming a plurality of access transistors; forming a plurality of word lines, they are the same number of a plurality of access transistors coupled to the gate; forming a plurality of source lines, they access transistor the same number of a plurality of first source / drain region coupled; forming a plurality of bit lines, the number of access transistor are the same number of second source / drain region coupled.
6. 权利要求1或2的方法,其中形成电子器件包括形成电子系统,其包括:提供处理机;使存储器与处理机相耦合,其中存储器或处理机之一至少有一个这样的晶体管,它在位于第一和笫二源/漏区之间的主体区上有含HfA103的薄膜,这种含HfA103的薄膜通过将含铪前体脉冲输入反应室和将含铝前体脉冲输入反应室的方法形成;和形成系统总线,该总线使处理器与存储器阵列相耦合。 6. The method of claim 1 or claim 2, wherein forming an electronic device includes forming an electronic system, comprising: providing a processor; and the processor makes a memory coupled to the at least one memory or processor one such transistor, in which a thin film containing HfA103 located in the main area of the first and second undertaking of the source / drain regions on this film by HfA103 containing the reaction chamber and the method of aluminum-containing precursor pulses fed to the reaction chamber containing hafnium precursor pulse input form; and forming a system bus that enables the processor coupled to the memory array.
7. 权利要求l, 2, 3, 4或6的方法,其中将含铪前体脉冲输入反应室,随后将第一含氧前体脉冲输入反应室,然后将含铝前体脉冲输入反应室,接着将第二含氧前体脉冲输入反应室。 L 7. Claim 2, Method 3, 4 or 6, wherein the hafnium-containing precursor pulses fed to the reaction chamber, followed by the first oxygen-containing precursor pulses fed to the reaction chamber, and then the aluminum-containing precursor pulse input chamber Then the second oxygen-containing precursor pulse input reaction chamber.
8. 权利要求7的方法,其中脉冲输送第一含氧前体包括脉冲输送水蒸气。 The method of claim 7, wherein the first oxygen-containing precursor pulsing includes pulsing water vapor.
9. 权利要求7的方法,其中脉冲输送第二含氧前体包括脉冲输送蒸镏水蒸气。 The method of claim 7, wherein the pulsing of the second oxygen-containing precursor comprises pulsing steam distillation.
10. 权利要求7的方法,其中脉冲输送第二含氧前体包括脉冲输送氧。 10. The method of claim 7, wherein the pulsing of the second oxygen-containing precursor comprises pulsing oxygen.
11. 权利要求l, 2, 3, 4或6的方法,其中按照预定的周期对将每种前体脉冲输入反应室加以控制,预定的周期则根据被脉冲输入反应室的每种前体分别地加以确定。 L 11. claimed in claim 2, Method 3, 4 or 6, wherein the predetermined period of each precursor pulse input to control the reaction chamber, the predetermined period is based on the pulse input of each of the reaction chambers are precursors to be determined.
12. 权利要求l, 2, 3, 4或6的方法,其中该方法包括,使衬底保持在根据每次脉冲输送的前体选定的温度下,这选定的温度根据脉冲输送的每种前体独立地设定。 L each of this pulsing according to the selected temperature to claim 12. The process of 2, 3, 4 or 6, wherein the method comprises, according to the substrate is maintained at each pulsing of a precursor selected temperature, set independently precursors.
13. 权利要求l, 2, 3, 4或6的方法,其中在每次脉冲输送前体之后,接着用吹洗气体吹洗反应室。 L 13. claimed in claim 2, Method 3, 4 or 6, wherein after each pulse before the transport body, followed by a purge gas purge reaction chamber.
14. 权利要求l, 2, 3, 4或6的方法,其中该方法包括重复进行若干次脉沖输送含铪前体和含铝前体的循环。 L 14. Claim 2, Method 3, 4 or 6, wherein the method comprises repeating the cycle several times pulsing a hafnium-containing precursor and an aluminum-containing precursor.
15. 权利要求14的方法,其中在重复进行若干次脉冲输送含铪前体和含铝前体循环之后,接着在300'C〜800。 15. The method of claim 14, wherein the repeated several times after pulsing a hafnium-containing precursor and an aluminum-containing precursor circulation, followed 300'C~800. C的温度下进行退火处理。 Then annealed at a temperature of C's.
16. 权利要求l, 2, 3, 4或6的方法,其中该方法包括独立地控制每种前体的脉冲周期的时间,被脉冲输送到衬底上的前体的次数,和衬底的温度,以便形成含HfA103的介质薄膜,这介质薄膜具有的介电常数为9-25。 L 16. claim, Tier 2, 3, 4 or 6, wherein the method comprises independently controlling each precursor pulse period of time, is pulsed into the number of precursors on the substrate, and the substrate temperature, to form a dielectric film containing HfA103, which dielectric film having a dielectric constant of 9-25.
17. 权利要求16的方法,其中形成含HfA103的介质薄膜包括形成一种基本上是HfA103的薄膜。 17. The method of claim 16, wherein the dielectric film is formed containing HfA103 comprises forming a substantially HfA103 the film.
18. 权利要求l, 2, 3, 4或6的方法,其中脉冲输送含铪前体包括脉冲输送HfCl4前体。 L 18. claimed in claim 2, Method 3, 4 or 6, wherein pulsing a hafnium-containing precursor comprises pulsing HfCl4 precursor.
19. 权利要求18的方法,其中将HfCU前体脉冲输入反应室是在使衬底的温度保持在350C〜5501C的条件下进行的。 19. The method of claim 18, wherein the precursor pulse input HfCU the reaction chamber in the substrate is maintained at a temperature of 350 C~5501C conditions.
20. 权利要求18的方法,其中将HfCl4前体脉沖输入反应室是在HfCU前体的温度为130C〜154。 20. The method of claim 18, wherein the precursor is HfCl4 pulse is fed to the reaction chamber at a temperature HfCU precursor is 130 C~154. C的条件下进行的。 Under C of conditions.
21. 权利要求18的方法,其中该方法包括在脉冲输送HfCL(前体之后,以0.5 mPam"秒〜1.0mPam"秒的流速将笫一含氧前体脉冲输入反应室。 21. The method of claim 18, wherein the method comprises, after pulsing HfCL (precursor to 0.5 mPam "second ~1.0mPam" sec flow rate of the oxygen-containing precursor pulse Zi entered the reaction chamber.
22. 权利要求l, 2, 3, 4或6的方法,其中脉冲输送含铝前体包括将三甲基铝前体脉沖输入反应室。 L 22. claimed in claim 2, Method 3, 4 or 6, wherein the aluminum-containing precursor comprises pulsing trimethyl aluminum precursor pulse input of the reaction chamber.
23. 权利要求22的方法,其中将三甲基铝前体脉冲输入反应室是在使衬底温度保持在350C〜370。 23. The method of claim 22, wherein the precursor is trimethyl aluminum pulse input is in the reaction chamber so that the substrate temperature was kept at 350 C~370. C的条件下进行的。 Under C of conditions.
24. 权利要求22的方法,其中将三甲基铝前体脉冲输入反应室是在压力为230 m托的条件下进行的。 24. The method of claim 22, wherein trimethyl aluminum precursor pulse is fed to the reaction chamber at a pressure of 230 m Torr conditions.
25. 权利要求l, 2, 3, 4或6的方法,其中脉冲输送含铝前体包括将DMEAA前体脉冲输入反应室。 L 25. claimed in claim 2, Method 3, 4 or 6, wherein the aluminum-containing precursor comprises pulsing the pulse input DMEAA precursor reaction chamber.
26. 权利要求25的方法,其中将DMEAA前体脉冲输入反应室是在使衬底温度保持在350C -55(TC的条件下进行的。 26. The method of claim 25, wherein the precursor pulse input DMEAA the reaction chamber is maintained at the substrate temperature at 350 C -55 (carried out under the conditions of TC.
27. 权利要求25的方法,其中将DMEAA前体脉冲输入反应室是在压力为30m托的条件下进行的。 27. The method of claim 25, wherein the precursor pulse input DMEAA reaction chamber is at a pressure of 30m torr conducted.
28. 权利要求l, 2, 3, 4或6的方法,其中脉冲输送含铪前体包括脉冲输送HfCl4前体入反应室而脉冲输送含铝前体包括将三甲基铝前体脉冲输入反应室。 L 28. claimed in claim 2, Method 3, 4 or 6, wherein pulsing a hafnium-containing precursor comprises pulsing body front HfCl4 pulsed into the reaction chamber and the aluminum-containing precursor comprises trimethylaluminum reaction precursor pulse input room.
29. 权利要求28的方法,其中在将三甲基铝前体脉冲输入反应室之后,接着用氩气吹洗反应室。 29. The method of claim 28, wherein after trimethyl aluminum precursor pulse input of the reaction chamber, and then purged with argon gas chamber.
30. 权利要求l, 2, 3, 4或6的方法,其中脉冲榆送含铪前体包括脉冲输送HfCl4前体入反应室和脉冲输送含铝前体包括将DMEAA 前体脉冲输入反应室。 L 30. claimed in claim 2, Method 3, 4 or 6, wherein the pulse elm hafnium-containing precursor delivery includes a front body pulsing HfCl4 pulsed into the reaction chamber and the aluminum-containing precursor comprises a precursor pulse input DMEAA reaction chamber.
31. 权利要求28的方法,其中在将HfCl4前体脉冲输入反应室之后,接着用纯净氮气吹洗反应室。 31. The method of claim 28, wherein after the pulse input HfCl4 precursor reaction chamber, followed by a nitrogen purge of the reaction chamber clean.
32. 权利要求30的方法,其中在将DMEAA前体脉冲输入反应室之后,接着用氢气吹洗反应室。 32. The method of claim 30, wherein after the pulse input DMEAA precursor reaction chamber, purged with hydrogen and then the reaction chamber.
33. —种用权利要求l, 2, 3, 4, 6, 18, 22, 25, 28或30的方法形成的电子器件。 33. - breeding claim l, 2, 3, 4, 6, 18, an electronic device 22. The method of 25, 28 or 30 is formed.
34. —种电子器件,它包含:至少一个晶体管,它具有位于第一和第二源/漏区之间的主体区, 在主体区上的介质薄膜,和与该介质薄膜相耦合的栅; 其特征在于介质薄膜含有原子层沉积型HfA103。 34. - of electronic devices, comprising: at least one transistor having a body region located between the first and second source / drain regions, a dielectric film on the body region, and coupled with the gate dielectric film; wherein the dielectric film comprises atomic layer deposition type HfA103.
35. 权利要求34的电子器件,其中这电子器件是存储器。 35. The electronic device of claim 34, wherein the electronic device which is a memory.
36. 权利要求35的电子器件,其中这存储器包括: 若干个存取晶体管;若干条字线,它们与存取晶体管数目相同的若干个栅相耦合; 若干条源线,它们与存取晶体管数目相同的若干个第一源/漏区相耦合;若干条位线,它们与存取晶体管数目相同的若干个第二源/漏区相耦合。 The number of access transistors are a plurality of source lines; a plurality of access transistors; a plurality of word lines, the same number they access transistors coupled to a plurality of gate: 36. The electronic device of claim 35, wherein it comprises a memory the same number of the first source / drain region coupled; a plurality of bit lines, the number of access transistor are the same number of second source / drain region coupled.
37. 权利要求34的电子器件,其中这电子器件是具有与存储器相耦合的处理机的电子系统。 37. The electronic device of claim 34, wherein the electronic device is an electronic system that has a memory coupled to the processor.
38. 权利要求34, 35或37的电子器件,其中介质薄膜包括A1203 和Hf02。 34, 35 or 38. The electronic device of claim 37, wherein the dielectric film comprises A1203 and Hf02.
39. 权利要求34, 35或37的电子器件,其中介质薄膜基本上是非晶形的。 34, 35 or 39. The electronic device of claim 37, wherein the dielectric film is substantially amorphous.
40. 权利要求34, 35或37的电子器件,其中介质薄膜具有的介电常数为9~25。 34, 35 or 40. The electronic device of claim 37, wherein the dielectric film having a dielectric constant of 9 to 25.
41. 权利要求34, 35或37的电子器件,其中介质薄膜具有的等效氧化物厚度(teq)为3埃-12埃。 34, 35 or 41. The electronic device of claim 37, wherein the dielectric film having an equivalent oxide thickness (teq) of 3 -12 .
42. 权利要求34, 35或37的电子器件,其中介质薄膜具有的等效氧化物厚度(teq)小于3埃。 34, 35 or 42. The electronic device of claim 37, wherein the dielectric film having an equivalent oxide thickness (teq) of less than 3 Angstroms.
Description  translated from Chinese

氧化铪铝介质薄膜 Hafnium oxide dielectric thin film of aluminum

相关申请 RELATED APPLICATIONS

本申请与以下的,共同未决的,共同转让的申请有关,这些有关 This application is related to the following co-pending and common application for the transfer of relevant, those concerned

申请在此引入作参考: Hereby incorporated by reference:

美国申请号10/137499,代理巻号1303.050US1标题:'6用作栅介质的原子层沉积LaAK)3薄膜", US Application No. 10/137499, agent number Volume 1303.050US1 title: '6 is used as the gate dielectric ALD LaAK) 3 film "

美国申请号10/137058,代理巻号303.802 US1标题:"原子层沉积和转化", US Application No. 10/137058, Acting Volume No. 303.802 US1 headline: "atomic layer deposition and transformation",

美国申请号10/137168,代理巻号1303.048US1标题:"利用ULSI 栅原子层沉积法形成的,用作栅介质层的AIOx原子层"和 US Application No. 10/137168, Acting Volume No. 1303.048US1 headline: "ULSI gate formed by atomic layer deposition method, used as the gate dielectric layer AIOx atomic layer" and

美国申请号09/797324,代理巻号303.717 US1标题:"均匀化学气相沉积法所采用的方法,系统,和设备"。 US Application No. 09/797324, Acting Volume No. 303.717 US1 title: "Uniform chemical vapor deposition method used, systems, and equipment."

发明领域 Field of the Invention

本发明涉及半导体器件和器件的制作。 The present invention relates to semiconductor devices and device fabrication. 特别是,本发明涉及晶体管器件的栅介质层和它们的制作方法。 In particular, the present invention relates to a gate dielectric layer transistor devices and their production methods.

发明背景 Background of the Invention

半导体器件制造业有着驱使其需要改善速率性能,改善其低静态(静止态)功率要求和适应对硅基微电子产品的各式各样的电源要求及输出电压要求等方面的市场需求。 Semiconductor manufacturing industry has driven the need to improve its rate performance, improve its low quiescent (resting state) power requirements and meet the market demand for silicon-based microelectronic products of all kinds of power requirements and output voltage requirements and so on. 尤其是在晶体管制作中,有着面临要求减小器件例如晶体管尺寸的持续压力。 Especially in transistor production, it has faced continued pressure required to reduce the size of devices such as transistors. 最终的目的是制作出越来越小的和更可靠的集成电路(IC)供在例如信息处理机芯片,移动电话机或存储器例如DRAM等产品中使用。 The ultimate goal is to produce ever smaller and more reliable integrated circuit (IC) for use in the information processor chip, for example, a mobile phone or a memory such as DRAM and other products. 较小的器件经常是由蓄电池供电,故也面临要求减小蓄电池尺寸和延长电池充电之间的时间的压力的处境。 Smaller devices are often powered by the battery, it is also faced with requirements to reduce the battery size and extend the time between battery charging pressure of the situation. 这促使工业界不仅要设计更小的晶体管而且要将它们设计成能在较低的电源下可靠工作。 This prompted the industry not only to design smaller transistors and which are designed to work reliably in low supply.

目前,半导体工业有赖于减小或按比例缩小基本器件,主要是硅基金属氧化物半导体场效应晶体管(MOSFET),的尺寸的能力。 Currently, the semiconductor industry relies substantially reduced or scaled devices, primarily the ability of the silicon metal-oxide semiconductor field effect transistor (MOSFET), size. 这一类晶体管的常见构型示于图1。 Frequently this type of transistor configuration shown in Fig. 虽然以下的讨论应用了图l来阐明利 Although the following discussion to clarify the application of the Figure l Lee

6用现有技术制造的晶体管,但本领域的每一位技术人员都承认可以将本发明引入图1所示晶体管中,以制成与本发明相应的新型晶体管。 6 transistors fabricated by the prior art, but every skill in the art will recognize the present invention may be introduced into the transistor shown in Figure 1, the present invention is to produce a corresponding new transistors.

晶体管100用通常为硅的衬底110制成,但也可以用其它的半导体材料制成。 Transistor 100 is generally made of a silicon substrate 110, but may also be made of other semiconductor materials. 晶体管100具有第一源极/漏极区120和第二源极/漏极区130。 Transistor 100 has a first source / drain region 120 and the second source / drain region 130. 主体区132位于第一源极/漏极区和第二源极/漏极区之间,此处的主体区132定义了具有沟道长度134的晶体管沟道。 Body region 132 located between the first source / drain region and a second source / drain region between the body region 132 here defines a channel having a channel length of the transistor 134. 栅介质,或栅氧化物140位于主体区132内,而栅150位于栅介质的上方。 Gate dielectric, or gate oxide 140 is located within the body region 132, and gate 150 located above the gate dielectric. 虽然栅介质可以是由氧化物之外的材料形成,但栅介质通常是氧化物,并常称为栅氧化物。 Although gate dielectric may be formed of a material other than an oxide, it is usually an oxide gate dielectric, and is often referred to as a gate oxide. 栅可以用多晶硅制成,或用其它导电材料制成例如可以使用金 Polysilicon gate can be made, or made of other conductive material such as gold

为了制造尺寸更小的和能在较低电源下可靠地工作的晶体管,一个重要的设计标准是栅介质140。 In order to produce a smaller size and can operate reliably at lower power supply transistor, an important design criterion is the gate dielectric 140. 形成栅介质的主角是二氧化硅Si02. 热生长非晶形Si02层是一种电和热力稳定材料,在Si02层与底层Si 的界面处形成了高质量的界面以及上佳的电绝缘性能。 Protagonist forming a gate dielectric is silicon dioxide Si02. Thermally grown amorphous Si02 layer is an electrical and heat stable material at the interface with the underlying Si Si02 layer forms a high-quality interface and excellent electrical insulating properties. 在典型的加工过程中,在Si上使用Si02会造成缺陷电荷密度,其量级为10lfl/cm2, 中间带隙界面态密度约为101(Vcm2eV,和击穿电压在15 MV/cm范围内。就这样的质量而言,没有明显看出需要使用除Si02之外的材料, 但是栅介质的定标的提高和其它要求会产生需要寻找用作栅介质的其它介质材料。 In a typical process, the use of the Si Si02 defect can cause the charge density on the order of 10lfl / cm2, the intermediate band-gap interface state density is about 101 (Vcm2eV, and breakdown voltage in 15 MV / cm range. So the quality is concerned, there is no apparent need to use materials other than Si02, but scaled gate dielectric enhancement and other requirements will have a need to find other medium is used as the gate dielectric material.

所需要的是这样一种替代介质材料,它可用来形成具有较之Si02 有高介电常数的栅介质和相对于硅是热力稳定的,以致在硅层上形成 What is needed is such an alternative dielectric material, which may be used to form a high dielectric constant than Si02 gate dielectric and phase so as to form a silicon layer on the silicon is heat stable,

介质时不会导致有Si02形成或使来自底层硅层的材料例如掺杂剂扩散 It does not result in the formation of the medium or the material has Si02 underlying silicon layer, for example, from dopant diffusion

到栅介质中。 The gate dielectric. 发明概述 Summary of the Invention

在本发明所讲授的实施方案中论述了解决以上所迷问题的方法。 Taught in the present invention embodiments discussed a solution to the above problem of fans. 在一种实施方案中, 一种在晶体管主体区上形成栅介质的方法包括在晶体管主体区上进行舍HfA103非晶形薄膜的原子层沉积(ALD)。 Methods In one embodiment, a method of forming a gate dielectric of the transistor body region including homes HfA103 amorphous thin films atomic layer deposition (ALD) in the transistor body region. 形成HfA103薄膜所采用的ALD方法是将含铪前体脉冲输入装有衬底的反应室,将第一含氧前体脉冲输入反应室,将含铝前体脉冲输入反应室,最后将第二含氧前体脉冲输入反应室。 ALD method for forming a thin film HfA103 employed is hafnium-containing precursors reaction chamber containing a substrate of the input pulse, the first pulse input oxygen-containing precursor the reaction chamber, the aluminum-containing precursor pulse input chamber, and finally the second oxygen-containing precursor pulse input reaction chamber. 每种前体根据所选定的时间周期被脉冲输入反应室。 Each precursor according to the selected time period is the pulse input of the reaction chamber. 脉冲输送每种前体所用时间的长短根据所采用的前体选定。 Pulsing each precursor used in accordance with the length of time the precursor used is selected. 在每次脉冲输送前体之间将剩余的前体和反应的副 Deputy before each pulsing between the body and the remaining precursors and reaction

产物从反应室中除去。 The product was removed from the reaction chamber. HfAi03薄膜的厚度通过重复进行脉冲输送含铪前体,第一含氧前体,含铝前体和第二含氧前体的循环次数来控制, 直至形成要求的厚度。 HfAi03 film thickness by repeating the thickness of the front pulsing a hafnium-containing precursor, the first oxygen-containing body, the number of cycles a second oxygen-containing aluminum precursor and a precursor to control, until a requirement.

有利之处是,由HfA103薄膜形成的栅介质具有比二氧化硅要大的介电常数,相对地小的漏电电流和对硅基衬底有良好的稳定性。 Advantageous, the gate dielectric film formed by the HfA103 larger than the silicon dioxide dielectric constant, relatively small leakage current and the silicon substrate have good stability. 本发 The hair

明所讲授的各种实施方案包含形成各种晶体管,存储器,和具有含HfA103的介质层的电子系统。 The invention comprises various embodiments taught various transistors are formed, a memory, and electronic systems with dielectric layers containing the HfA103.

其它实施方案包括适用于晶体管,存储器,和具有HfAK)3薄膜的介质栅的电子系统的各种结构。 Other embodiments include structure for a variety of transistors, memory, and have HfAK) 3 gate dielectric film of an electronic system. 与具有同样实体厚度的氧化硅栅相比,这类介质栅具有显著地薄的等效氧化物厚度。 Compared with silicon oxide having the same physical thickness of the gate, the gate dielectric having such significantly thinner equivalent oxide thickness. 另一方面,这类介质栅较之具有同样等效氧化物厚度的氧化硅栅具有显著地厚的实体厚度。 On the other hand, compared with the same kind of gate dielectric equivalent oxide thickness of the gate with a solid silicon oxide thickness significantly thicker.

本发明的这些和其它的实施方案,见解,优点和特点部分地陈述于随后的叙述中,和对于本领域的那些技术人员来说,部分地通过参阅下述本发明的叙述和参阅附图或通过本发明的实践而变得显而易见了。 The present invention These and other embodiments, opinion, features and advantages set forth in part in the ensuing narrative, and for those skilled in the art that, in part, by reference to the following description and to the drawings of the invention or by practice of the invention will become apparent. 本发明的这些见解,优点和特点借助于尤其是在后面所附的权利要求书中所指出的装置,程序和组合得以实现和达到。 These insights of the present invention, the advantages and features of the aid, especially in the back of the book pointed out in the appended claims, means, procedures, and combinations can be realized and attained.

附图简述 BRIEF DESCRIPTION

图l描绘了晶体管的常见构型。 Figure l depicts a common configuration transistors.

图2A描绘了一种本发明所讲授的加工HfA103薄膜用的原子层沉积系统的实施方案。 2A depicts an embodiment of the present invention is a process as taught HfA103 films atomic layer deposition system.

图2B描绘了一种本发明所讲授的加工HfAK)3薄膜用的原子层沉 2B depicts the present invention teaches a method of processing HfAK) atomic layer 3 film with

积室的气体分配装置的实施方案。 It means the product of embodiments of the gas distribution chamber.

图3说明了一种本发明所讲授的HfA103薄膜加工方法的实施方案 Figure 3 illustrates an embodiment of the present invention teaches a film processing method HfA103

所采用的单元工艺流程图。 Unit process flow diagram used.

图4描绘了一种本发明所讲授的可以用来制作一种晶体管构型的实施方案。 Figure 4 depicts a teaching of the present invention can be used to produce an embodiment of the transistor configuration.

图5说明了引入本发明所讲授的器件的个人用计算机的实施方案的透视困。 Figure 5 illustrates a perspective sleepy incorporated herein taught personal computer device embodiments.

图6说明了引入本发明所讲授的器件的中央处理机的实施方案的示意固。 Figure 6 illustrates a schematic of the present invention teaches a solid introduction of a device central processing embodiment.

图7说明了本发明所讲授的DRAM存储器的实施方案的示意图。 Figure 7 illustrates a schematic diagram of the present invention are taught in an embodiment of DRAM memory. 优选实施方案详述 Detailed Description of the preferred embodiments

在本发明的以下详述中,参照了形成详述一部分的附图,并为了说明,这些附图显示了可以实施本发明的具体的实施方案。 In the following detailed description of the present invention, described in detail with reference to the drawings which form a part of, and to explain, these figures show the embodiment of the present invention may be specific embodiments. 对这些实施方案所作的详细陈述,足以使本领域的那些技术人员能够实施本明。 Detailed statement made to these embodiments, enough so that those skilled in the art to practice the invention. 可以应用其它的实施方案并可在不超越本发明的范围的情况下进行结构,逻辑和电学的更改。 It can be applied to other embodiments and can be changed structure, logic and electricity does not exceed in the case of the scope of the invention.

在以下叙述中使用的术语晶片和衬底包括任何具有外露面的结构,以便利用外露面形成本发明的集成电路(IC)结构。 Terms wafer and substrate used in the following description include any structure having an outer appearance in order to take advantage of external appearance form an integrated circuit (IC) structure of the present invention. 术语衬底应理解成包括半导体晶片。 The term substrate is understood to include semiconductor wafers. 术语衬底也用来指加工过程中的半导体结构,并可以包括在其上已制成的其它层-晶片和衬底二者均包括掺杂和非掺杂的半导体,由基底半导体或绝缘体支承的外延半导体层,以及本领域的技术人员熟知的其它半导体结构。 The term substrate is also used to refer to semiconductor structures during processing, and may include other layers thereon have been made - both the wafer and substrate include doped and undoped semiconductors, supported by a base semiconductor or insulator epitaxial semiconductor layer, and well known to those skilled in the art of other semiconductor structures. 术语导体应理解成包括半导体,而术语绝缘体或介质被定义为包括导电性比称为导体的材料要低些的任何材料。 The term conductor is understood to include semiconductors, and the term insulator or dielectric is defined to include a conductive material than the known conductor of any material are lower.

本申请中所采用的术语"水平"被定义为平行于晶片或衬底的普通的平面或表面,与晶片或衬底的取向无关。 Terminology used in this application, "horizontal" is defined as parallel to a wafer or substrate plane or surface normal, regardless of the orientation of the wafer or substrate. 术语"垂直"指的是其方向与上面所定义的水平相垂直。 The term "vertical" refers to a direction horizontal perpendicular defined above. 以位于晶片或衬底的上表面上的普通平面或表面为基准来定义表示位置的介词,例如"在上面",《側面"(如在側壁上),"高于","低于","在上方,,和"在下面", 与晶片或衬底的取向无关。 Ordinary plane or surface located on the upper surface of the wafer or substrate as a benchmark to define the preposition indicates the position, such as "above", "side" (as on the sidewall), "above", "less than" "In the above ,, and" below ", regardless of the orientation of the wafer or substrate. 所以,以下的详述并不作出限制的含义, 而本发明的范闺仅由附于后面的权利要求书,以及与权利要求书所给予的范围等同的全范围来定义。 Therefore, the following detailed description is not to limit the meaning and scope of the present invention is limited only by the boudoir rights attached to the back of the claims, as well as to define the scope given the full range of equivalents of the claims.

图l的栅介质HO,当其运行于晶体管中时,既有实体栅介质厚度又有等效氧化物厚度(teq),等效氧化物厚度量化了以典型的实体厚 Figure l of the gate dielectric HO, when it is run on transistors, there are both physical gate dielectric thickness equivalent oxide thickness (teq), equivalent oxide thickness quantifies the thickness of a typical entity

度表示的栅介质140的电气性能例如电容。 Gate dielectric 140 degrees in electrical properties such as capacitance. t叫被定义为要求其具有和已知介质同样的电容密度的一种理论上的SK)2层的厚度,而不考虑漏 t call is defined as required to have the same kind of media and known theoretical capacitance density of the SK) 2 layer thickness, regardless of the drain

电电流和可靠性这些方面的问题。 Electric current and reliability issues in these areas.

沉积在Si表面上作为栅介质的厚度t的Si02层还将有一个大于它 Si deposited on the surface as a gate dielectric thickness t of Si02 layer will have a greater than it

的厚度t的teq。 The thickness t of teq. 这t叫是由在其上沉积了SK)2的表面沟道内的电容引起 This call is t) within the capacitor surface channel 2 is caused by depositing the SK

9的,这要归因于耗尽/反型区的形成,。 9 This is due to the depletion formation / inversion region. 这耗尽/反型区可导致使teq比 This depletion / inversion region may lead to more than make teq

Si02层的厚度t大3〜6埃(A)。 Si02 layer thickness t big 3 ~ 6 angstroms (A). 于是,总有一天,在半导体工业驱使将栅介质等效氧化物厚度按比例缩小到低于10A的情况下,用作栅介质的SiCh层的实体厚度要求大概必须是大约4~7A。 Then, one day, in the semiconductor industry, driven by the gate dielectric equivalent oxide thickness is scaled down to less than 10A of the case, the entity thickness SiCh layer used as the gate dielectric requirement probably must be about 4 ~ 7A.

对于Si02的额外要求取决于和Si02栅介质一起使用的栅电极。 For additional requirements Si02 Si02 depends on the gate electrode and gate dielectric used together. 使 Make

用常规的多晶硅栅会导致Si。 Conventional polysilicon gate will cause Si. 2层的teq额外增加。 Increase teq additional 2 layers. 这额外增加的厚度可 This additional thickness may be

通过采用金属栅电极而消除,可是,金属栅目前尚未用于互补金属氧 By using a metal gate electrode to eliminate, however, it has not yet been used for metal gate complementary metal oxide

化物半导体场效应晶体管(CMOS)工艺中。 Compound semiconductor field effect transistor (CMOS) process. 因此,未来的器件将被设计为Si02栅介质层的实体厚度约5A或更小。 Therefore, future devices will be designed to Si02 gate dielectric layer entity thickness of about 5A or less. 对Si02氧化层如此小 Si02 oxide layer on such a small

的厚度要求引起了额外的一些问题。 The thickness requirements cause additional problems.

二氧化硅用作栅介质,部分地是由于它在SiOrSi基结构中的电绝缘性能。 Silica is used as the gate dielectric, in part due to its electrical insulation properties in SiOrSi base structure. 这种电绝缘是由于Si02的相对大的带隙(8.9eV)使它成为一种没有导电性的好的绝缘体。 This is due to the electrically insulating Si02 relatively large band gap (8.9eV) makes it a good insulator no conductivity. 显著减小它的带隙会排除它作为一种栅介质的材料。 Significantly reduced its bandgap material would exclude it as a gate dielectric. 当Si02层的厚度降低时,在这厚度内的原子层层数或这种材料的单层层数将下降。 When reducing the thickness of the Si02 layer, the number of atomic layers or a single layer of such material within this thickness decreases. 在一定的厚度下,单层层数将少到足以使Si02层不能象在较厚的或整体层中那样具有完整的原子排列。 Under certain thickness, the single small enough so that the number of layers Si02 layer like that can not be arranged in a complete atomic layer thick or whole. 较之整体结构而言,不完全构造的结果是,只有一层或二层单层的薄Si02层将不能形成全带隙。 Compared with the overall structure, the results are not fully constructed, only one or two layers of thin single Si02 layer will not be able to form a full band gap. 在SK)2栅介质中不是全带隙会在底层Si沟道和上层多晶硅栅之间造成有效短路。 In SK) 2 gate dielectric is not fully effective band gap can cause a short circuit between the ground floor and the upper Si channel polysilicon gate. 这不良特性对可以按比例缩小的Si02 层的实体厚度规定了限制值。 This undesirable characteristics can be scaled down to a thickness of Si02 layer entity specified limit. 由于这单层效应,这最小厚度被认为是约7-8A。 Since this single effect, which is considered the minimum thickness of about 7-8A. 所以,对于要求teq小于约IOA的未来的器件来说,必需考虑除Si02以外别的介质用作栅介质。 Therefore, the requirements for teq less than about IOA of future devices, it is necessary to consider other media as the gate dielectric in addition to Si02.

对于用作栅介质的典型介质层,其电容根据适用于平行板电容的公式确定:C=K€。 For a typical dielectric layer used as the gate dielectric, the capacitance of the parallel plate capacitor according to the applicable formula to determine: C = K €. A/t,式中K是介电常数,€。 A / t, where K is the dielectric constant, €. 是自由空间的电容率, A是电容器的面积,和t是这介质的厚度。 Is the permittivity of free space, A is the area of the capacitor, and t is the thickness of that medium. 对于给定电容的将SiCh的 For a given capacitor of the SiCh

介电常数,K。 Dielectric constant, K. x=3.9,与teq结合的某种材料的厚度t与teq的关系如下 x = 3.9, the relationship between teq bonded with a material thickness t teq following

t= ( K/Kox) teq= ( K/3.9) teq t = (K / Kox) teq = (K / 3.9) teq

于是,介电常数大于SK)2的介电常数3.9的材料,^具有的实体 Thus, the dielectric constant greater than SK) material dielectric constant of 3.9 2 ^ entity has

厚度,当提供了所要求的等效氧化物厚度时,将显著地大于所要求的 Thickness, while providing an equivalent oxide thickness required, it will be significantly greater than the required

teq。 teq. 例如,具有介电常数10的替代介质材料可以具有约25."的厚度,便可使teq为10A,不计及任何耗尽/反型层效应。于是,通过采用具有介电常数高于Si02的介质材料就能实现降低晶体管的等效氧化物厚度。 For example, a substitute dielectric constant of the dielectric material 10 may have about 25. "thickness, can make teq to 10A, without taking into account any depletion / inversion layer effects. Thus, by the use of having a dielectric constant higher than that of Si02 dielectric materials can achieve lower transistor equivalent oxide thickness.

为了获得较低的晶体管工作电压和较小的晶体管尺寸而所需的较薄的等效氧化物厚度可以利用很多种材料来实现,但额外的制作要求使确定替代Si02的合适的置换材料变得困难了。 In order to achieve a lower operating voltage and smaller transistor size of transistors required thinner equivalent oxide thickness can be used to implement a wide variety of materials, but the extra production requirements make identification of alternative Si02 suitable replacement material becomes difficult. 微电子工业目前的观点仍然是赞成Si基器件。 The current view of the microelectronics industry is still in favor of Si-based devices. 这就要求采用的栅介质要能生长在硅衬底或硅层上,而这就对取代的介质材料设置了大量的限制。 This requires the use of the gate dielectric can be grown on a silicon substrate or silicon layer, and this set of substituted dielectric material a lot of restrictions. 介质在硅层上 Media on the silicon layer

形成的过程中,除了所要求的介质之外,还存在有可能形成一小层Si02 Formed in the process, in addition to the desired medium, there are likely to form a small layer of Si02

的可能性。 Possibilities. 结果实际上是一种由二层彼此平行的子层组成的介质层和在其上形成该介质的硅层。 It is actually a result of the dielectric layer parallel to each other two layers composed of sub-layers forming the dielectric and the silicon layer thereon. 在这种情况下,最终的电容是二个串联介 In this case, the final two series capacitors are mediated

质的电容。 Quality capacitors. 因此,介质层的teq是SK)2层的厚度与所形成的介质的厚度乘以系数之和,写成 Therefore, teq dielectric layer is SK) thickness by a factor of 2 layer thickness and the formation of the media and, written in

teq=t SH32+ ( Kox/K ) t teq = t SH32 + (Kox / K) t

因此,如果在此过程中形成了SiOz层,那么t叫再次受Si02层的限制。 Thus, if an SiOz layer is formed in the process, then t is called again by limiting Si02 layer. 即使是在硅层和要求的介质之间有防止Si02层形成的阻挡层, t叫仍会受具有最小介电常数的那层的限制。 Even between the silicon layer and the requirements of the media has a barrier layer to prevent the formation of Si02, t called restricted that layer will have a minimum dielectric constant. 可是,不管是采用了具有高介电常数的单层介质层还是采用了介电常数比SiC)2高的阻挡层,与硅层面接的层必须具有高质量的界面,以保持高的沟道载流子迁移率。 However, whether using a single dielectric layer having a high dielectric constant or permittivity than using SiC) 2 high barrier, level into contact with the silicon layer must have a high quality interface to maintain a high channel carrier mobilities.

GDWilk等人的聂新一篇论文发表在应用物理杂志第的巻10期第5243-5275页(2001)上,该论文讨论了用作栅介质的高介质材料 Nie et al GDWilk new paper published in the Journal of Applied Physics section of Volume 10 page section 5243-5275 (2001), the paper discusses the use as a high-dielectric gate dielectric material

的材料性能。 The material properties. 公开的资料之一是Al203作为Si02的置换材料的适用性。 One of the applicability of public information is as Si02 Al203 replacement material.

公开的Al2Cb具有用作栅介质的良好的性能,例如大带隙,直至高温在Si上仍具有热力稳定性,和非晶形结构。 Disclosed Al2Cb used as the gate dielectric having good properties, such as large band gap, until temperature on Si still has thermal stability, and amorphous structures. 此外,Wilk公开了在硅上形成Ah03层不会导致出现Si02界面层。 In addition, Wilk discloses Ah03 layer is formed on the silicon does not cause Si02 interface layer appears. 可是,Al203的介电常数仅为9, 其一些薄层可能具有的介电常数为约8~约10。 However, only 9 of the dielectric constant of Al203, some of which may have a thin layer of a dielectric constant of from about 8 to about 10. 虽然入1203介电常数比SK)2有改进,但仍希望栅介质采用更高的介电常数。 Although the 1203 constant than SK) 2 has improved, but still want to use a higher dielectric constant gate dielectric. Wilk所论及的其它介质及其性能如下材料 介电常数(K) 带隙Eg (Ev) 晶体结构 Wilk are addressed and other media properties as dielectric constant (K) band gap Eg (Ev) crystal structure

Si02 3.9 8.9 非晶 Amorphous Si02 3.9 8.9

Si3N4 7 5.1 非晶 Amorphous Si3N4 7 5.1

A1203 9 8,7 非晶 A1203 9 8,7 Amorphous

Y203 15 5,6 立方 Y203 15 5,6 cubic

La203 30 4,3 六方,立方 La203 30 4,3 of hexagonal, cubic

Ta2Os 26 (5 斜方 Ta2Os 26 (5 ramps

Ti02 80 3.5 四方(金红石,锐钬矿) Ti02 80 3.5 tetragonal (rutile, anatase holmium mine)

25 5.7 单斜,四方,立方 25 5.7 monoclinic, tetragonal, cubic

Zr02 25 7.8 单斜,四方,立方 Zr02 25 7.8 monoclinic, tetragonal, cubic

使用Si()2作为栅介质的优点之一是形成的Si02层是一种非晶形的栅介质。 One advantage of using Si 2 as the gate dielectric () is an amorphous Si02 layer is formed on the gate dielectric. 栅介质具有非晶形结构是有利的,因为在多晶形栅介质中的晶界提供高的漏电路径。 Gate dielectric having an amorphous structure is advantageous because polymorphs gate dielectric with high grain boundary leakage paths. 另外,在整个多晶形栅介质中晶粒尺寸和取向的变化可能引起该薄膜的介电常数发生变化。 Further, the entire gate dielectric polymorphs grain size and orientation changes may cause changes in the dielectric constant of the film. 上述材料的性能包括结构都是针对呈整体状态的材料的。 Material properties of such materials include structures are present for the whole state of. 具有介电常数高于SK)2这一优点的材料也有呈结晶形态,至少呈整体构型这一缺点。 Having a dielectric constant higher than SK) 2 material also has the advantage in crystalline form, at least this shortcoming was the overall configuration. 用来替代SK)2作为栅介质的最佳选择材料是具有高介电常数的,能将它们制作成具有非晶形状态的薄层的那些材料。 Used to replace SK) 2 as the best choice of the gate dielectric material having a high dielectric constant, that they can be made into a thin layer of material having the amorphous state.

在共同未决的,共同转让的美国专利申请:标题为"用作栅介质的原子层沉积LaAL03薄膜"代理巻号1303050 US1,序列号10/137499 中公开了LaALO;j作为Si02的替换材料,在电子器件例如MOS晶体管中用来形成栅介质和其它介质薄膜。 In the co-pending, commonly assigned U.S. patent application: the title is "used as the gate dielectric thin films atomic layer deposition LaAL03" Proxy Volume No. 1303050 US1, serial number 10/137499 discloses LaALO; j as Si02 replacement materials, such as MOS transistors are used to form the gate dielectric film, and other media in an electronic device. 这份申请公开了,其中包括, 应用原子层沉积法利用含镧源和含铝源在硅上形成LaAL03层。 This application discloses, including, atomic layer deposition method using lanthanum source and aluminum-containing source LaAL03 layer is formed on the silicon. 控制镧顺序沉积和铝顺序沉积便可形成这样一种栅介质,它是一种具有预定介电常数的组合物。 Lanthanum and aluminum deposition control sequence can be sequentially deposited to form such a gate dielectric, which is a composition having a predetermined dielectric constant.

在本发明所讲授的某一种实施方案中,利用原子层沉积(ALD) 法,也称为原子层外延(ALE)法,使HfA103层沉积在硅上。 In a particular embodiment of the invention taught, using atomic layer deposition (ALD) method, also known as atomic layer epitaxy (ALE) method, so HfA103 layer is deposited on silicon. ALD 作为化学气相沉积(CVD)的一种改进是在20世纪70年代初期开发出来的,所以也叫"交替脉冲型CVD"。 ALD as a chemical vapor deposition (CVD) is an improvement in the early 1970s developed, it is also called "alternate pulsed CVD". 在ALD中,将各种气体前体 In ALD, the body before various gases

12每次一种引导到放置在反应室(或反应釜)中的衬底表面上。 Each time a boot 12 onto the surface of the substrate placed in the reaction chamber (or reactor) in. 这些气体前体的引进采用脉冲输送每种气体前体的方式。 These precursor gases introduced by way of the gas before pulsing each body. 在各个脉冲之间用情性气体吹洗反应室或抽空反应室。 Between each pulse and soul of the gas purge reaction chamber or evacuation of the reaction chamber. 在第一个脉沖相中,在前体饱和地化学吸附在衬底表面的情况下,与衬底的化学反应发生了。 In the first phase of a pulse, the precursor chemical in the case of the saturated adsorbed substrate surface, chemical reaction with the substrate occurs. 随后利用惰性气体吹洗清除反应室中剩余前体。 Then purged with an inert gas purge reaction chamber before the remaining body.

第二脉冲相将另一种前体引至衬底上,在此发生所要求的薄膜的生长反应。 The second pulse phase will lead to another precursor on the substrate, this growth response occurs in the film claims. 在薄膜生长反应之后,从反应室中清除反应的副产物和剩余前体。 After the film growth reaction, remove from the reaction chamber and the remaining by-product precursors. 在正确设计的流动式反应室内,凭借良好的前体化学性质, 这些前体在衬底上积极地吸附和彼此发生反应,能在小于1秒钟的时 When properly designed flow type reaction chamber, with a good precursor chemical nature, these precursors actively adsorb and react with each other on the substrate can be less than 1 second

间内进行一次ALD循环。 Once inside the room ALD cycle. 典型地,前体的脉冲输送时间范围从约0.5 秒到约2至3秒。 Typically, precursor pulsing time ranges from about 0.5 seconds to about 2 to 3 seconds.

在ALD中,有利之处是所有反应和净化阶段处于饱和状态使生长受到自身限制。 In ALD, the advantageous of all reaction and purification stage is saturated so that growth is self-limiting. 这种自身限制式生长导致大面积的均匀性和共形性, 这对于诸如平板衬底,深沟槽这类情况,并在多孔硅,和高表面面积的二氧化硅以及氧化铝粉末的加工中有着重要的应用价值。 This self-limiting growth results in a large area of formula uniformity and conformality, such that the flat substrate, the deep trench such cases, and in the processing of porous silicon and high surface area silica and alumina powders It has an important application value. 有意义的是,ALD提供了通过控制生长循环次数来控制薄膜厚度的一种直截了 Significantly, ALD provides by controlling the growth cycles to control the film thickness of a straightforward

当的简单的方法。 When the easy way.

最初,开发ALD是为了制造场致发光显示器中所需的发光薄膜和介质薄膜。 Originally developed in order to produce ALD is a thin film electroluminescent light emitting display and a dielectric film required. 经多方努力已将ALD应用于掺杂硫化锌和碱土金属硫化物的薄膜的生长。 The various efforts have been applied to doping ALD growth of zinc sulfide and alkaline earth metal sulfide films. 另外,已研究出将ALD应用于各种各样的外延nV和n-VI薄膜的生长,非外延的结晶或非晶形的氧化物和氮化物薄膜的生长,和这些薄膜的多层结构的形成。 Additionally, ALD has been developed to be applied to a variety of growth nV and n-VI epitaxial films, grown crystalline or amorphous oxide and nitride films of non-epitaxial, and forming a multilayer structure of these films . 还有值得感兴趣的是关于硅和锗薄膜的ALD生长,但是由于困难的前体化学,故这一努力不十分成功。 Also worthy of interest is about the ALD growth of silicon and germanium films, but because of the difficulties of precursor chemicals, it is not very successful in this endeavor.

这些前体可以是气体,液体或固体。 These precursors can be a gas, liquid or solid. 但是,液体或固体前体必须 However, liquid or solid precursor must

是易发挥的。 It is easy to play. 蒸气压力必须足够高以便能有效地输送质量。 Vapor pressure must be high enough to be able to efficiently deliver quality. 还有,固体前体和某些液体前体必需在反应室内加以加热并通过受热式管路将 Also, the solid precursor and some liquid precursors required to be heated in a reaction chamber and through the heat pipe line will

其引至衬底上。 Which lead to the substrate. 必需的蒸气压力务必在低于衬底温度的温度下达到, 以避免前体凝结在衬底上。 Always vapor pressure at a temperature below the required temperature of the substrate temperature is reached, to avoid precursor condensation on the substrate. 由于ALD的这种自身限制生长机理,对固体前体可以采用比较低的蒸气压力,虽然在此过程中由于它们的表面面积改变,蒸发速度可能有点变化。 Because of this self-limiting ALD growth mechanism, solid precursor may be employed for a relatively low vapor pressure, though in the process because of their surface area change, the evaporation rate may change somewhat.

对用于ALD的前体有一些其它要求。 Precursors for ALD has some other requirements. 这类前体在衬底温度下必须 Such precursors must at a substrate temperature

是热稳定的,因为它们的分解会破坏表面控制,并从而破坏了基于前体在衬底表面上形成反应物的ALD方法的优点。 It is thermally stable, because they will damage the surface decomposition control, and thus undermine the advantages of ALD method based reactant precursor formed on the substrate surface. 当然,如果这种分解与ALD生长相比是緩慢的,则少量分解是可以允许的。 Of course, if such decomposition is slow compared with the ALD growth, the small amount of decomposition can be tolerated.

前体应该化学吸附在衬底表面上或与表面起化学反应,虽然前体和表面之间相互作用以及吸附的机理对于不同的前体是不同的。 Chemical precursors should be adsorbed on the substrate surface or chemically react with the surface, although the mechanism of interaction between the precursor and the surface and adsorption for different precursors are different. 衬底表面上的分子必须积极地与第二前体发生反应以便形成要求的固体薄膜。 Molecules on the substrate surface must react aggressively with the second precursor to form a solid film occurred required. 另外,前体不应该与薄膜发生反应而引起浸蚀,和前体不应该溶于薄膜中,在ALD中使用高活性前体与常规CVD的前体选用形成了对比。 In addition, the precursors should not react with the film caused by etching, and precursors should not be dissolved in the film, the use of a high activity conventional CVD precursors in ALD precursor chosen contrasts.

在本反应中的副产物必须是气体,以便很容易地将其从反应室中排出,再者,这副产物不应该发生反应或吸附在表面上。 In this reaction byproducts must be a gas, in order to be easily discharged from the reaction chamber which, furthermore, this pair of products should not react or adsorbed on the surface.

在一种实施方案中,采用以下程序使HfA103薄膜形成在放置于反应室内的衬底上,即将含铪前体脉冲输入反应室,随后脉冲输入第一含氧前体,然后将含铝前体脉冲输入反应室,接着将第二含氧前体脉冲输入反应室。 In one embodiment, the following program causes HfA103 film is formed on the substrate placed in the reaction chamber, i.e. hafnium-containing precursor pulses fed to the reaction chamber, followed by a first oxygen-containing precursor pulse input, and then the aluminum-containing substance before pulse input of the reaction chamber, followed by the second oxygen-containing precursor pulses fed to the reaction chamber. 在每次脉冲输送之间,将吹洗气体引入反应室。 Between each pulse transmission, the purge gas is introduced into the reaction chamber. 将含铪前体脉冲输入反应室,随后脉冲输送第一含氧前体,同时在每次脉冲输送之后接着进行吹洗便构成一个铪顺序。 The hafnium-containing body pulse input before the reaction chamber, followed by pulsing the former first oxygen-containing body, while pulsing after each followed by a purge sequence will constitute a hafnium. 类似地,将舍铝前体脉冲输入反应室,随后将第二含氧前体脉冲输入反应室,同时在每次脉冲输送之后接着进行吹洗便构成一个铝顺序。 Similarly, the rounded aluminum precursor pulse input of the reaction chamber, followed by the body before the pulse input of the second oxygen-containing reaction chamber, while feeding after each pulse followed by a purge of aluminum constitutes a sequence. 逸择第一含氣前体取决于被脉冲输入反应室的含铪前体,同样,第二含氧前体取决于被脉冲输入反应室的含铝前体。 Yi optional first gas precursor depends on the pulse input hafnium-containing precursor of the reaction chamber, and similarly, the second oxygen-containing precursors depends on the pulse input containing aluminum precursor reaction chamber. 另外,可以将不同的吹洗气体应用于铪顺序和铝顺序。 In addition, you can wash different blowing gas to the hafnium and aluminum sequential order. 此外,按照预定的周期逐一地对将每一种前体脉冲输入反应室加以控制,此处每种前体的预定周期根据前体的性质而不同。 Further, according to a predetermined one by one for each period one precursor pulse input to control the reaction chamber, each of the predetermined period where the precursor according to the nature of the precursor varies.

这样选择前体,以致在进行了一个铪顺序之后接着进行一个铝顺序便完成一次HfAlCb层的ALD沉积循环。 So choose precursor that after performing a sequence followed by a hafnium aluminum sequential ALD deposition cycle is completed once HfAlCb layer. HfAlO;j层的厚度取决于所采用的前体,脉冲输送的周期和工艺温度。 HfAlO; j precursor layer thickness depends on the use of periodic pulses delivered and the process temperature. 通过重复进行若干次铪顺序和铝顺序循环来形成具有预定厚度的HfA103薄膜。 By repeating the sequence several times hafnium and aluminum to form a cyclic order HfA103 film having a predetermined thickness. 一旦形成了具有要求厚度的HfA103薄膜,就对HfA103薄膜进行退火。 Once formed HfA103 film having a desired thickness, the film is annealed to HfA103.

在本发明的某一实施方案中,前体气体被用来在晶体管主体上形成用作栅介质的HfAK)3薄膜。 In one embodiment of the present invention, the precursor gas is used as the gate dielectric HfAK) 3 thin film transistor formed on the main body. 另一方面,固体或液体前体可用于恰当设计的反应室中。 On the other hand, a solid or liquid precursor can be used in appropriately designed reaction chamber. 其它材料的ALD形成公开于共同未决的,共同转让的美国专利申请中,标题"原子层沉积和转化"代理巻号303.802US1, 序列号10/137, 058,和"利用VLSI栅原子层沉积法形成的,用作栅介质层的AlOx原子层"。 ALD formed of other materials are disclosed in co-pending, commonly assigned U.S. patent application, the title "atomic layer deposition and transformation" Agent Volume No. 303.802US1, serial number 10/137, 058, and "the use of VLSI gate atomic layer deposition law is formed, as a gate dielectric layer AlOx atomic layer. " 代理巻号1303細画,系列号10/137, 168。 Acting Volume 1303 fine art, serial number 10/137, 168. 图2A描述了本发明所讲授的加工HfAlC)3薄膜用的原子层沉积系统的实施方案。 Figure 2A depicts the teachings of the present invention is processed HfAlC) Embodiment 3 films atomic layer deposition system. 所描述的部件是讨论本发明所必需的那些部件,以致本领域的那些技术人员无需过分的实验工作经验就可实践本发明。 Described components are those components of the present invention is necessary to discuss, so that those skilled in the art without undue experimentation work experience can practice the invention. 有关ALD反应室的进一步讨论可从在此引入作参考的,共同未决的,共同转让的美国专利申请:标题"均匀化学气相沉积所采用的方法,系统和装置",代理巻号303J17US1,系列号09/797324中找得。 For further discussion of ALD reaction chamber from which is hereby incorporated by reference, the co-pending, commonly assigned U.S. patent application: The title "Uniform chemical vapor deposition employed, systems and devices," Agent Volume No. 303J17US1, series No. 09/797324 are looking for, too. 在图2A中,村底210被放置在ALD系统200的反应室220内。 In FIG. 2A, the village at the end 210 is positioned within the reaction chamber 220 ALD system 200. 在反应室220内还放置了加热元件230,它和衬底210发生热耦合,以控制衬底的温度。 Also within the reaction chamber 220 heating element 230 is placed, it and the substrate 210 are thermally coupled, to control the temperature of the substrate. 气体分配装置240将前体气体引至衬底210。 Gas distribution means 240 of the precursor gas is introduced to the substrate 210. 每一种前体气体来源于各自的气体源251-254,其流量分别由质量流量控制器256~ 259控制。 Each precursor gas from the respective gas supply 251-254, respectively, by the flow mass flow controllers 256 to 259 control. 气体源251〜254或者通过储存气体状前体的方法或是通过 251~254 method before or gaseous body through the stored gas source or through

i^方法^提供前;气体。 ^ i ^ method before delivery; gas. 、"' ' , '' '

在ALD系统中还包括吹洗气体源261, 262,其中每个分別与质量流量控制器266, 267相耦合。 In ALD system further includes purge gas source 261, 262, respectively, and wherein each mass flow controllers 266, 267 are coupled. 气体源251 ~ 254和吹洗气体源261-262 通过它们的质量流量控制器与公共输气管或导管270相耦合,这输气导管又与反应室220内的气体分配装置240相耦合.这输气导管270 还通过质量流量控制器286与真空泵或排气泵281相耦合,以便在吹洗程序结束时从输气导管中除去剩余的前体气体,吹洗气体,和副产 Gas source 251 to the purge gas source 254 and 261-262 by their mass flow controller 270 and the common pipeline or conduit coupled to this gas conduit 220 and the reaction chamber and the inner gas distribution means 240 is coupled to this input gas conduit 270 through mass flow controller 286 and a vacuum pump or an exhaust pump 281 is coupled, to remove residual precursor gas from gas duct purge at the end of the process, the purge gas, and byproduct

品气体。 Product gas.

真空泵或排气泵282与质量流量控制器28"7相耦合,以便在吹洗程序结束时从反应室220中除去剩余的前体气体,吹洗气体,和副产物气体。为了方便起见,本领域的那些技术人员熟知的控制器显示器, 固定装置,温度传感器件,衬底操纵装置和必需的电气引线,在图2A 上均未示出。 Exhaust pump 282 and the vacuum pump or the mass flow controller 28 'is coupled to 7, to remove residual precursor gas from the reaction chamber 220 at the end of the purge process, purge gas, and byproduct gases. For convenience, in the art well known to those skilled in the controller display fixture, a temperature sensor element, the substrate handling means and the necessary electrical leads, in FIG. 2A are not shown.

图2B描述了本发明所讲授的加工HfA103薄膜用的原子层沉积室的气体分配装置的实施方案。 Figure 2B depicts an embodiment of a gas distribution device according to the present invention process taught HfA103 films atomic layer deposition chamber. 气体分配装置240包括气体分配部件242 和气体进气管244。 Gas distribution means 240 comprises a gas distribution member 242 and the gas inlet pipe 244. 气体进气管244使气体分配部件242与图2A的输气导管270相耦合。 Gas inlet pipe 244 of the gas distribution component gas conduit 242 and 270 of FIG. 2A coupled. 气体分配部件242包括气体分配孔或出口246和气体分配管道248。 Gas distribution means 242 includes a gas distribution holes or outlet 246 and the gas distribution pipeline 248. 在这示范性实施方案中,这些孔246基本上都是具有同样的直径为15~20微米的圃;气体分配管道248具有同样的宽度20~45微米。 In this exemplary embodiment, the holes 246 basically have the same diameter of 15 to 20 microns garden; gas distribution pipes 248 have the same width of 20 to 45 microns. 具有气体分配孔246的气体分配部件的表面249基本上是平面且平行于图2A的衬底210。 Gas distribution hole 246 having a gas distribution member 249 is substantially planar surface and parallel to the substrate 210 of FIG. 2A. 但是,其它一些实施方案采用了其它的表面形式以及孔和管道的形状和尺寸,孔的分布和尺寸还可能影响沉积厚度,因而可以用来参与厚度控制。 However, other embodiments using other forms of surfaces and holes, and the shape and dimensions of the pipe, and the pore size distribution may also affect deposition thickness and thus can be used to participate in thickness control. 孔246通过气体分配管道248与气体进气管244相耦合。 Hole 246 through the gas distribution piping 248 and 244 is coupled to the gas inlet pipe. 虽然ALD系统200很适宜于实践本发明,但市场上有售的其它ald系统也可使用。 Although ALD system 200 is suitable for the practice of the present invention, but the market for sale to other ald systems may be used.

沉积薄膜所采用的反应室的应用,结构和基本运作,对于半导体制作领域的那些普通技术人员来说都是了解的。 Applications, the basic structure and operation of the reaction chamber deposition film used for semiconductor fabrication to those of ordinary skill in the art to understand for both. 本发明可以在各种这样的反应室内得以实施无需过分的实验工作经验。 The present invention can be implemented without undue experimentation experience in a variety of such reaction chamber. 此外,本领域的每个普通技术人员一阅读本公开内容就将会理解半导体制作领域中所必需的探测,测量和控制技术。 In addition, each of ordinary skill in the art of a reading of the present disclosure will be understood that it is necessary in the field of semiconductor fabrication detection, measurement and control technology.

图3说明了本发明所讲授的HfAK)3薄膜加工方法的实施方案所采用的单元的流程图。 Figure 3 illustrates a flow chart of the present invention are taught HfAK) film processing method of Embodiment 3 employs a unit. 本方法可利用图2A, B所示的原子层沉积系统得以实现。 This method can be used to Figure 2A, B atomic layer deposition system shown can be achieved. 在程序块305内,制备衬底。 In block 305, the substrate is prepared. 用来形成晶体管的衬底典型地是硅或含硅材料。 A substrate for forming a transistor is typically a silicon or silicon-containing materials. 在其它实施方案中,可以采用锗,砷化镓,和蓝宝石上硅衬底。 In other embodiments, it may be employed germanium, gallium arsenide, and silicon-on-sapphire substrates. 这制备方法包括在形成栅介质之前清洗衬底210和形成衬底的各层和各个区,例如金属氧化物半导体(MOS)晶体管的漏区和源区。 This preparation includes cleaning the substrate prior to forming the gate dielectric 210 and the formation of layers and each region of the substrate, such as metal-oxide-semiconductor (MOS) transistor, the drain region and the source region. 正被加工的晶体管其各个区的形成顺序遵循着在MOS晶体管的制作中通常采用的,本领域的那些技术人员众所周知的典型顺序。 The formation order is being processed for each region of the transistor which followed in the production of MOS transistors commonly used, those skilled in the art of well-known typical sequence.

衬底区的掩蔽,、这正是mos制作过程中典型地j^进行的工作:在本实 Mask substrate region ,, this is the mos production process is typically performed j ^ work: in the present

施方案中,非掩蔽的区包括晶体管的主体区,可是,本领域的每个技术人员将认识到其它的半导体器件结构可以利用本方法。 Embodiments, the non-masked region includes a body region of the transistor, however, each skilled in the art will recognize that other semiconductor device structures may utilize this method. 另外,将处于准备加工状态的衬底210传送到进行ALD作业所采用的反应室220 中的某一位置上. Further the substrate, the processing in a ready state 210 is transferred to the reaction chamber 220 ALD operation used in a certain position.

在程序块310内,将含铪前体脉冲输入反应室220。 In block 310, the hafnium-containing precursor pulses fed to the reaction chamber 220. 尤其是,HfCl4 用作源材料。 Especially, HfCl4 used as source material. HfCl4通过位于衬底210上方的气体分配装置M0被脉冲输入反应室220。 HfCl4 located above the substrate 210 through the gas distribution means M0 is a pulse input chamber 220. 来自气体源251的HfCl4流量由质量流量控制器256 加以控制。 HfCl4 flow from the gas source 251 are controlled by the mass flow controller 256. HfC!4源的气体温度范围为约130TC -约154TC。 ! HfC 4 source of the gas temperature in the range of from about 130TC - about 154TC. HfCU与位于由衬底210的非遮掩面所定义的要求区中的衬底210的表面发生反应》 HfCU react with the surface of the substrate at a defined by the cover surface 210 of the non-requirement region 210 of the substrate occurs. "

在程序块315内,将第一吹洗气体脉冲输入反应室220。 In block 315, the first purge gas pulses fed to the reaction chamber 220. 尤其是, In particular,

16纯度大于99,99%的纯净氮气用作HfClj的吹洗气体。 16 more than 99,99% purity pure nitrogen as a purge gas HfClj. 来自吹洗气体源261的氮进入输气导管270的流量由质量流量控制器266控制。 From the purge gas source 261 of nitrogen into the gas flow conduit 270 is controlled by the mass flow controller 266. 利用纯净氮气吹洗避免了前体脉冲和可能的气相反应发生重叠。 Use pure nitrogen purge to avoid a possible precursor pulse and the gas phase reactor overlap. 吹洗之后, 在程序块320内,将第一含氧前体脉冲输入反应室220。 After purging, in block 320, the first oxygen-containing precursor pulse input chamber 220. 对于使用HfCl4 For HfCl4

作为前体的铪顺序,选择水蒸气作为前体起着氧化反应物的作用,以便在衬底210上形成氧化铪。 As a hafnium precursor sequence, reactant selection steam oxidation plays a role as a precursor for hafnium oxide is formed on the substrate 210. 来自气体源2"的水蒸气,利用质量流量控制器257,以约0,5~约1.0mPamV秒的流速,通过输气导管270, 将其脉冲输入反应室220。水蒸气在村底210的表面上发生积极的反应。 From the gas source 2 "of water vapor, using the mass flow controller 257, from about 0.5 to about 1.0mPamV sec flow through the gas conduit 270, which is the pulse input of water vapor in the reaction chamber 220. The bottom 210 of the village occur on the surface of a positive response.

在脉冲输送氧化反应物水蒸气之后,在程序块内,将第一吹洗气体喷射入反应室220。 After the oxidation reaction was pulsing vapor within the block, the first purge gas is injected into the reaction chamber 220. 在HfCl4/水蒸气顺序中,在脉冲输送每种前体气体之后,利用纯氮气体吹洗反应室。 In HfCl4 / water vapor sequence, after the pulsing of each precursor gas using nitrogen gas purge the reaction chamber. 利用吹洗气体,清除掉系统中的剩余前体气体和反应副产物,同时利用真空泵282,通过质量流量控制器287抽空反映器220,和利用真空泵281,通过质量流量控制器286抽空输气导管270。 The use of purge gas, the system removed the residual precursor gas and reaction by-products, while the vacuum pump 282, through a mass flow controller 287 reflects 220 evacuated, and the vacuum pump 281, a mass flow controller 286 was evacuated through the gas conduit 270.

在实施HfCW水蒸气顺序过程中,通过加热元件230和使用呈低压(250Pa)热壁构形的反应室一起使衬底温度保持为约350*0~约550 1C。 In order to implement HfCW steam process, by heating element 230 and use was low pressure (250Pa) hot-wall reaction chamber together with the topography and the substrate temperature maintained at about 350 * 0 to about 550 1C. 在其它的一些实施方案中,使衬底温度保持为约5001C - IOOOTC。 In other embodiments, the substrate temperature is maintained at about 5001C - IOOOTC. HfCl4的脉冲输送时间在约1.0秒- 2.0秒范围内。 HfCl4 pulse delivery time of about 1.0 seconds - within 2.0 seconds range. 在脉冲输送HfCLj之后,继续进行包括吹洗脉冲,接着水蒸气脉冲,再接着吹洗脉冲在内的铪顺序,在一种实施方案中,进行吹洗脉冲,接着水蒸气脉冲,再接着吹洗脉冲共费时约2秒。 After pulsing HfCLj, proceed comprising purging pulse, then the pulse water vapor, followed by purging pulse sequence including hafnium, in one embodiment, pulse purged, followed by water vapor pulse, followed by purge pulse total took about two seconds. 在另一实施方案中,在脉冲输送HfCl4 之后,在铪顺序中,每个脉冲有2秒的脉冲周期。 In another embodiment, after pulsing HfCl4, Hf in sequence, each pulse has a pulse period of 2 seconds.

在程序块330内,将含铝前体脉沖输入反应室220。 In block 330, the aluminum-containing precursor pulse input chamber 220. 在一种实施方案中,在HfCli/臭氧顺序之后,三甲基铝(TMA) , AS (CH3) 3,用作含铝前体。 In one embodiment, after HfCli / ozone sequence, trimethyl aluminum (TMA), AS (CH3) 3, as an aluminum-containing precursor. 来自气流源253的TMA,利用质量流量控制器"8,通过气流分配装置240,将其脉冲输送到村底210的表面。TMA被引至在HfCl4/水蒸气顺序进行过程中形成的二氧化铪薄膜上。 TMA gas flow from source 253, using the mass flow controller "8, through the air distribution device 240, which pulses supplied to the bottom surface 210 of the village is introduced to the process .TMA formed HfCl4 / steam sequence of hafnium oxide film.

在程序块335内,第二吹洗气体被引入系统。 In block 335, the second purge gas is introduced into the system. 对于TMA前体,纯净氩气用作吹洗气体和载气。 For TMA precursors, pure argon gas is used as a purge gas and a carrier gas. 来自吹洗气源262的氩气进入输气导管270,随后进入反应室220,其流量由质量流量控制器267控制。 From purge gas source 262 into the argon gas conduit 270, and then into the reaction chamber 220, the flow controller 267 is controlled by the mass flow. 在经氩气吹洗之后,在程序块340内,将第二含氧前体脉冲输入反应室220。 After argon-purged, in block 340, the second oxygen-containing precursor pulses fed to the reaction chamber 220. 对于使用TMA作为前体的铝顺序,选用蒸馏水蒸气作为前体起氧化反应物作用,以便和位于衬底210上的TMA相互作用。 For TMA as the aluminum precursor sequence, use distilled water vapor from the oxidation reaction is as a precursor role for and located on the substrate 210. TMA interactions. 来自气体源254 的蒸馏水蒸气,利用质量控制器259,通过输气导管270将其脉冲输入反应室220。 Distilled water vapor from the gas source 254, the use of quality controller 259 via gas conduit 270 to 220 pulses fed to the reaction chamber. 蒸馏水蒸气在衬底210的表面上发生积极的反应,从而形成HfAK)3薄膜。 Distilled water vapor positive reactions occur on the surface of the substrate 210, thereby forming HfAK) 3 film.

在脉冲输送起氧化反应物作用的蒸馏水蒸气之后,在程序块345 内,将第二吹洗气体喷射入反应室220。 After the pulse was delivered from the oxidation effects of distilled water vapor, in block 345, the second purge gas is injected into the reaction chamber 220. 在TMA/蒸馏水蒸气顺序中, 在脉沖输送每种前体气体之后,用氩气吹洗反应室。 In the TMA / distilled water vapor sequence, pulsing after each precursor gas, purged with argon chamber. 在另一实施方案中,纯净氮气重新用作吹洗气体。 In another embodiment, pure nitrogen gas is reused as purge. 利用吹洗气体,清除掉系统中的剩余前体气体和反应副产物,同时利用真空泵282,通过质量流量控制器287,抽空反应室220,和利用真空泵281,通过质量流量控制器286, 抽空输气导管270。 The use of purge gas, rid the system of the gas and the remaining reaction byproduct precursors, while taking advantage of the vacuum pump 282, through the mass flow controller 287, evacuation of the reaction chamber 220, and the vacuum pump 281, through the mass flow controller 286, taking input gas conduit 270. 这不仅完成了TMA/蒸馏水蒸气顺序,而且它还完成了铪顺序/铝顺序循环,从而形成了具有与一种ALD循环有关的设定厚度的HfAK)3层。 This not only completed the TMA / distilled water vapor order, and it completed the hafnium order / aluminum order cycle, which formed a combination with one ALD cycle-related setting the thickness of the HfAK) 3 layers.

在进行TMA/蒸馏水蒸气顺序的过程中,通过加热元件230,使衬底温度保持为约350TC ~约4501C。 Conducting TMA / distilled water vapor sequential process, by heating element 230, the substrate temperature is maintained from about 350TC ~ to about 4501C. 使反应室的温度保持为约150TC, 以便使反应物凝结的可能性降至最低。 The temperature of the reaction chamber is maintained at about 150TC, so that the possibility of condensation of the reactants to a minimum. 使工艺压力在脉冲输送前体气体时保持为约230 m托,而用于脉冲输送吹洗气体时保持为约200 m 托。 Making the process pressure was maintained at about 230 m Torr, and maintained at about 200 m Torr for pulsing purge gas at the pulsing precursor gas. 用于TMA和蒸馏水蒸气二种前体的脉冲时间均约为1秒,而用于吹洗的脉冲时间约为15秒。 Pulse time for TMA and distilled water vapor two precursor was about one second, and used to purge the pulse time of about 15 seconds. 在一种实施方案中,在完整的HfCW水蒸气/TMA/蒸馏水蒸气循环过程中,使衬底温度保持为约3501C。 In one embodiment, the full HfCW steam / TMA / distilled water steam cycle process, the substrate temperature is maintained at about 3501C. 在另一实施方案中,在完整的HfCl4/水蒸气/TMA/蒸馏水蒸气循环过程中,使衬底温度保持为约550TC。 In another embodiment, the intact HfCl4 / steam / TMA / distilled water steam cycle process, the substrate temperature is maintained at about 550TC.

作为一种替代的铝顺序,可使用DMEAA/氧顺序而不是TMA/蒸馏水蒸气顺序。 As an alternative to aluminum order, may be used DMEAA / oxygen instead of sequentially TMA / distilled water vapors order. 含铝前体DMEAA是一种铝烷(A1H3)和二甲基乙烷[N (CH3) 2 (C2H5)】的加合物。 DMEAA aluminum-containing precursor is an aluminum alkyl (A1H3) and dimethyl ethane [N (CH3) 2 (C2H5)] adduct. 在程序块330内,来自气体源253的DMEAA气体被脉冲输送到衬底210表面上。 In block 330, DMEAA gas from the gas source 253 is pulsed into the surface of the substrate 210. 通过将温度控制在25TC 的气泡型蒸发作用向气体源253提供DMEAA气体。 By controlling the temperature of the bubble-type evaporation 25TC DMEAA in providing gas to the gas source 253. 在程序块335内, 与DMEAA有关的吹洗气体和载气是来自吹洗气体源262的氢。 In block 335, and DMEAA relevant purge gas and the carrier gas is hydrogen from purge gas source 262. 在程序块340内,为了在衬底210上产生必要的反应,来自气体源254的作为第二舍氧前体的氧被脉冲输入反应室220。 In block 340, in order to generate the necessary response on a substrate 210, from the gas source 254 second homes as an oxygen precursor is pulsed oxygen fed to the reaction chamber 220. 在程序块M5内,来自吹洗气体源262的吹洗气体氢再次流过反应室220。 In the block M5, purge gas from purge gas source 262 through the hydrogen flow reaction chamber 220 again.

18在进行DMEAA/氧顺序的过程中,利用加热元件230使衬底温度保持为约100TC ~约1251C。 Process 18 during DMEAA / oxygen in order, by heating element 230 so that the substrate temperature maintained at about 100TC ~ about 1251C. 在进行DMEAA/氧顺序的过程中,使工艺压力保持为约30m托。 Process during DMEAA / oxygen in order to make the process pressure was maintained at approximately 30m Torr.

在利用DMEAA替代铝顺序时,可在与TMA/蒸馏水顺序相同的温度和压力范围下使用DMEAA/蒸馏水蒸气顺序。 In the use of DMEAA order instead of aluminum may be used DMEAA / distilled water vapor in the order and TMA / distilled water order in the same temperature and pressure range. 在本发明的某一实施方案中,在完整的HfCW水蒸气/DMEAA/蒸馏水蒸气循环过程中使衬底温度保持为约3501C。 In one embodiment of the present invention, in the full HfCW steam / DMEAA / distilled water steam cycle process, to maintaining the substrate temperature of about 3501C. 另一方面,可在使衬底温度保持为约550TC 的条件下,进行完整的HfCW水蒸气/DMEAA/蒸馏水蒸气循环。 On the other hand, the substrate temperature can be maintained under conditions of about 550TC, a complete HfCW steam / DMEAA / distilled water steam cycle.

在一个循环之后的HfA103薄膜的厚度,在已知温度下,由在铪顺序和铝顺序中所采用的脉冲周期确定。 In a cycle of a thickness of the film after HfA103, at a known temperature, determined by the order in hafnium and aluminum used in the pulse sequence cycle. ALD方法的脉沖周期取决于所使用的反应系统200和前体以及吹洗气体源的特性。 The method depends on the pulse period 200 and ALD precursor and purge gas source used in the reaction system properties. 典型地,在给定温度下,脉冲周期可以在一个要比前体的最小脉冲时间长一些的较大范围内变化,但基本上没有改变生长速率。 Minimum pulse over a long time, typically, at a given temperature, pulse period than the body can be in front of a large range of some changes, but essentially unchanged growth rate. 一旦一个循环的周期组被确定,那么HfAK)3薄膜的生长速率将被定为某一值例如Niim/循环。 Once a cycle period group is determined, then HfAK) growth rate of the third film will be set to a value such as Niim / cycle. 例如在形成MOS晶体管的栅介质的应用中,为了使HfAK)3薄膜达到要求的厚度t, ALD方法应重复t/N次循环。 For example, in the application of the gate dielectric of the MOS transistor is formed, in order to HfAK) 3 to achieve the required film thickness t, ALD method should be repeated t / N cycles.

在程序块350内,要确定HfA103薄膜是否达到了要求的厚度t。 In block 350, to determine whether the requirements HfA103 film thickness t. 正如所述,要求的厚度应在t/N次循环后完成。 As mentioned, the thickness of the claim should be completed in the t / N cycles. 如果完成的循环次数小于t/N,本方法从脉冲输送含铪前体的程序块310处重新开始,在上面所讨论的实施方案中,这含铪前体就是HfCl4气体。 If the number of cycles completed less than t / N, the method comprising the block from the pulsing hafnium body 310 before restart, in embodiments discussed above, this body is HfCl4 hafnium-containing gas before. 如果t/N次循环已完成,不再进一步要求继续ALD作业,而在程序块355内,对HfA103 薄膜进行退火。 If t / N cycles have been completed, no further requested to continue ALD operation, and in the 355 block of HfA103 film annealed. 退火是生产HfAl03薄膜的最后的加热循环,是在温度约300TC〜8001C下进行的,以便生产出具有最佳性能的介质绝缘体。 Annealing is a film production HfAl03 last heating cycle is carried out at a temperature of about 300TC~8001C to produce a medium insulator has the best performance. 退火可以在惰性气氛或氮气气氛中进行。 Annealing may be performed in an inert atmosphere or nitrogen atmosphere.

在程序块360内,在形成HfA103薄膜之后,含HfA103薄膜的器件的加工便完成了。 In block 360, after forming HfA103 film processing devices containing HfA103 film is complete. 在一种实施方案中,完成这个器件包含完成晶体管的构成。 In one embodiment, the device contains complete completion constituting transistors. 另一方面,完成这方法包括完成存储器的构建,这存储器具有由HfA103薄膜栅介质形成的存取晶体管组成的阵列。 On the other hand, the completion of this method include building complete memory, this memory has an array of access transistor gate dielectric film formed by the HfA103 composition. 再者,在另一实施方案中,完成这方法包括含有信息处理器的电子系统的形成, 这信息处理器采用的电子器件使用了由HfA103薄膜栅介质形成的晶体管。 Further, in another embodiment, this method comprises forming a complete information processor containing an electronic system, the electronic device which uses the information used by the processor HfA103 gate dielectric film transistor formed. 典型地,信息处理器例如计算机包括许多存储器,这些存储器内装有许多存取晶体管。 Typically, information processor such as a computer comprising a plurality of memory, many of these memories built access transistor. 在一种实施方案中,用作栅介质的Hf线薄膜是通过采用铪/水蒸气/铝/水蒸气循环的ALD方法使其形成在晶体管的本体区内。 In one embodiment, the line is used as the gate dielectric film of Hf is hafnium by using / steam / ALD method Al / steam cycle to form the body region of the transistor. 这循环是铪/水蒸气顺序和铝/水蒸气顺序的组合。 This cycle is hafnium combination / sequential and aluminum vapor / steam sequence. 在铪/水蒸气顺序结束时终止这循环将典型地导致形成Hf02薄膜。 This cycle is terminated at the end of a hafnium / steam sequence will typically result in the formation Hf02 film. 只进行铝/水顺序则典型地会导致 Were only aluminum / water order will typically lead to

形成Al203薄膜。 Al203 film form.

聂近W,Zhu等人在第一届国际电子器件会议上发表的,刊登在会议论文集P.463-466 (2001 )上的论文,报导了利用喷射蒸汽沉积法形成的Hf02和HfAlO薄膜的生长。 Nie near W, Zhu et al., At the first session of the International Electron Devices Meeting on published P.463-466 papers published in the Conference Proceedings (2001), and reported the formation of an ink-jet vapor deposition of thin films Hf02 and HfAlO Growth. 大约3 nm厚的Hf02薄膜在400 1C -5001C下似乎发生了晶化,而含有约6.8% Al的HfAlO薄膜在比Hf02薄膜约高200TC的温度下发生晶化,舍有约31/7% Al的HfAlO薄膜则在比HfO2薄膜约高400"C的温度下发生晶化。因此,该论文指出HfAlO薄膜在较高温度下对其进行加工时往往导致形成结晶形结构, 可是非晶形结构有利于用作栅介质。 Hf02 about 3 nm thick film at 400 1C -5001C seems to happen a crystallized while HfAlO film contains about 6.8% Al at a temperature higher than Hf02 film about the occurrence of crystallization 200TC, homes about 31/7% Al The HfAlO film is higher than HfO2 film about 400 "C occurs at a temperature of crystallization. Therefore, the paper points out HfAlO films processed at higher temperatures tend to result in the formation of its crystalline structure, but the amorphous structure facilitates used as the gate dielectric.

最近J.Aarik等人在应用表面科学第173巻P,15 ~ 21 ( 2001)上发表了一篇论文,报导了通过使用HfCLj/水蒸气顺序的ALD形成Hf02 薄膜的生长。 Recently J.Aarik et al. Applied Surface Science Volume 173 P, 15 ~ 21 (2001) published a paper, reported growth by using HfCLj / vapor sequential ALD film forming Hf02. 在衬底温度保持在从500C到1000TC范围内的不同温度的情况下,HfOU源的温度范围为1301C-154*C。 In the case where the substrate is maintained at a temperature of from 500C to 1000TC range of different temperatures, HfOU source temperature range of 1301C-154 * C. 对于衬底温度为940 C和水蒸气流速0.7 mPa/m3的情况,已证实最终的薄膜结构取决于HfCU源的温度。 For a substrate temperature of 940 C and water vapor flow rate of 0.7 mPa / m3 in the case, it has confirmed that the final film structure depends on the temperature HfCU source. 在HfCL(源温度为128t:时,薄膜是单斜晶系的,此时生长速率为0.034 nm/循环,而在104源温度为152C时,薄膜是立方晶系的,此时生长速率为0.067 nm/循环。该报导断定,通过采用HfCl4 和水蒸气的ALD生长成的Hf02薄膜的表面结构,当改变生长温度和前体剂量时,可以发生变化。 In HfCL (source temperature of 128t: 152C, the film is a cubic system, the film is monoclinic, this time the growth rate of 0.034 nm / cycle, and in a 04 source temperature, where growth rate of 0.067 nm / cycle. The report concluded that, by adopting HfCl4 and steam ALD grown Hf02 surface structure of the film, when changing the growth temperature and precursor dose, can be changed.

最近Y.Kim等人在应用物理通讯71 (25 )巻P,3604~3606 (1997) 页上发表的论文,报导了通过使用TMA/蒸馏水蒸气顺序的ALD形成A】203薄膜的生长。 Recently Y.Kim et al. Applied Physics Letters 71 (25) Volume P, 3604 ~ 3606 on the (1997) page papers, reported by using the TMA / ALD distilled water vapor formed sequentially grown A] 203 film. 在衬底温度保持为3701C和TMA和蒸馏水蒸气的脉冲输送时间设定为各l秒的情况下,人1203薄膜的生长速率确定为每个循环约0,19nm。 The substrate temperature was maintained at 3701C and TMA and distilled water vapor pulsing time is set to l seconds each case, the growth rate of people 1203 film is determined for each loop about 0,19nm. 确定的这个生长速率对于TiN, Si,和Si02衬底都是相同的。 The growth rate determined for the TiN, Si, Si02, and the substrate are the same. 在最近由C.Jeong等人发表的刊登在日本应用物理杂志第40巻1部1章P.285-289页(2001 )上的论文中,报导了利用ALD 在IOOTC下A1203的生长速率为24.4A/循环,此处一个循环为利用DMEAA作为前体进行五次Al沉积随后是02等离子体氧化。 In a recent publication by the C.Jeong et al published in the paper (2001) on the Japanese Journal of Applied Physics 40, Volume 1 Chapter 1 P.285-289 page, we reported the use of ALD growth rates in IOOTC A1203 24.4 A / cycle, where a cycle of use DMEAA conducted as a precursor Al deposition followed by five 02 plasma oxidation. 典型地,由ALD形成的A1203薄膜是非晶形的。 Typically, the A1203 film formed by the ALD amorphous.

含HfA103, Al203和HfC)2的介质薄膜具有的介电常数在从A1203 的介电常数9到Hf02的介电常数25的范围内。 Containing HfA103, Al203 and HfC) dielectric film 2 has a dielectric constant in the range from 9 to Hf02 A1203 permittivity of the dielectric constant (25). 通过控制铪顺序的循环次数和铝顺序的循环次数,就能控制沉积在衬底表面区上的铪和铝的数量。 By controlling the sequence of cycles of hafnium and aluminum sequential cycles, you can control the number of hafnium and aluminum is deposited on the substrate surface area. 因此,通过采用铪顺序和铝顺序的ALD所形成的介质薄膜可利用由含有选定或预定百分率的HfA103,入1203和Hf02组成的组合物制成,在这种情况下,这薄膜的有效介电常数将被选定或预定在9〜25 的范围内。 Therefore, the dielectric film by using a hafnium aluminum sequential order and can be formed utilizing ALD composition containing a selected or predetermined percentage HfA103, 1203, and the composition is prepared consisting of Hf02, in this case, the effective dielectric film of this dielectric constant to be selected or predetermined in the range of 9~25. 此外,在铪顺序之后采用铝顺序,最后所得的含HfA103的 Further, after the hafnium aluminum sequential order, the last obtained containing HfA103

介质应是非晶形的。 The media should be amorphous.

除了分別控制在ALD方法中的铪顺序和铝顺序的循环次数外,也可通过控制以下因素将含有HfA103的介质薄膜制造成具有选定的特性,即控制每个顺序所用的前体材料,每个顺序所采用的工艺温度和压力,各个前体的脉冲输送时间,以及在本方法的末尾,在每个循环的末尾和在每个顺序的末尾的热处理。 In addition to the number of cycles were controlled ALD method hafnium and aluminum sequential order, but also by controlling the following factors will contain dielectric film HfA103 manufacturer to have selected characteristics, namely the control of precursor materials used for each sequence, each sequential process temperature and pressure employed, each precursor pulse delivery time, and at the end of the process, at the end of each cycle and heat-treated at the end of each sequence. 热处理可包括在原位在各种环境包括在氩和氮环境中进行退火。 The heat treatment may include in-situ annealing in a variety of environments including argon and nitrogen environments.

前体的脉冲输送时间范围为约0.5秒~约2至3秒,尽管可以使用较长的脉冲。 Precursor pulsing time is from about 0.5 seconds to about 2-3 seconds, although the use of a longer pulse. 典型地,吹洗气体的脉沖输送时间范围从等于与其相关的前体脉冲输送时间到数量级大于该相关前体脉冲输送时间,以便将 Typically, the purge gas pulse delivery times range from equal to its associated precursor pulsing time is orders of magnitude greater than the associated precursor pulsing time, in order to

所有剩余材料和副产物从反应系统中吹洗掉.通常吹洗气体的脉冲输送时间范围为约l秒-约30秒。 All surplus materials and byproducts from the reaction system is usually blown wash purge gas pulse delivery time ranges from about l seconds - about 30 seconds. 在一种实施方案中,吹洗气体的脉冲输送时间范围为1~2秒。 In one embodiment, the purge gas pulse delivery time ranges from 1 to 2 seconds.

所制成的含HfA103的薄膜的生长速率将受各个顺序的生长速率控制,而典型地可以是约0,34A/循环-约5A/循环。 The growth rate of the film containing HfA103 made will be subject to the control of the growth rate for each sequence, and typically can be about 0,34A / cycle - about 5A / cycle. 其它的生长速率也可获得。 Other growth rate can be obtained.

在本发明的各种实施方案中可能得到的等效氧化物厚度"q的范围 In the scope of various embodiments of the present invention may be obtained in the equivalent oxide thickness "q of

与形成具有介电常数为约9~约25的组合物的能力有关,和与达到实体薄膜厚度约2 -约3 nm和以上的能力有关。 And the ability to form a dielectric constant of the composition of about 9 to about 25 relevant, and achieve solid film with a thickness of about 2 - about 3 nm and above capacity. 符合本发明的"的范围示于下表: The extent consistent with the present invention "is shown in the following table:

21<table>table see original document page 22</column></row> <table> 21 <table> table see original document page 22 </ column> </ row> <table>

含HfA103的层其定标的下限将取决于形成全带隙所必须的薄膜的各单层,以使底层硅层和对着HfAK)3薄膜的上层导电层之间保持良好绝缘性。 Containing layer HfA103 its lower limit will depend on the formation of scaling each full bandgap monolayer film necessary to make between the underlying silicon layer and the opposite HfAK) 3 upper conductive thin film layer to maintain good insulation. 这一要求是避免底层硅层和上层导电层之间可能发生短路所必需的,根据上面所述,可明显看到可以实现使含HfA103的薄膜具有 This requirement is to avoid that may occur between the underlying silicon layer and an upper conductive layer short necessary, according to the above can be achieved is apparent containing film having HfA103

的t叫为3A~12A。 The t called for the 3A ~ 12A. 再说,基本上没有界面层的薄膜可以达到的teq显 Moreover, virtually no interface layer film can be achieved significant teq

著地小于2或3A甚至小于L5A。 3A with less than 2 or even less than L5A.

上面所述的利用铪顺序/铝顺序沉积循环进行原子层沉积的新颖方法具有很多优点。 The use of the above-described sequence of hafnium / aluminum deposition sequence of a novel method of atomic layer deposition cycles has many advantages. 再者,通过独立地控制每个顺序的各个参数便可形成具有选定介电常数的栅介质。 Furthermore, by independently controlling the parameters of each sequence can be formed having a selected dielectric constant gate dielectric. 另外,提供的这新颖的方法可以用来形成各种晶体管,存储器和信息处理器。 In addition, this novel method can be used to provide various transistors are formed, and the information processor memory.

图1中所描绘的晶体管100可以由形成在硅基衬底110中的源/漏区120和另一个源/漏区130构成,而这二个源/漏区120, 130被主体区132隔开。 Source / drain regions 120 and another source / drain regions depicted in Figure 1 may be formed of a transistor 100 formed in the silicon substrate 110 constituting 130, and these two source / drain regions 120, 130 separated by the body region 132 On. 源/漏12G和源/漏130隔开的主体区132定义了具有沟道长度134的沟道。 Source / drain 12G and the source / drain 130 separated from the main body region 132 defines a channel having a channel length of 134. HfAK)3薄膜利用ALD方法形成,这ALD方法包括将含铪前体脉冲输入装有衬底110的反应室,将第一含氧前体脉冲输入反应室,将含铝前体脉冲输入反应室,以及将第二含氧前体脉冲输入反应室。 HfAK) 3 ALD method for forming a film utilizing this ALD method includes hafnium-containing precursor pulse input containing the reaction chamber of the substrate 110, the first oxygen-containing precursor pulse input of the reaction chamber, the aluminum-containing precursor pulse input reaction chamber and the second oxygen-containing precursor pulses fed to the reaction chamber. 每一种前体根据选定的时间周期被脉冲输入反应室。 Each one precursor according to the selected time period is the pulse input of the reaction chamber. 脉冲输送每一种前体所需时间的长短根据所采用的前体选定。 Precursor pulsing time required for each precursor used in accordance with the length selected. 在每次脉冲输送前体之间,将剩余前体和反应的副产物从反应室中去除。 Between each pulsing precursor-product remaining precursor and reaction removed from the reaction chamber. HfA103 薄膜的厚度由重复进行脉冲榆送含铪前体,第一含氧前体,含铝前体, 和第二含氧前体的循环次数来控制,直到在主体区上形成要求厚度的舍HfA103的薄膜140。 HfA103 film thickness by repeated pulse transmission elm hafnium-containing precursor, a first oxygen-containing precursor, an aluminum-containing precursor, and a number of cycles of the second oxygen-containing precursor is controlled, until the formation of the body region thickness requirement homes HfA103 film 140. 栅形成在栅介质140的上方。 Gate is formed over the gate dielectric 140. 典型地,形成栅包括形成多晶硅层,虽然在另外别的方法中可以形成金属栅。 Typically, the polysilicon layer forming the gate comprises forming, although other methods may be in another form a metal gate. 可采用本领域的那些技术人员周知的标准方法来形成村底,源/漏区和栅。 Standard methods to those skilled in the art may be used to form a well-known village at the end, the source / drain region and the gate. 另外,用来形成晶体管的工艺各个单元的操作程序是按照对本领域的那些技术人员来说也是周知的标准制作程序进行的。 In addition, procedures for forming the respective units in accordance with the process of the transistors to those skilled in the art is also well-known standard production procedures.

利用ALD形成用作栅介质的HfAK)3薄膜的方法的实施方案可以应用于其它的含有介质层的晶体管结构。 ALD is used as the gate dielectric is formed utilizing the HfAK) Embodiment 3 of the method may be applied to a thin film transistor structure comprising other dielectric layers. 例如,图4描绘了一种本发明所讲授的可以用来制作一种晶体管400构型的实施方案。 For example, Figure 4 depicts a teaching of the present invention can be used to produce A transistor 400 configuration embodiments. 晶体管400 包括硅基衬底410和被主体区432隔开的二个源/漏区420, 430。 Transistor 400 comprises a silicon substrate 410 and the body region 432 spaced two source / drain regions 420, 430. 位于二个源/漏区420, 430之间的主体区432定义了具有沟道长度434的沟道区。 Located two source / drain regions 420, 430 between the body region 432 defines a channel region 434 having channel length. 位于主体区432上方的是叠层455,它包括栅介质440,浮栅452, 浮栅介质442,和控制栅450。 Located in the upper body region 432 is a laminate 455, which includes a gate dielectric 440, a floating gate 452, the floating gate dielectric 442, and a control gate 450. 栅介质440按照上述本发明所讲授的ALD 方法形成,而晶体管400的其余单元采用本领域的那些技术人员熟知的方法形成。 Gate dielectric 440 ALD method according to the present invention is formed as taught, while the rest of the cell transistor 400 of the present art methods well known to those skilled formed. 另一方面,栅介质440和浮栅介质442 二者均可按照上述本发明所讲授的ALD方法形成, On the other hand, the gate dielectric 440 and the floating gate dielectric 442 can be formed both ALD method according to the present invention are taught,

采用上述方法产生的晶体管可以用于存储器和包舍信息处理器的电子系统中。 Transistors produced by the above method can be used for storage and pack house information processor of electronic systems. 内含HfAK)3薄膜介质层的信息处理器可以采用上述方法的各种实施方案构成。 Containing HfAK) an information processor 3 thin-film dielectric layer may be employed in various embodiments of the method described above constitute. 这类信息处理器包括各种无线系统,电信系统和计算机。 Such information processor includes a variety of wireless systems, telecommunications systems and computers. 一种内含HfAK)3薄膜介质层的计算机实施方案示于图5~7 并叙述如下。 An intron HfAK) computer Embodiment 3 thin film dielectric layers are shown in Figures 5-7 and described below. 虽然下面所示的是特定形式的存储器和计算器件,但本领域的每一位技术人员都承认各个不同形式的存储器和和包含信息处理器的电子系统均可利用本发明。 Although shown below is a particular form of memory and computing devices, but every skill in the art will recognize various forms of memory and information and electronic system including processors can utilize the present invention.

个人用计算机如图5和图6所示,它包括监视器500,键盘输入502 和中央处理机504。 Personal computer shown in FIG. 5 and FIG. 6, which includes a monitor 500, keyboard input 502 and a central processing unit 504. 处理机部件504典型地包括微处理机606,存储器总线电路608,它含有许多存储器沟槽612 (a~n),和其它外围电路610。 Processor means 504 typically comprises a microprocessor 606, memory bus circuit 608, comprising a number of memory grooves 612 (a ~ n), and other peripheral circuits 610. 外围电路610允许各种外围器件6M通过输入/输出(I/O)总线622与处理机/存储器总线620连接。 Peripheral circuit 610 allows various peripheral devices 6M input / output (I / O) bus 622 is connected to processor / memory bus 620 through. 图5和图6所示的个人用计算机还包括至少有一个这样的晶体管,它具有按照本发明所讲授的一种实施方案形成的含HfA103薄膜的栅介质。 Individual Figures 5 and 6 as shown by computer further comprises at least one such transistor having a gate dielectric film containing HfA103 According to one embodiment of the present invention is formed as taught.

微处理机606产生控制和地址信号,以便控制存储器总线电路608 和微处理和606之间以及存储器总线电路608和外围电路610之间的数据交换。 The microprocessor 606 generates control and address signals to control data exchange circuit 608 and the memory bus between the microprocessor and the memory bus circuit 606 and 608 and between the peripheral circuit 610. 这种数据交换是通过高速存储器总线620和通过高速I/O总线622完成的。 This data exchange is through the completion of high-speed memory bus 620 and high-speed I / O bus 622.

许多存储器沟槽"2 (an)与存储器总线620耦合,这些沟槽能 Many memory groove "2 (an) coupled to memory bus 620, these grooves can

23容纳对本领域的那些技术人员来说是众所周知的各种存储器。 23 hold for those skilled in the art is well known all kinds of memory. 例如单 For example, single

列直插式存储模块(SIMM)和双列直插式存储模块(DIMM)可用于本发明的装置中。 In-line Memory Module (SIMM) and dual in-line memory module (DIMM) that can be used in the present invention.

这些存储器可根据各种不同的设计生产,这些设计提供不同的读出和写入存储器沟槽612的动态存储单元的方法。 These memories may be based on a variety of design and production, these designs provide different read and write memory trench method of dynamic memory cells 612. 一种这样的方法是页面模式运行。 One such method is the page mode operation. DRAM中的页面模式运行由如下方法定义,存取一行存储单元阵列和随机地存取这阵列的不同的列。 The DRAM page mode operation is defined by the following methods, accessing a row of memory cell array and random access to this array of different columns. 当存取该列的时候, 储存在上述行和该列相交处的数据便可读出并输出。 When access to the column, the data stored in the row and the column can be read out at the intersection and output. 页面模式DRAM 要求有一些限制存储器电路608通信速度的存取步骤。 Page Mode DRAM requires some limitations communication speed memory access circuit 608 steps.

一种替代型器件是扩充数据输出(EDO)型存储器,它使储存在存储器阵列地址处的数据,在寻址列已关闭之后仍可以有效输出。 An alternative is to expand the data output device (EDO) type memory, which allows data to be stored in the memory array at the address, after the address column is closed output can still be effective. 这种存储器由于允许较短的存取信号而增加了一些通信速度,但没有降低存储器输出数据在存储器总线620上有效的时间。 This memory by allowing shorter access signals and adds some communication speed, but the memory output data is valid on the memory bus 620 time is not reduced. 其它别的类型的器件包括SDRAM, DDR SDRAM, SU)RAM和直接式RDRAM,以及其它的例如SRAM或快速存储器。 Other other types of devices including SDRAM, DDR SDRAM, SU) RAM and Direct RDRAM, and other such as SRAM or Flash memory.

图7阐明了本发明所讲授的DRAM存储器700的实施方案的示意图。 Figure 7 illustrates a schematic view of the teachings of the present invention is an embodiment of a DRAM memory 700. DRAM器件700是与存储器沟槽612( a - n )相容的。 DRAM memory device 700 is a groove 612 - Compatibility (a n) of. 对DRAM 700 的叙述已作了简化,为的是阐明DRAM存储器而不是用来全面叙述DRAM的所有特性。 Description of the DRAM 700 has been simplified in order to clarify the DRAM memory rather than to a comprehensive account of all the characteristics of DRAM. 本领域的那些技术人员都承认各种各样的存储器均可用于本发明的装置中。 Those skilled in the art will recognize a wide variety of memory devices can be used in the present invention. 图6所示的DRAM存储器实例包括至少有一个这样的晶体管,它具有按本发明所讲授的实施方案形成的HfAI03 薄膜的栅介质。 DRAM memory example shown in Figure 6 comprises at least one such transistor having a gate dielectric taught by the invention embodiment formed HfAI03 film.

通过存储器总线620提供的控制,地址和数据信息由DRAM 700 的各路输入进一步表示,正如图7所示。 Control provided by the memory bus 620, the address and data information further indicated by the DRAM each input 700, as shown in Figure 7. 这些各路的表示由数据线702, 地址线704和指向控制逻辑部件706的各条分立的线来阐明。 The brightest is represented by the data lines 702, address lines 704 and pointing control logic unit 706 pieces of separate lines to clarify.

正如本领域内众所周知的,DRAM 700包括存储器阵列710,它本身包含行和列的可寻址存储器单元。 As well known in the art, DRAM 700 includes a memory array 710, which itself contains memory cells addressable in rows and columns. 同一行上的每个存储器单元与一条公用字线相耦合。 Each memory cell with a common word line coupled to the same line. 这字线与各个晶体管的栅相耦合,此处至少有一个晶体管具与采用前面所述方法和结构形成的含HfA103的栅介质相耦合的栅。 This word line coupled to the gate of each transistor, having at least one transistor with a gate dielectric containing HfA103 using previously described methods and structures formed by the gate coupled here. 另外,在同一列上的每个存储器单元与一条公用位线相耦合。 Further, each memory cell and a common bit line coupled to the same column. 在存储器阵列710中的每个单元包括本领域内常见的存储电容器和存取晶体管。 Each cell in the memory array 710 include the art of common access transistor and a storage capacitor. 例如,DRAM 700通过地址线704和数据线702与微处理机606 相连接。 For example, DRAM 700 are connected via address lines 704 and data lines 702 and the microprocessor 606. 另一方面,DRAM700可以与DRAM控制器,微控制器,芯片装置或其它电子系统相连接。 On the other hand, DRAM700 can be connected to a DRAM controller, a microcontroller, a chip or other electronic systems. 微处理机606还向DRAM 700提供许多控制信号,包括但不限于行和列地址选通信号RAS和CAS,写入启动信号WE,输出启动信号OE和其它常规控制信号。 The microprocessor 606 also offers many control signals to DRAM 700, including, but not limited to the row and column address strobe signal RAS and CAS, write enable signal WE, an output enable signal OE, and other conventional control signals.

行地址援冲器712和行译码器714接收和译解来自行地址信号的行地址,这行地址信号由微处理机606经地址线704提供'每个唯一的行地址与存储器阵列710中的一行单元相对应。 The row address 712 rushing aid row decoder 714 and to receive and decode row address signal from the row address, this row address signal 704 'each unique row address memory array 710 by the microprocessor 606 via address lines The corresponding row of cells. 行译码器7"包括字线驱动器,地址译码器树,和电路系统,这电路系统译出收到的来自行地址緩沖器712的给定行地址以及通过字线驱动器有选择地激活存储器阵列710的适合的字线。 The row decoder 7 "includes word line driver, an address decoder tree, and electrical systems, this circuitry translated received from the row address buffer 712 and a row address given by the word line driver selectively activate memory Suitable array word lines 710.

列地址緩冲器716和列译码器718接收和译解通过地址线704提供的列地址信号。 Column address buffer 716 and column decoder 718 receiving and deciphering by the column address signal lines 704 provide. 列译码器718还确定列何时发生了故陣和确定置换列的地址。 The column decoder 718 also determines when columns have it front and determine the address of the replacement column. 列译码器718与读出放大器720相耦合。 Column decoder 718 and sense amplifier 720 is coupled. 读出放大器720与存储器阵列710的互补位线对相耦合。 Amplifiers 720 and complementary bit line memory array is read out 710 is coupled to.

读出放大器720与数据输入緩冲器722和数据输出緩沖器724相耦合。 The sense amplifier 720 and the data input buffer 722 and coupled to the data output buffer 724. 数据输入緩冲器722和数据输出緩冲器? Data input buffer 722 and data output buffer? 24均与数据线702相耦合。 24 are coupled to the data line 702. 在写入运作过程中,数据线702向数据输入緩冲器722提供数据。 In the write operation of the data line 702 to the data input buffer 722 provides data. 读出放大器720接收来自数据输入緩冲器722的数据并将数据储存在存储器阵列710中,以电荷形式储存在地址线704上规定地址处的单元的电容中。 The sense amplifier 720 receives the data buffer 722 and the data stored in the memory array 710 to the charge stored in the form of unit at the address on the address line 704 predetermined capacitance from the data input.

在读出运作过程中,DRAM 700将数据从存储器阵列710传输到微处理机606。 In the course readout, DRAM 700 will transfer data from the memory array 710 to the microprocessor 606. 在预充电运行期间使存取单元的互补位线平衡于基准电压,该基准电压由平衡电路和基准电压源提供。 During the pre-charging operation so complementary bit line access unit balance to the reference voltage, the reference voltage is provided by the balance circuit and a reference voltage source. 于是,储存在存取单元中的电荷与相关的位线分享。 Thus, the storage access unit in charge share associated with the bit line. 诸读出放大器720的一个读出放大器检测和放大互补位线之间的电压差。 Read-out of a sense amplifier 720 detects and amplifies the voltage difference amplifier complementary bit line. 读出放大器将放大的电压传到数据输出緩冲器724。 The sense amplifier to amplify the voltage transmitted data output buffer 724.

控制逻辑部件706用来控制DRAM 700的许多有用的功能。 The control logic unit 706 to control many useful features of DRAM 700. 此外, 正如本领域的那些技术人员所熟知的那些用来启动DRAM 700并使DRAM 700运作保持同步的各种控制电路和信号在本文中没有详述。 Moreover, as those skilled in the art are well known to those used to start the operation of DRAM 700 and DRAM 700 holding various control circuits and signals are not described in detail herein synchronized. 如上所迷,已对DRAM 700的叙述作了简化,以便阐明本发明和没有打算完整叙述DRAM的所有性能。 As described above, it has been simplified description of DRAM 700 in order to clarify the present invention and does not intend a complete description of all performance DRAM. 本领域的那些技术人员应认识,许多种存储器,包括但不限于,SDRAM, SLDRAM, RDRAM,和其它的DRAM和SRAM, VRAM和EEPROM,均可用于本发明的装置中。 Those skilled in the art will appreciate that many kinds of memory, including but not limited to, SDRAM, SLDRAM, RDRAM, and other DRAM and SRAM, VRAM and EEPROM, can be used in apparatus of the present invention. 文中所描述的DRAM装置仅是为了说明,并没有排他或限制的意图。 DRAM devices described herein are merely illustrative, and not exclusive or limiting his intention. 结论 In conclusion

一种舍HfAK)3的栅介质和一种制作这一类栅介质的方法生产出了一种可靠的栅介质,它具有的等效氧化物厚度比采用SiCh可能得到的要薄。 A method of homes HfAK) gate dielectric 3 and the method of making this type of gate dielectric to produce a reliable gate dielectric equivalent oxide thickness it has a specific use thinner SiCh might get.

使用本文中所述方法形成的HfAK)3栅介质是热力稳定的,以致形成的栅介质在加工过程中与硅衬底或其它结构有极微弱的反应。 Using the method described herein is formed HfAK) 3 gate dielectric is heat stable, so as to form the gate dielectric in the process has a very weak reaction with the silicon substrate or other structures.

晶体管,高水平IC或器件,和系统是应用了形成超薄等效氧化物 Transistors, high-level IC or device, and the system is applied to the formation of ultra-thin equivalent oxide

厚度teq的栅介质的新颖方法构成的。 Novel methods of gate dielectric thickness teq constituted. 形成的含HfA103的栅介质层或薄膜具有高的介电常数(K ),此处的栅介质的teq能够小于IOA,小 HfA103 containing gate dielectric layer or film having a high dielectric constant is formed (K), teq herein can be less than the gate dielectric IOA, small

于SiCh栅介质的预定限制值。 SiCh predetermined limit value in the gate dielectric. 同时,HfAK)3层的实体厚度比与SK32 Meanwhile, HfAK) entity than the thickness of the third layer and SK32

的teq限制值相关的SiCh厚度厚得多。 SiCh thicker limit value of teq much related. 形成较厚厚度有利于加工栅介 A thicker gate dielectric thickness is conducive to processing

质。 Quality. 此外,通过控制衬底的ALD加工过程中的铪顺序和铝顺序能使形成的含HfAl03, Ah03和Hf02的介质的介电常数可在A1203的介电常数到Hf02的介电常数范围内选择。 In addition, by controlling the substrate ALD process hafnium aluminum order to make the dielectric constant of the order and containing HfAl03, Ah03 and Hf02 medium A1203 formed in the dielectric constant of the dielectric constant to within Hf02 range selection.

虽然在本文中已对一些具体的实施方案作了阐明和陈述,但本领域的那些普通技术人员都知道,任何以达到同样目的为目标的方案均可以代替所示的这些具体实施方案。 Although some specific embodiments set forth and statements made in this article, but those of ordinary skill in the art will appreciate that any order to achieve the same purpose as the goal of the program can be replaced by these specific embodiments illustrated. 本申请意图是包舍本发明的任何修改或变更。 This application is intended to be rounded package of the present invention to make any changes. 可以认为上面的叙述是为了用来阐明的而不是限制的。 The above description is considered in order to clarify and not of limitation. 在审阅上面陈述时,上述实施方案和其它的实施方案的组合对本领域 When reviewing the above statement, combinations of the above embodiments and other embodiments of the art

的那些技术人员来说是显而易见的。 Those skilled apparent. 本发明的范围包括其中采用了上述结构和制作方法的任何其它申请。 The scope of the invention includes any other applications in which the use of the above-described structure and fabrication method. 本发明的范围应由附于后面的权 The scope of the invention should be attached to the right rear

利要求书,以及与该权利要求书所给予的范围等同的全范围来确定。 The claims, and given the scope of the full range of equivalents of the claims to determine.

26 26

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Classifications
International ClassificationH01L21/8242, H01L21/28, H01L29/51, H01L29/792, H01L27/10, H01L29/788, H01L27/108, H01L29/78, H01L21/316, H01L21/8247, C23C16/40, H01L27/115
Cooperative ClassificationH01L21/28185, H01L29/518, H01L29/513, H01L21/28176, H01L21/28194, H01L29/517
European ClassificationH01L21/28E2C2B, H01L21/28E2C2D, H01L21/28E2C2C, H01L29/51M, H01L29/51B2
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