CN100478907C

CN100478907C - PCT bus protocol monitor card

Info

Publication number: CN100478907C
Application number: CNB200510120980XA
Authority: CN
Inventors: 李�杰
Original assignee: Mitac Computer Shunde Ltd
Current assignee: Mitac Computer Shunde Ltd; Shunda Computer Factory Co Ltd
Priority date: 2005-12-22
Filing date: 2005-12-22
Publication date: 2009-04-15
Anticipated expiration: 2025-12-22
Also published as: CN1987811A

Abstract

This invention discloses a PCI main lines protocol monitor card which can plug into the PCI slug of the main board of the computer, the signal and the plug signal introducing foot corresponds with each other and contains the some function module, they can monitor the normal data exchange sequence between the computer main board and object device, whether it accords with the standard of the PCI protocol, and it also can monitor and measure the return data for the computer main board when the object device is fault. This invention discloses the PCI main lines protocol monitor card, which can judge whether the computer main board can do the corresponding response to the wrong data transmission sequence of the PCI device.

Description

The pci bus protocol monitor card

Ji Intraoperative field

The present invention is relevant for a kind of pci bus protocol monitor card.

Bei Jing Ji Intraoperative

At present the pci bus protocol monitor card mainly is the whether standard of accord with PCI bus protocol of the sequential of control measurement computer motherboard pci bus when normally sending data to the sequential of target device and the normal echo back data of target device to the computer motherboard pci bus, and can not monitor and measure to the sequential of computer motherboard pci bus target device mistake echo back data.Therefore, the pci bus protocol monitor card can not determine whether computer motherboard can make corresponding response to the data transmission of PCI Device Errors sequential at present.

So develop the pci bus protocol monitor card that a kind ofly can monitor and measure, can monitor and measure to the sequential of computer motherboard pci bus target device mistake echo back data again to the sequential of computer motherboard pci bus and the normal swap data of target device for computer industry such as researching and developing or there is certain significance aspect such as manufacturing.

Summary of the invention

The present invention has overcome the deficiencies in the prior art, and a kind of pci bus protocol monitor card is provided.This pci bus protocol monitor card can be monitored and measure also and can monitor and measure to the sequential of computer motherboard pci bus target device mistake echo back data the sequential of computer motherboard pci bus and the normal swap data of target device.

For reaching above-mentioned purpose, this pci bus protocol monitor card can be inserted in the computer motherboard PCI slot, its signal pins is corresponding one by one with this PCI slot signal pins, it comprises plurality of function modules: a PCI address date cache module, one PCI instruction cache module, one parity checking instruction module, one parameter configuration register, one slave unit Logic control module, one main equipment Logic control module, one fifo circuit (Firstin First Out, be called for short FIFO) cache module, one direct storage access (Direct Memory Access is called for short DMA) module, one sequential detects Logic control module, control of one liquid crystal and display module, one internal memory control module, one memory modules, an one wrong time-sequence control module and a manual gauge tap module.

This slave unit Logic control module detects the sequential of computer motherboard pci bus and the normal swap data of this pci bus protocol monitor card by this sequential detection Logic control module, and the result is shown by this liquid crystal control and display module.

This hand control switch module can manually be set a high level and low level composite signal, produce wrong sequential via this mistake time-sequence control module, and make this main equipment Logic control module generation mistake read sequential to this pci bus by this parameter configuration register.Can at this moment, can find this mistake by detection computations machine mainboard pci bus controller, the concurrent information that makes mistake be to the user application interface.

Owing to adopt technique scheme; but the present invention is the sequential standard of accord with PCI agreement whether of supervisory control comuter mainboard pci bus and the normal swap data of target device not only, also can monitor and measure to the sequential of computer motherboard pci bus the unusual echo back data of target device.

Description of drawings

Fig. 1 is the functional module structure figure of pci bus protocol monitor card of the present invention.

Embodiment

The present invention is further detailed explanation below in conjunction with accompanying drawing.

Consult shown in Figure 1ly, it is the functional module structure figure of pci bus protocol monitor card of the present invention.This pci bus protocol monitor card 100 is inserted on the slot of computer motherboard pci bus 500, and this monitor card 100 is corresponding one by one with the signal pins of these pci bus 500 slots.Comprise a PCI address date cache module 110, a PCI instruction cache module 120 and a parity checking module 130 on this monitor card 100, wherein this PCI address date cache module 110 is responsible for these monitor cards 100 and is carried out the address date exchange with this pci bus 500, and this PCI instruction cache module 120 and this parity checking module 130 are responsible for these monitor cards 100 and this pci bus 500 and are instructed exchange.

This monitor card 100 also comprises a parameter configuration register 210, a slave unit Logic control module 220 and a main equipment Logic control module 230.

Wherein, this parameter configuration register 210 is connected with this PCI address date cache module 110, this PCI instruction cache module 120, this parity checking module 130 respectively, the line data of going forward side by side exchange; This slave unit Logic control module 220 is connected with this PCI address date cache module 110, this PCI instruction cache module 120, this parity checking module 130 respectively, the line data of going forward side by side exchange; This main equipment Logic control module 230 carries out exchanges data with this PCI address date cache module 110, this PCI instruction cache module 120, this parity checking module 130 respectively.

This slave unit Logic control module 220 also is connected with a sequential and detects Logic control module 310, and this sequential detects Logic control module 310 and connects a liquid crystal display and control module 410 again.

Be provided with a fifo circuit cache module 320 on this monitor card 100 again, it is responsible for carrying out exchanges data with this slave unit Logic control module 220 and this main equipment Logic control module 230, it also connects an internal memory control module 420, and this internal memory control module 420 connects a memory modules 430.

In addition, this monitor card 100 is provided with a manual gauge tap module 450, and this hand control switch module 450 connects a wrong time-sequence control module 440, and this mistake time-sequence control module 440 is connected to above-mentioned this parameter configuration register 210.

When 500 pairs of these monitor cards 100 of this pci bus are write data, when promptly this pci bus 500 sent data to this monitor card 100, this slave unit Logic control module 220 was write memory modules 430 by this fifo circuit cache module 320 and this internal memory control module 420 with data.And this sequential detects the action that command byte enable signal #C/BE that Logic control module 310 sends according to this slave unit Logic control module 220 judges execution, and by this liquid crystal control and display module 410 result is shown.

Work as #C/BE=4 ' b0011 output and show " carrying out I/O writes ".

Work as #C/BE=4 ' b0010 output and show " carrying out I/O reads ".

When the signal #FRAME of #C/BE=4 ' b0110 and this monitor card 100 was low level, output showed " carrying out 32 multibyte internal memories reads ".

When the signal #FRAME of #C/BE=4 ' b0110 and this monitor card 100 was high level, output showed " carrying out 32 multibyte internal memories reads ".

Work as #C/BE=4 ' b1011 output and show " configurable write ".

Work as #C/BE=4 ' b1010 output and show " configuration is read ".

When the signal #FRAME of #C/BE=4 ' b0111 and this monitor card 100 was low level, output showed " carrying out 32 multibyte internal memories writes ".

When the signal #FRAME of #C/BE=4 ' b0111 and this monitor card 100 was high level, output showed " carrying out 32 multibyte internal memories reads ".

When ending appears in data transmission, this monitor card 100 will just be judged the type that bus is ended by the level of signal #FRAME, #IRDY, #DEVSEL, #STOP and #TRDY on it, in addition, this signal #FRAME, #IRDY, #DEVSEL, #STOP and #TRDY are that low level is effective, high level is invalid, and decision logic is as follows:

1. at first clock of computer system, signal #FRAME is invalid, and signal #IRDY is effective, shows that last data segment carries out; At second clock, signal #FRAME is effective, and signal #IRDY is effective, shows that last data transmits generation; At the 3rd clock, signal #FRAME is invalid, and signal #IRDY is invalid, shows that bus gets back to idle condition.At this moment, this monitor card 100 goes out interpretation " bus master termination ", and demonstrates this result by this liquid crystal control and display module 410.

2. effective at first clock signal of computer system #FRAME, signal #IRDY begins effectively at the 3rd clock, but it is still invalid up to the 5th clock signal #DEVSEL, and that signal #IRDY becomes at the 6th clock is invalid, this monitor card 100 will be judged " bus master failure terminating " thus, and demonstrate this result by this liquid crystal control and display module 410.

3. effective at first clock signal of computer system #FRAME, signal #IRDY, #TRDY, #STOP, #DEVSEL are invalid; At second clock, signal #FRAME, #IRDY are effective, and signal #TRDY, #STOP, #DEVSEL are invalid; At the 3rd clock, signal #FRAME, #IRDY, #STOP, #DEVSEL are effective, and signal #TRDY is invalid; At the 4th clock, signal #FRAME, #IRDY, #STOP, #DEVSEL are effective, and signal #TRDY is still invalid.This monitor card 100 will be judged " target device stops and retry " thus, and demonstrate this result by this liquid crystal control and display module 410.

4. effective at first clock signal of computer system #FRAME, #DEVSEL, signal #IRDY, #TRDY, #STOP are invalid; At second clock, signal #FRAME, #TRDY, #STOP, #DEVSEL are effective, and signal #IRDY is invalid; At the 3rd clock, signal #FRAME is invalid, and signal #IRDY, #TRDY, #STOP, #DEVSEL are effective, and at the 4th clock, signal #FRAME, #IRDY, #TRDY, #STOP, #DEVSEL are invalid.At this moment, this monitor card 100 will be judged " target device is removed the A pattern ", and demonstrate this result by this liquid crystal control and display module 410.

5. effective at first clock signal of computer system #FRAME, #IRDY, #TRDY, #DEVSEL, signal #STOP is invalid; At second clock, signal #FRAME, #IRDY, #TRDY, #DEVSEL, #STOP are effective; At the 3rd clock, signal #FRAME, #TRDY are invalid, and signal #IRDY, #DEVSEL, #STOP are effective; At the 4th clock, signal #FRAME, #IRDY, #TRDY, #DEVSEL, #STOP are invalid.At this moment, 100 of this monitor cards will be judged " target device is removed the B pattern ", and demonstrate this result by this liquid crystal control and display module 410.

When this monitor card 100 when this pci bus 500 transmits data, this main equipment Logic control module 230 will control this fifo circuit cache module 320 from these memory modules 430 read datas to this pci bus 500, and control from these direct memory access (DMA) module 330 read datas to this memory modules 430.

By this hand control switch module 450 high level and low level composite signal can be set, produce wrong sequential via this mistake time-sequence control module 440, and make these main equipment Logic control module 230 generation mistakes read sequential to this pci bus 500 by this parameter configuration register 210.

The high-low level composite signal that this hand control switch module 450 is provided with is 0001 o'clock, and this mistake time-sequence control module 440 will be set system clock of #FRAME time-delay and send.

The high-low level composite signal that this hand control switch module 450 is provided with is 0010 o'clock, and this mistake time-sequence control module 440 will be set #IRDY time-delay four systems clock and send.

The high-low level composite signal that this hand control switch module 450 is provided with is 0100 o'clock, and this mistake time-sequence control module 440 will be set #DEVSEL response time eight clocks of delaying time.

The high-low level composite signal that this hand control switch module 450 is provided with is 1000 o'clock, and this mistake time-sequence control module 440 will be set #STOP response time six clocks of delaying time.

The high-low level composite signal that this hand control switch module 450 is provided with is 1111 o'clock, default setting, and this mistake time-sequence control module 440 will not produce wrong sequential.

Thereby, when the above-mentioned mistake of these main equipment Logic control module 230 generations is read sequential to this pci bus 500, can find this mistake by detection computations machine mainboard pci bus controller, the concurrent information that makes mistake is to the user application interface.

Claims

1. pci bus protocol monitor card, it can be inserted in the PCI slot of computer motherboard, and its signal pins is corresponding one by one with this PCI slot signal pins, but the sequential of its supervisory control comuter mainboard pci bus and the normal swap data of the target device standard of accord with PCI agreement whether, and it comprises:

One PCI address date cache module is used for this pci bus protocol monitor card and computer motherboard pci bus and carries out the address date exchange;

An one PCI instruction cache module and a parity checking instruction module are used for this pci bus protocol monitor card and computer motherboard pci bus and instruct exchange;

One parameter configuration register is connected with this PCI address date cache module, this PCI instruction cache module, this parity checking module respectively, the line data of going forward side by side exchange;

One slave unit Logic control module is connected with this PCI address date cache module, this PCI instruction cache module, this parity checking module respectively, the line data of going forward side by side exchange;

One main equipment Logic control module carries out exchanges data with this PCI address date cache module, this PCI instruction cache module, this parity checking module respectively;

Control of one liquid crystal and display module, it detects Logic control module by a sequential and is connected with this slave unit Logic control module, this slave unit Logic control module detects the sequential of computer motherboard pci bus and the normal swap data of this pci bus protocol monitor card by this sequential detection Logic control module, and the result is shown by this liquid crystal control and display module;

One direct storage access module, it is connected with this main equipment Logic control module, and both carry out exchanges data;

One fifo circuit cache module, it is connected respectively with this main equipment Logic control module with this slave unit Logic control module, again, this fifo circuit cache module is connected with an internal memory control module, and this internal memory control module connects a memory modules, and this memory modules, this internal memory control module carry out exchanges data with this slave unit Logic control module, this main equipment Logic control module respectively by this fifo circuit cache module; It is characterized in that:

This pci bus protocol monitor card also comprises a wrong time-sequence control module and a manual gauge tap module, this hand control switch module is connected to this parameter configuration register by this mistake time-sequence control module, and this pci bus protocol monitor card is also monitored and measured to computer motherboard in wrong sequential echo back data target device.

2. pci bus protocol monitor card according to claim 1, it is characterized in that: this hand control switch module can manually be provided with a high level and low level composite signal, produce wrong sequential via this mistake time-sequence control module, and make this main equipment Logic control module generation mistake read sequential to this pci bus by this parameter configuration register.