CN100477011C - Programming method of multiple level memory cell - Google Patents
Programming method of multiple level memory cell Download PDFInfo
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- CN100477011C CN100477011C CNB2005100776598A CN200510077659A CN100477011C CN 100477011 C CN100477011 C CN 100477011C CN B2005100776598 A CNB2005100776598 A CN B2005100776598A CN 200510077659 A CN200510077659 A CN 200510077659A CN 100477011 C CN100477011 C CN 100477011C
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Abstract
The invention relates to a method for programming multi-stage memory unit, which comprises: first, supplying memory unit which comprises the first and second memory positions; then erasing the memory units, to improve the threshold voltage value of first and second memory positions; then judging to compare the first and second programming conditions relative to the first and second memory positions, to select right program steps.
Description
Technical field
The present invention relates to a kind of method of operating of storer, and particularly relate to a kind of multi-level cell memory (Multiple Level Cell, programmed method MLC).
Background technology
Whether memory component still can preserve data after cutting off the power supply, can be divided into two kinds of volatibility and nonvolatile memories.Wherein, therefore nonvolatile memory has become extensively a kind of memory component of employing of personal computer and electronic equipment institute owing to have the advantage that still can preserve data after can writing, can wiping and cut off the power supply.
In general, nonvolatile memory is to be made of a plurality of storage unit, and each storage unit is to be formed with control grid layer storehouse successively by end dielectric layer (tunneling layer), charge storage layer, top dielectric layer (electric charge barrier layer).And according to the difference of the material of charge storage layer, non-volatile memory cells can be used for storing 1 or bits of data.Wherein, if the material of charge storage layer is a conductive material, then storage unit can be stored 1 data.And if the material of charge storage layer is a non-conducting material, then can be considered in the left and right sides of charge storage layer and have two memory locations, and the data that make a storage unit can store 2.
Yet because computer application software is huge gradually, required memory span is also just more and more big, therefore knownly can be used for storing 1 or 2 memory component and can't satisfy now demand.And, because the demand for the element integrated level is more and more higher now, therefore how under the prerequisite that does not influence the element integrated level, improve the capacity of storer, especially all circles' target of making great efforts.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of programmed method of multi-level cell memory, with under the prerequisite that does not influence the element integrated level, makes single memory cell can be used as multi-level cell memory and uses.
The present invention proposes a kind of programmed method of multi-level cell memory, and the method provides storage unit earlier, and this storage unit includes first memory location and second memory location, and wherein n position can be stored in each memory location, and includes 2 individually
nIndividual state with different threshold voltages value, and the threshold voltage value of these states is by the 1st state, the 2nd state ... to the 2nd
nState diminishes gradually.Originally, storage unit is carried out erase step (erase to high level), improving the threshold voltage value of first memory location and second memory location, and make its threshold voltage value greater than these states.Then, carry out determining step, relatively first programming state and second programming state of first memory location and the desire programming of second memory location institute.When first programming state is identical with second programming state, then storage unit is carried out bilateral (Two-Side) programming step; Be the 1st above-mentioned state one of in first programming state and second programming state, and another then carry out one-sided (One-Side) programming step to storage unit when being in addition other state of the 1st state; When first programming state and second programming state are not above-mentioned the 1st state, and the pairing threshold voltage value of this two condition then carries out suitching type bilateral (Switched Two-Side) programming step to storage unit when unequal.
According to the programmed method of the described multi-level cell memory of preferred embodiment of the present invention, above-mentioned bilateral programming step comprises: (a) carry out the programming in the time interval to one of in first memory location and second memory location.Then, (b) another memory location is carried out the programming in the same time interval.In addition, (b) also comprises afterwards in step: (c) detect step, whether equal first programming state and the pairing threshold voltage value of second programming state with first memory location confirming to have programmed and the threshold voltage value of second memory location, when if this two numerical value is unequal, then repeat at least step (a) and step (b), till this two numerical value equates.
Programmed method according to the described multi-level cell memory of preferred embodiment of the present invention, above-mentioned one-sided programming step comprises: (a) one of in first memory location and second memory location is programmed, the memory location of being programmed wherein, its pairing programming state is not the 1st state.In addition, (a) also comprises afterwards in step: (b) detect step, whether equal the threshold voltage value of pairing programming state to confirm its threshold voltage value of memory location of having programmed, when unequal as if this numerical value, then repeat at least step (a), till this numerical value equates.
According to the programmed method of the described multi-level cell memory of preferred embodiment of the present invention, above-mentioned suitching type bilateral programming step comprises: (a) compare first programming state and the pairing threshold voltage value of second programming state.Then, (b) select to have first programming state or second programming state than threshold voltage value, first programming is carried out in its pairing memory location, up to the threshold voltage value of first memory location and second memory location apart till the difference value.Then, (c) second programming is carried out in another memory location.In addition, also comprise before afterwards and in step (c) in step (b): (b1) detect step, whether equal above-mentioned difference value with first memory location confirming to have programmed and the gap between its threshold voltage value of second memory location, when if this two numerical value is unequal, then repeat at least step (a), till this two numerical value equates.In addition, (c) also comprises afterwards in step: (c1) detect step, whether equal the threshold voltage value of the corresponding programming state of institute with its threshold voltage value of memory location of confirming to have programmed, when unequal as if this two numerical value, then repeat at least step (c), till this two numerical value equates.
Because storage unit of the present invention is before programming, can carry out the judgement of the programming state of desire programming earlier, therefore can select suitable programming step to carry out data writes, and then can effectively control the distribution of the threshold voltage value of each state, use and make single memory cell can be used as multi-level cell memory.And, utilize suitable programming step to carry out data and write, can also make storage unit possess preferable monitoring window, and help follow-up memory cell read operation.In addition, utilize method of the present invention also can effectively control, and then reduce the erroneous judgement of data when subsequent read operations because of second harmful effect that effect caused.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the programming flow diagram according to a kind of multi-level cell memory of a preferred embodiment of the present invention.
Fig. 2 is the diagrammatic cross-section according to a kind of silicon nitride ROM of a preferred embodiment of the present invention.
Fig. 3 is the diagrammatic cross-section of silicon nitride ROM gained after wiping of Fig. 2.
Fig. 4 A is at the memory location 214b to the silicon nitride ROM of Fig. 2, the diagrammatic cross-section of gained after programming.
Fig. 4 B is at the memory location 214b to the silicon nitride ROM of Fig. 2, the diagrammatic cross-section of gained after programming.
Fig. 5 A is the programmable state that the bilateral programming step is suitable for.
Fig. 5 B is when carrying out the bilateral programming step, threshold voltage and programming time relation figure.
Fig. 6 A is the programmable state that one-sided programming step was suitable for.
Fig. 6 B is when carrying out one-sided programming step, threshold voltage and programming time relation figure.
Fig. 7 A, 8A, 9A are the programmable state that suitching type bilateral programming step is suitable for.
Fig. 7 B, 8B, 9B are when carrying out suitching type bilateral programming step, threshold voltage and programming time relation figure.
The main element description of symbols
100,102,104,106,108a, 108b, 108c: step numbers
200: silicon nitride read-only memory unit
202: substrate
204: tunneling layer
206: charge storage layer
208: electric charge barrier layer
210: the control grid layer
212a, 212b: doped region
214a, 214b: memory location
Embodiment
The programmed method of multi-level cell memory proposed by the invention is suitable for the non-volatile memory cells that charge storage layer is a non-conductive material, and it for example is a silicon nitride read-only memory unit.In addition, the method for programming of the present invention is the method for the programming that a kind of hole writes and electronics is wiped.Furtherly, the method for programming of the present invention is earlier with in the electronics iunjected charge accumulation layer, to improve the threshold voltage value of each storage unit in the whole memory component.Because this method of operating is that whole memory component is operated, therefore it can be considered as a kind of erase operation that utilizes electronics again.And then selected storage unit injected the hole of appropriate amount, reducing the threshold voltage value of memory location, thereby reach the purpose of programming.And above-mentioned hole writes and the method for the programming that electronics is wiped has the title of " PHINES operation ".
Please refer to Fig. 1, it is depicted as the programming flow diagram according to a kind of multi-level cell memory of a preferred embodiment of the present invention.In the method for programming of the present invention, at first provide storage unit, and this storage unit includes first memory location and second memory location (step 100).Wherein n position can be stored in each memory location, and includes 2 individually
nIndividual state with different threshold voltages value, and the threshold voltage value of these states is by the 1st state, the 2nd state ... to the 2nd
nState diminishes gradually.What deserves to be mentioned is that the pairing threshold voltage value of above-mentioned these states is all inequality, and the difference of the threshold voltage value between the adjacent two condition can be identical, also can be different.
Originally, said memory cells is carried out erase step, improving the threshold voltage value of first memory location and second memory location, and make the threshold voltage value (step 102) of its size greater than above-mentioned these states.Detailed explanation is, step 102 be utilize FN or-the FN tunneling effect, electronics is injected each storage unit of memory component.That is to say, utilize the mechanism of similar erase operation, make whole storage unit all be in the state of a high threshold voltage value.
Then, carry out determining step, relatively first programming state and second programming state (step 104) of first memory location and the desire programming of second memory location institute.Wherein, first programming state and second programming state are to be selected from above-mentioned the 1st state, the 2nd state ... to the 2nd
nState is wherein a kind of.And, what deserves to be mentioned is that first programming state can be identical with second programming state each other, also can be different.
Afterwards, select suitable programming step (step 106) according to result relatively.Detailed explanation is that step 106 is that selected storage unit is being carried out the operation that the hole is injected.Make the threshold voltage value of the win memory location and second memory location do the decline of degree varies by the hole of injecting appropriate amount, and reach purpose the storage unit programming.Wherein, alternative programming step comprises: when first programming state is identical with second programming state, storage unit is carried out bilateral programming step (step 108a); Be the 1st above-mentioned state one of in first programming state and second programming state, and another then carry out one-sided programming step (step 108b) to storage unit when being in addition other state of the 1st state; When first programming state and second programming state are not above-mentioned the 1st state, and the pairing threshold voltage value of this two condition then carries out suitching type bilateral programming step (step 108c) to storage unit when unequal.
Below to equal 2 with the n value be that example illustrates the present invention, only following content only is one embodiment of the present invention, and is non-in order to limit the present invention.In other words, also other round values of n value.
At first, carry out the step 100 of Fig. 1, storage unit with two memory locations is provided, it for example is a silicon nitride read-only memory unit 200 as shown in Figure 2, and this storage unit 200 is followed successively by tunneling layer 204, silicon nitride charge storage layer 206, electric charge barrier layer 208 and control grid layer 210 by substrate 202.In addition, storage unit 200 also includes doped region 212a and 212b and is arranged in control grid layer 210 substrate on two sides 202.
What deserves to be mentioned is, because silicon nitride charge storage layer 206 is dielectric material layer, therefore by voltage application, can inject electronics or hole respectively, thereby make silicon nitride charge storage layer 206 can provide two memory location 214a and 214b to write for data in its left and right sides.In addition, in the present embodiment, suppose that each memory location 214a, 214b can store 2 positions, then each memory location 214a, 214b can include 4 (2
2Individual) state with different threshold voltages value, it for example is (11) of (10) and the 4th state of (01), the 3rd state of (00), the 2nd state of the 1st state.
In addition, in the present embodiment, the threshold voltage value that the threshold voltage value of the 1st state (00) is set at 4.2 volts (V), the 2nd state (01) is set at 3.5 volts, the threshold voltage value of the 3rd state (10) and is set at 2.8 volts, the threshold voltage value of the 4th state (11) and is set at 2.1 volts.Therefore, in the present embodiment, threshold voltage value is to be successively decreased gradually toward the 4th state by the 1st state, and the threshold voltage value difference between the adjacent two condition is all 0.7 volt.But, in other embodiments, the threshold voltage value difference between the adjacent two condition can be inequality.In addition, for the memory cell read operation after making it can be carried out smoothly, therefore maximum with minimum threshold voltage difference can not be too little, to possess preferable monitoring window.In a preferred embodiment, maximum with minimum threshold voltage difference is at least 2 volts, so that preferable monitoring window to be provided.
Then, carry out the step 102 of Fig. 1, storage unit is carried out erase step, to improve the threshold voltage value of above-mentioned two memory locations.Detailed explanation is, utilize FN or-the FN tunneling effect, make in the electronics iunjected charge accumulation layer 206, and make each storage unit in the memory component all be positioned at high threshold voltage state of value (as shown in Figure 3).And its size of this high threshold voltage value can be greater than the threshold voltage value of the 1st～4 state.In one embodiment, the method for eraseable memory unit for example is that control grid layer 210 is applied-20 volts voltage, and doped region 212a and 212b apply 0 volt voltage, and make the threshold voltage of each storage unit rise to 7 volts.
Then, carry out the step 104 of Fig. 1, carry out determining step, first programming state and second programming state of more above-mentioned two memory location 214a, the desire programming of 214b institute.Wherein, first programming state and second programming state are to be selected from a kind of in the 1st state (00), the 2nd state (01), the 3rd state (10) and the 4th state (11) individually.Therefore, by the difference of this selected programming state in two memory locations, storage unit will have 16 kinds of possible programming kenels.
Afterwards, carry out the step 106 of Fig. 1, to select suitable programming step according to result relatively.In the present embodiment, because storage unit has 16 kinds of possible programming states, therefore in order to possess preferable monitoring window, the present invention is classified various possible programming states, and carrying out suitable programming step according to different classification, wherein alternative programming step comprises step 108a, 108b and the 108c among Fig. 1.
What deserves to be mentioned is that in the present invention, the various programming steps that proposed can utilize and can bring to hot hole (the Band-to-Band Hot Hole) effect that can be with and carry out, to inject the hole of appropriate amount respectively in memory location 214a, 214b.Wherein, the quantity in hole is to be decided by the time of programming, and the injected holes amount is many more, and the threshold voltage value of memory location 214a, 214b can descend many more.In one embodiment, it for example is that control grid layer 210 is applied-10 volts that utilization can bring to the programming that the hot hole effect that can be with carried out, doped region 212b is applied 5 volts, doped region 212a is applied 0 volt, with memory location 214b injected hole (shown in Fig. 4 A) at close doped region 212b.In another embodiment, it for example is that control grid layer 210 is applied-10 volts that utilization can bring to the programming that the hot hole effect that can be with carried out, doped region 212a is applied 5 volts, doped region 212b is applied 0 volt, with memory location 214a injected hole (shown in Fig. 4 B) at close doped region 212a.
Below further specify above-mentioned alternative programming step.
Please refer to Fig. 5 A, the programming state of programming when memory location 214a, 214b institute desire is identical, when for example memory location 214a, data that 214b desired to write one of are all in (00), (01), (10) and (11), then storage unit 200 is carried out the bilateral programming step.This bilateral programming step is earlier to carry out the programming (step 500) in the time interval to one of among memory location 214a, the 214b, afterwards again to another memory location 214b, 214a carry out equally should the time interval programming (step 502).In addition, for 16 kinds of possible programming states, 4 kinds of states in the middle of this bilateral programming step is applicable to.
What deserves to be mentioned is, when (for example: when memory location 214a) utilizing the hole to write to programme to one of them memory location, another memory location (for example: threshold voltage value memory location 214b) is the interaction of two memory locations therefore, and along with the threshold voltage value of the memory location of programming descend (shown in Fig. 5 B).Because these two memory locations all will write identical data, therefore the time of twice programming in front and back must be identical, so just can make the threshold voltage value decline scope identical.
In addition, except by round-robin step 500 and 502 the purpose that reaches programming, in another embodiment, to memory location 214a, when 214b programmes, can repeatedly circulate above-mentioned steps 500 and 502, and make threshold voltage value drop to the programming state that institute's desire is programmed, its pairing threshold voltage value gradually.And, after each circulation step 500 and 502, can detect step earlier, whether the threshold voltage value with the memory location 214a that confirms to have programmed and 214b equals the pairing threshold voltage value of programming state that desire is programmed, when if this two numerical value is unequal, then repeat again at least once to circulate, till this two numerical value equates.Wherein, this detects the similar read step of step, passes through the current value that monitored, judges the programming state that reaches institute's desire programming whether.
Then, please refer to Fig. 6 A, the programming state of programming when memory location 214b institute desire is the 1st state (00), and the programming state of another memory location 214a institute desire programming is the 1st state (00) other state in addition, for example when (01), (10), (11), then storage unit 200 is carried out one-sided programming step.This one-sided programming step is that memory location 214a is programmed, and equals up to the threshold voltage value of memory location 214a (step 600) till its pairing threshold voltage value of state of desire programming.Certainly, in another embodiment, the programming state of memory location 214a institute desire programming also can be the 1st state (00), and the programming state of another memory location 214b institute desire programming is the 1st state (00) other state in addition, for example (01), (10), (11).Therefore, for 16 kinds of possible programming states, 6 kinds of states in the middle of this one-sided programming step is applicable to.
What deserves to be mentioned is, when utilizing the hole to write to memory location 214a to programme, the threshold voltage value of another memory location 214b is the interaction of two memory locations therefore, and along with the threshold voltage value of the memory location of programming descend (shown in Fig. 6 B).And the fall of affected memory location its threshold voltage value of 214b can be less than the fall of memory location 214a.
In addition, except reaching the purpose of programming by the step 600 of carrying out once, in another embodiment, when memory location 214a is programmed, can repeat repeatedly step 600, and make threshold voltage value drop to its pairing threshold voltage value of programming state of institute's desire programming gradually.And, after step 600 each time, can detect step earlier, to confirm whether its threshold voltage value of memory location 214a of having programmed equals the threshold voltage value of the programming state of institute's desire programming, when if this two numerical value is unequal, then repeat one time step 600 more at least, till this two numerical value equates.Wherein, this detects the similar read step of step, passes through the current value that monitored, judges the programming state that reaches institute's desire programming whether.
Afterwards, please refer to Fig. 7 A, when the programming state of memory location 214a, 214b institute desire programming is not above-mentioned the 1st state, and the pairing threshold voltage value of this two condition then carries out suitching type bilateral programming step to storage unit when unequal.With Fig. 7 A is example, memory location 214a, the programming state of 214b institute desire programming is respectively (10) and (01), and this suitching type bilateral programming step is the pairing threshold voltage value of programming state (step 700) that compares this two desires programming earlier, select to have programming state afterwards than threshold voltage value, its pairing memory location (for example: memory location 214a) programme, up to memory location 214a and 214b till a difference value (step 702), switch then, (for example: memory location 214b) carry out another time programming (step 704) another memory location.Certainly, in other embodiments, the programming state of memory location 214a, 214b institute desire programming can be respectively (11) and (10) (shown in Fig. 8 A), (11) and (01) (shown in Fig. 9 A) or other kenel that is arranged in a combination by (01), (10), (11).Therefore, for 16 kinds of possible programming states, deduct the programming state that one-sided programming and two survey programming is suitable for, remaining programmable state is applicable to this suitching type bilateral programming step.
What deserves to be mentioned is, when in the ban memory location 214a being utilized the hole to write to programme, the threshold voltage value of another memory location 214b is the interaction of two memory locations therefore, and along with the threshold voltage value of the memory location of programming descend (shown in Fig. 7 B, 8B and 9B).And the fall of affected memory location its threshold voltage value of 214b can be less than the fall of memory location 214a.
In addition, for the storage unit that makes selected programming has good monitoring window, so the switching point that step 702 switches to step 704 also need be done suitable selection.With Fig. 7 B and 8B is example, suppose that the threshold voltage value difference between the adjacent two condition is a threshold voltage interval, for example 0.7 volt, and when its threshold voltage value difference of programming state of memory location 214a, 214b institute desire programming also is 0.7 volt, then the difference value in the step 702 at least should be greater than 1 volt, to obtain preferable monitoring window.And be example with Fig. 9 B, suppose that the threshold voltage value difference between the adjacent two condition is a threshold voltage interval, for example 0.7 volt, and when its threshold voltage value difference of programming state of memory location 214a, 214b institute desire programming is 1.4 volts, then the difference value in the step 702 at least should be greater than 1.6 volts, to obtain preferable monitoring window.
In addition, except reaching the purpose of programming by the step 702 of carrying out once, in another embodiment, when memory location 214a is programmed, can repeat repeatedly step 702, and make threshold voltage value drop to its pairing threshold voltage value of programming state of institute's desire programming gradually.And, after step 702 each time, can detect step earlier, whether equal above-mentioned difference value with the memory location 214a that confirms to have programmed and the difference of its threshold voltage value of 214b, if when this two numerical value is unequal, then repeat one time step 702 more at least, till this two numerical value equates.Wherein, this detects the similar read step of step, passes through the current value that monitored, judges the programming state that reaches institute's desire programming whether.
Similarly, except reaching the purpose of programming by the step 704 of carrying out once, in another embodiment, when memory location 214b is programmed, can repeat repeatedly step 704, and make threshold voltage value drop to its pairing threshold voltage value of programming state of institute's desire programming gradually.And, after step 704 each time, can detect step earlier equally, to confirm whether its threshold voltage value of memory location 214b of having programmed equals its pairing magnitude of voltage of programming state of desire programming, when if this two numerical value is unequal, then repeat one time step 704 more at least, till this two numerical value equates.Wherein, this detects the similar read step of step, passes through the current value that monitored, judges the programming state that reaches institute's desire programming whether.
In sum, the present invention has following advantage at least:
Since storage unit of the present invention the programming before, can carry out the judgement of the programming state of desire programming earlier, therefore can select suitable programming step to carry out data writes, and then can effectively control the distribution of the threshold voltage value of each state, use and make single memory cell can be used as multi-level cell memory.
2. the present invention is owing to utilize suitable programming step to carry out data to write, therefore can be so that storage unit is possessed preferable monitoring window, and help follow-up memory cell read operation.
3. utilize method of the present invention can effectively control, and then reduce the erroneous judgement of data when subsequent read operations because of second harmful effect that effect caused.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any one of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (14)
1. the programmed method of a multi-level cell memory is characterized in that comprising:
Storage unit is provided, and this storage unit includes first memory location and second memory location, and wherein respectively n position can be stored in this memory location, and includes 2 respectively
nIndividual state with different threshold voltages value, and the threshold voltage value of above-mentioned state is by the 1st state to the 2
nState diminishes gradually;
This storage unit is carried out erase step, improving the threshold voltage value of this first memory location and this second memory location, and make its threshold voltage value greater than above-mentioned state; And
Carry out determining step, relatively first programming state and second programming state of this first memory location and the desire programming of this second memory location institute,
When this first programming state is identical with this second programming state, then this storage unit is carried out first kind of programming step;
Be the 1st state one of in this first programming state and this second programming state, and another is when being other state beyond the 1st state, then this storage unit is carried out second kind of programming step, wherein this second kind of programming step comprises: one of in (d) programme this first memory location and this second memory location, the memory location of being programmed wherein, its pairing programming state is not the 1st state;
When this first programming state and this second programming state are not the 1st state, and when the pairing threshold voltage value of this two condition is unequal, then this storage unit is carried out the third programming step, wherein this third programming step comprises: (e) relatively this first programming state and the pairing threshold voltage value of this second programming state; (f) select to have this first programming state or this second programming state than threshold voltage value, first programming is carried out in its pairing memory location, up to the threshold voltage value of this first memory location and this second memory location apart till the difference value; And (g) another memory location is carried out second and programme.
2. the programmed method of multi-level cell memory according to claim 1 is characterized in that this first kind of programming step comprises:
(a) carry out the programming in the time interval to one of in this first memory location and this second memory location; And
(b) carried out should programming in the time interval equally in another memory location.
3. the programmed method of multi-level cell memory according to claim 2 is characterized in that also comprising afterwards in this step (b):
(c) detect step, whether equal this first programming state and the pairing threshold voltage value of this second programming state with this first memory location confirming to have programmed and the threshold voltage value of this second memory location, when if this two numerical value is unequal, then repeat at least step (a) and step (b), till this two numerical value equates.
4. the programmed method of multi-level cell memory according to claim 2 is characterized in that this step (a) and this step (b) are to utilize can bring to the hot hole effect that can be with and carry out.
5. the programmed method of multi-level cell memory according to claim 1 is characterized in that also comprising afterwards in this step (d):
(d1) detect step, whether equal the threshold voltage value of pairing this programming state, when unequal, then repeat at least step (d), till this two numerical value equates as if this two numerical value to confirm its threshold voltage value of memory location of having programmed.
6. the programmed method of multi-level cell memory according to claim 1 is characterized in that this step (d) is to utilize can bring to the hot hole effect that can be with and carry out.
7. the programmed method of multi-level cell memory according to claim 1 is characterized in that also comprising before afterwards and in this step (g) in this step (f):
(f1) detect step, whether equal this difference value with this first memory location confirming to have programmed and the gap between this its threshold voltage value of second memory location, if when this two numerical value is unequal, then repeat at least step (e), till this two numerical value equates.
8. the programmed method of multi-level cell memory according to claim 1, it is characterized in that the threshold voltage value difference between the adjacent two condition in this third programming step is a threshold voltage interval, and differ a threshold voltage at interval the time when this first programming state and this second programming state, then this difference value in the step (f) is at least greater than 1 volt.
9. the programmed method of multi-level cell memory according to claim 1, it is characterized in that the threshold voltage value difference between adjacent two these states in this third programming step is a threshold voltage interval, and differ two threshold voltages at interval the time when this first programming state and this second programming state, then this difference value in the step (f) is at least greater than 1.6 volts.
10. the programmed method of multi-level cell memory according to claim 1 is characterized in that also comprising afterwards in step (g):
(g1) detect step, whether equal institute to threshold voltage value that should programming state,, then repeat at least step (g), till this two numerical value is equal if when this two numerical value is unequal with its threshold voltage value of this memory location of confirming to have programmed.
11. the programmed method of multi-level cell memory according to claim 1 is characterized in that this step (f) and this step (g) are to utilize can bring to the hot hole effect that can be with and carry out.
12. the programmed method of multi-level cell memory according to claim 1 is characterized in that this erase step is to utilize the FN tunneling effect to carry out.
13. the programmed method of multi-level cell memory according to claim 1 is characterized in that the 1st state and the 2nd
nThe threshold voltage difference of state is at least 2 volts.
14. the programmed method of multi-level cell memory according to claim 13 it is characterized in that this n value equals 2, and respectively the difference of the threshold voltage value of this state is 0.7.
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