CN100461425C - Operation method for memory in P type channel - Google Patents
Operation method for memory in P type channel Download PDFInfo
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- CN100461425C CN100461425C CNB2005100919642A CN200510091964A CN100461425C CN 100461425 C CN100461425 C CN 100461425C CN B2005100919642 A CNB2005100919642 A CN B2005100919642A CN 200510091964 A CN200510091964 A CN 200510091964A CN 100461425 C CN100461425 C CN 100461425C
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Abstract
The P channel memory includes at least following parts: substrate; grid pole on the substrate; structure of trapping charges positioned between substrate and grid pole; first source pole/drain pole and second source pole/drain pole positioned in substrate on two sides of the structure of trapping charges. When carrying out erasing operation, the method applies first voltage to second source pole/drain pole, applies second voltage to first source pole/drain pole, applies third voltage to grid pole, and applies fourth voltage to substrate. Using mechanism of triple hot holes injects hot holes to the structure of trapping charges in order to erase P channel memory. Absolute value of voltage difference between third voltage and fourth voltage is smaller than or equal to 6 volts, and second voltage is smaller than third voltage.
Description
Technical field
The present invention relates to a kind of method of operation of semiconductor memory component, particularly relate to a kind of method of operation of P type channel transistor structure.
Background technology
Can electricity erasing and programmable read only memory (EEPROM) has the actions such as depositing in, read, erase that can carry out repeatedly data in the non-volatility memorizer, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory component of extensively adopting.
Typically can erase and polysilicon (Polysilicon) the making floating grid (Floating Gate) and control grid (Control Gate) of programmable read only memory by electricity to mix.In the prior art, also have the charge immersing layer of employing (Charge Trapping Layer) to replace polysilicon floating gate, the material of this charge immersing layer for example is a silicon nitride.This silicon nitride charge immersing layer respectively has one deck silica up and down usually, and forms silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide is called for short ONO) composite bed.This kind element is commonly referred to as silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon (SONOS) element.
Generally speaking, memory component is divided into P type raceway groove (P-Channel) memory and N type raceway groove (N-Channel) memory with the kind of its raceway groove.Wherein, N type channel transistor structure utilizes the operation that channel hot electron injection (Channel Hot Electron Injection) pattern and FN tunneling effect (Fowler-Nordheim Tunneling) carry out sequencing, erase more.Yet the FN tunneling effect need apply higher operating voltage, the power dissipation height, and the time of cost is also long.In order to improve wearing tunnel efficient and increasing element integrated level (Integrity) of electronics, the tunnel oxide thickness of memory can become very thin.But after size was dwindled, the knot breakdown voltage (BreakdownVoltage) of tunnel oxide also descended thereupon, and it can't bear FN and wear the required high voltage of tunnel, and can produce the problem of leakage current, reduce the reliability of memory.
On the other hand, P type channel transistor structure has higher element integrated level, can avoid hot hole and inject and to have lower advantages such as oxide layer electric field when the integrity problem caused and electronics inject.And its electronics injection rate is also fast than N type channel transistor structure, has characteristics such as lower power consumption, low power consuming, low sequencing voltage again concurrently, has been widely used in the semiconductor related industry at present.
Fig. 1 illustrate is the operation chart of existing a kind of P type channel transistor structure (as No. the 6801456th, United States Patent (USP)).This P type channel transistor structure comprises substrate 100, be arranged at ONO layer 110 (ONO layer 110 is made of silicon oxide layer 102, silicon nitride layer 104 and silicon oxide layer 106) in the substrate 100, be arranged at the P type doped polycrystalline silicon grid 120 on the ONO layer 110, and is arranged at source electrode 130a and drain electrode 130b in ONO layer 110 substrate on two sides 100.If desire to carry out erase operation for use, can make source electrode 130a, drain electrode 130b is 0 volt of voltage, apply-6 volts of voltages in grid 120, apply+6 volts of voltages, the stored data of script are erased to utilize FN tunneling effect or hot hole to inject (Hot HoleInjection) in substrate 100.
Above-mentioned P type channel transistor structure is owing to use the FN tunneling effect or the method for operation of hot hole injection, and its operating efficiency is lower, thereby need apply high voltage so that bigger electric current to be provided, and uses the raising operating efficiency.When carrying out erase operation for use, the voltage difference that grid 120 and substrate are 100 is up to 12 volts, and the time of its power consumption height, needs is longer, and the voltage height that applies, and causes high leakage current easily, causes the reliability of memory component to reduce.In addition, along with the raising of element integrated level, the high leakage current that is produced can be serious more, the degree that the limiting element size is dwindled.
Summary of the invention
In view of this, purpose of the present invention is exactly that the operating voltage that applies is low in the method for operation that a kind of P type channel transistor structure is provided, and can save power consumption, improves the efficient of sequencing/erase, and then shortens the running speed of memory, and promotes its reliability.
Another object of the present invention provides a kind of method of operation of P type channel transistor structure, can dwindle along with size of component, promotes its electrical performance, and helps to improve the integrated level of element.
The present invention proposes a kind of method of operation of P type channel transistor structure, this P type channel transistor structure for example is at least: substrate, in suprabasil grid, charge trapping structure between substrate and grid, and first source/drain and second source/drain that are arranged in the charge trapping structure substrate on two sides.The method is injected the charge trapping structure of first source/drain side with electronics, to deposit first in P type channel transistor structure when carrying out programming operations; And when carrying out erase operation for use, apply first voltage in second source/drain, first source/drain applies second voltage, grid applies tertiary voltage, substrate applies the 4th voltage, utilize three hot hole mechanism (Tertiary Hot Hole Mechanism) hot hole to be injected the charge trapping structure of first source/drain side, before deposit first of P type channel transistor structure in to erase, wherein, the absolute value of the pressure reduction of tertiary voltage and the 4th voltage is less than or equal to 6 volts, and second voltage is less than tertiary voltage.
According to the method for operation of the described P type of the preferred embodiments of the present invention channel transistor structure, the first above-mentioned voltage is about about 0 volt, second voltage is about-3～-4 volts, tertiary voltage is about-2.5～-3.5 volts, the 4th voltage is about 2.8～3.4 volts.
Method of operation according to the described P type of the preferred embodiments of the present invention channel transistor structure, can also be when carrying out programming operations, apply the 5th voltage in second source/drain, first source/drain applies the 6th voltage, and grid applies the 7th voltage, substrate applies the 8th voltage, electronics is injected the charge trapping structure of first source/drain side, to deposit first in, wherein in P type channel transistor structure, the 6th voltage is less than the 7th voltage, and the 7th voltage is greater than tertiary voltage.In a preferred embodiment, the 5th voltage is about about 0 volt, the 6th voltage is about-3～-4 volts, the 7th voltage is about-0.5～-1.5 volt, the 8th voltage is about 0～1 volt.In addition, the method with electronics iunjected charge immersal structure can be that channel hot electron injects (CHEI) pattern.
According to the method for operation of the described P type of the preferred embodiments of the present invention channel transistor structure, can also be when carrying out programming operations, electronics is injected the charge trapping structure of second source/drain side, to deposit second in P type channel transistor structure; And when carrying out erase operation for use, apply first voltage in first source/drain, second source/drain applies second voltage, grid applies tertiary voltage, substrate applies the 4th voltage, utilize three hot hole mechanism that hot hole is injected the charge trapping structure of second source/drain side, before deposit second of P type channel transistor structure to erase in.Wherein, when carrying out programming operations, more can apply the 5th voltage in first source/drain, second source/drain applies the 6th voltage, grid applies the 7th voltage, substrate applies the 8th voltage, electronics is injected the charge trapping structure of second source/drain side, to deposit second in P type channel transistor structure.The method of electronics iunjected charge immersal structure is comprised that channel hot electron injects (CHEI) pattern.
According to the method for operation of the described P type of the preferred embodiments of the present invention channel transistor structure, the material of above-mentioned grid for example is the polysilicon that the P type mixes, and charge trapping structure can be a silicon oxide/silicon nitride/silicon oxide.
The present invention proposes the method for operation of another kind of P type channel transistor structure, be applicable to P type channel silicon-silicon oxide/silicon nitride/silicon oxide-silicon (SONOS) memory, P type raceway groove SONOS memory for example is at least: the substrate of P type, be arranged in suprabasil ONO layer, be positioned at the P type doped polycrystalline silicon grid on the ONO layer, first source/drain that is positioned at ONO layer substrate on two sides and second source/drain.The method is when carrying out programming operations, apply first voltage in second source/drain, first source/drain applies second voltage, P type doped polycrystalline silicon grid applies tertiary voltage, substrate applies the 4th voltage, electronics is injected the ONO layer of first source/drain side, to deposit first in P type raceway groove SONOS memory, wherein, second voltage is less than tertiary voltage.When carrying out erase operation for use, apply the 5th voltage in second source/drain, first source/drain applies the 6th voltage, grid applies the 7th voltage, substrate applies the 8th voltage, hot hole is injected the ONO layer of first source/drain side to utilize three hot hole mechanism, before deposit first of P type raceway groove SONOS memory in to erase, wherein, the absolute value of the pressure reduction of the 7th voltage and the 8th voltage is less than or equal to 6 volts, the 6th voltage is less than the 7th voltage, and the 7th voltage is less than tertiary voltage.
According to the method for operation of the described P type of the preferred embodiments of the present invention channel transistor structure, can also be when carrying out programming operations, electronics is injected the ONO layer of second source/drain side, to deposit second in P type raceway groove SONOS memory; When carrying out erase operation for use, apply the 5th voltage in first source/drain, second source/drain applies the 6th voltage, grid applies the 7th voltage, substrate applies the 8th voltage, utilize three hot hole mechanism that hot hole is injected the ONO layer of second source/drain side, before deposit second of P type raceway groove SONOS memory to erase in.
Method of operation according to the described P type of the preferred embodiments of the present invention channel transistor structure, wherein when carrying out programming operations, can also apply first voltage in first source/drain, second source/drain applies second voltage, grid applies tertiary voltage, substrate applies the 4th voltage, electronics is injected the ONO layer of second source/drain side, to deposit second in P type raceway groove SONOS memory.The method of electronics iunjected charge immersal structure is comprised that channel hot electron injects (CHEI) pattern.
According to the method for operation of the described P type of the preferred embodiments of the present invention channel transistor structure, the first above-mentioned voltage is about 0 volt, second voltage is about-3～-4 volts, tertiary voltage is about-0.5～-1.5 volt, the 5th voltage is about 0 volt, the 6th voltage is about-3～-4 volts, the 7th voltage is about-2.5～-3.5 volts, the 4th voltage is about 0～1 volt, the 8th voltage is about 2.8～3.4 volts.
P type channel transistor structure of the present invention is because of adopting the operation that three times hot hole mechanism is erased, therefore required operating voltage is low, can save power consumption, improves the efficient of sequencing/erase, shorten the running speed of memory, and the reliability that can promote element.In addition, parallel electric field produces owing to applied three the hot hole mechanism of erase operation for use are based on, and therefore along with size of component is dwindled, more can promote its electrical performance, and help to improve the integrated level of element.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrate is the operation chart of existing a kind of P type channel transistor structure.
Fig. 2 illustrate is the section of structure according to a kind of P type channel transistor structure of one embodiment of the present invention.
Fig. 3 illustrate is a kind of P type channel transistor structure programming operations schematic diagram according to one embodiment of the present invention.
Fig. 4 illustrate is a kind of P type channel transistor structure erase operation for use schematic diagram according to one embodiment of the present invention.
Fig. 5 illustrate is a kind of P type channel transistor structure programming operations schematic diagram according to another preferred embodiment of the present invention.
Fig. 6 illustrate is a kind of P type channel transistor structure erase operation for use schematic diagram according to another preferred embodiment of the present invention.
Fig. 7 illustrate is the section of structure according to the P type channel transistor structure that has two position memory functions in one embodiment of the present invention.
The simple symbol explanation
100,200: substrate
102,106: silicon oxide layer
104: silicon nitride layer
The 110:ONO layer
120:P type doped polycrystalline silicon grid
130a: source electrode
130b: drain electrode
201:P type channel transistor structure
202: end dielectric layer
204: charge immersing layer
206: the top dielectric layer
210: charge trapping structure
220: grid
230a, 230b: source/drain
240: the first
242: the second
Embodiment
Fig. 2 illustrate is the section of structure according to a kind of P type channel transistor structure of one embodiment of the present invention.Fig. 3 illustrate is a kind of P type channel transistor structure programming operations schematic diagram according to one embodiment of the present invention.Fig. 4 illustrate is a kind of P type channel transistor structure erase operation for use schematic diagram according to one embodiment of the present invention.Fig. 5 illustrate is a kind of P type channel transistor structure programming operations schematic diagram according to another preferred embodiment of the present invention.Fig. 6 illustrate is a kind of P type channel transistor structure erase operation for use schematic diagram according to another preferred embodiment of the present invention.Fig. 7 illustrate is the section of structure according to the P type channel transistor structure that has two position memory functions in one embodiment of the present invention.
Please refer to Fig. 2, the present invention proposes a kind of method of operation of P type channel transistor structure, this P type channel transistor structure 201 for example is at least: substrate 200, in the grid in the substrate 200 220, charge trapping structure 210 between substrate 200 and grid 220, and the source/drain 230a and the source/drain 230b that are arranged in charge trapping structure 210 substrate on two sides 200.Wherein, charge trapping structure 210 is made of with top dielectric layer 206 end dielectric layer 202, charge immersing layer 204.
Please refer to Fig. 3, the method for operation of this P type channel transistor structure 201 applies bias voltage V in source/drain 230b when carrying out programming operations
PD, it for example is about-3～-4 volts; Source/drain 230a applies bias voltage V
PS, it for example is 0 volt; Grid 220 applies bias voltage V
PG, it for example is about-0.5～-1.5 volt; Substrate 200 applies bias voltage V
Psub, it for example is about 0～1 volt.Thus, electronics can be injected the charge trapping structure 210 of source/drain 230b side, to deposit first 240 in P type channel transistor structure 201, wherein, bias voltage V
PDLess than bias voltage V
PGWith the method for electronics iunjected charge immersal structure 210 can be that channel hot electron injects (Channel Hot Electron Injection) pattern.
Please refer to Fig. 4, when carrying out erase operation for use, apply bias voltage V in source/drain 230b
ED, it for example is about-3～-4 volts; Source/drain 230a applies bias voltage V
ES, it for example is 0 volt; Grid 220 applies bias voltage V
EG, it for example is about-2.5～-3.5 volts; Substrate 200 applies bias voltage V
Esub, it for example is about 2.8～3.4 volts.Wherein, bias voltage V
EGWith bias voltage V
EsubThe absolute value of voltage difference be less than or equal to 6 volts, bias voltage V
EDLess than bias voltage V
EG, and bias voltage V
EGLess than bias voltage V
PGAlong with bias voltage V
EsubRaising, the depletion region (Depletion Region) that is positioned at grid 220 belows can become broader, the intensity of electric field also can improve thereupon, thereby produces and to have more high-octane three hot holes.Utilize these three hot hole mechanism (Tertiary Hot Hole Mechanism) hot hole to be injected the charge trapping structure 210 of source/drain 230b side, hole and previous electronics mutually offset, and are therefore erased for first 240 that is stored in P type channel transistor structure 201.
Please refer to Fig. 5 and Fig. 6, can also carry out second 242 sequencing, the operation of erasing for P type channel transistor structure 201.It for example is when carrying out programming operations, applies bias voltage V in source/drain 230b
PS, for example be 0 volt; Source/drain 230a applies bias voltage V
PD, for example be about-3～-4 volts; Grid 220 applies bias voltage V
PG, for example be about-0.5～-1.5 volt; Substrate 200 applies bias voltage V
Psub, for example be about 0～1 volt, electronics is injected the charge trapping structure 210 of source/drain 230a side, to deposit second 242 in P type channel transistor structure 201.Wherein, bias voltage V
PDLess than bias voltage V
PGWith the method for electronics iunjected charge immersal structure 210 can be that channel hot electron injects (Channel Hot Electron Injection) pattern.
Please refer to Fig. 6, when carrying out erase operation for use, apply bias voltage V in source/drain 230a
ED, it for example is about-3～-4 volts; Source/drain 230b applies bias voltage V
ES, it for example is 0 volt; Grid 220 applies bias voltage V
EG, it for example is about-2.5～-3.5 volts; Substrate 200 applies bias voltage V
Esud, it for example is about 2.8～3.4 volts.Wherein, bias voltage V
EGWith bias voltage V
EsubThe absolute value of voltage difference be less than or equal to 6 volts, bias voltage V
EDLess than bias voltage V
EG, and bias voltage V
EGLess than bias voltage V
PGUtilize three hot hole mechanism that hot hole is injected the charge trapping structure 210 of source/drain 230b side, before deposit second 242 of P type channel transistor structure to erase in.The data of carrying out two in single memory cell write, erase.
In the foregoing description, because of adopting the operation that three times hot hole mechanism is erased, therefore required operating voltage is low, can save power consumption, shortens the running speed of memory.In addition, parallel electric field produces owing to applied three the hot hole mechanism of memory are based on, and therefore along with size of component is dwindled, more can promote its electrical performance, and help to improve the integrated level of element.
Please refer to Fig. 7, in one embodiment, the material of substrate 200 can be the substrate of P type.The material of grid 220 for example is a P type doped polycrystalline silicon.Charge trapping structure 210 is made of with top dielectric layer 206 end dielectric layer 202, charge immersing layer 204.Wherein, the material of end dielectric layer 202 for example is a silica, and the material of charge immersing layer 204 for example is a silicon nitride, and the material of top dielectric layer 206 for example is a silica.Aforesaid material constitutes P type channel silicon-silicon oxide/silicon nitride/silicon oxide-silicon (SONOS) memory 201.Wherein because its charge trapping structure 210 is the ONO layer, can be by the bias voltage that is applied on the source/drain 203a, the source/drain 203b that change grid 220 and its both sides, and have two groups of electronics, single group's electronics or do not have electronics in single silicon nitride layer (charge immersing layer 204).Therefore, this kind P type raceway groove SONOS memory 201 can write four kinds of states among single memory cell, is the non-volatility memorizer of two (2bits/cell) storages of a kind of single memory cell.
Therefore, the method for operation of above-mentioned P type raceway groove SONOS memory 201 can be the ONO layer (charge trapping structure 210) that electronics is injected source/drain 230b side, to deposit first 240 in.Utilize three hot hole mechanism that hot hole is injected the ONO layer (charge trapping structure 210) of source/drain 230b side afterwards, to erase first 240.
In addition, more can carry out second 242 sequencing and the operation of erasing to this P type raceway groove SONOS memory 201.For example be the ONO layer (charge trapping structure 210) that electronics is injected source/drain 230a side, to deposit second 242 in.Utilize three hot hole mechanism that hot hole is injected the ONO layer (charge trapping structure 210) of source/drain 230a side again, to erase second 242.
In addition, what deserves to be mentioned is that though the charge trapping structure 210 in the various embodiments described above and the diagram is that example explains with the ONO layer, yet end dielectric layer 202 and top dielectric layer 204 also can be other similar insulating material.The material of charge immersing layer 206 also is not limited to silicon nitride, also can be that other can make electric charge be absorbed in material wherein, for example tantalum oxide layer, strontium titanate layer and hafnium oxide layer etc.In addition, the material of grid 220 also is not limited to P type doped polycrystalline silicon, also can be metal, metal silicide or other suitable conductor material.
In sum, P type channel transistor structure of the present invention is because of adopting the operation that three times hot hole mechanism is erased, and required operating voltage is low, can save power consumption, improve the efficient of sequencing/erase, and then shorten the running speed of memory, and can promote its reliability.In addition, parallel electric field produces owing to applied three the hot hole mechanism of memory are based on, and therefore along with size of component is dwindled, more can promote its electrical performance, and help to improve the integrated level of element.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (21)
1. the method for operation of a P type channel transistor structure, this P type channel transistor structure comprises at least: a substrate; One grid is positioned in this substrate; One charge trapping structure is between this substrate and this grid; One first source/drain and one second source/drain are arranged in this substrate of these charge trapping structure both sides; And this method comprises:
When carrying out programming operations, electronics is injected this charge trapping structure of this first source/drain side, to deposit one first in this P type channel transistor structure; And
When carrying out erase operation for use, apply one first voltage in this second source/drain, this first source/drain applies one second voltage, this grid applies a tertiary voltage, this substrate applies one the 4th voltage, utilize three hot hole mechanism hot hole to be injected this charge trapping structure of this first source/drain side, before deposit this first of this P type channel transistor structure in to erase, wherein, the absolute value of the pressure reduction of this tertiary voltage and the 4th voltage is less than or equal to 6 volts, and this second voltage is less than this tertiary voltage.
2. the method for operation of P type channel transistor structure as claimed in claim 1, wherein this first voltage is 0 volt.
3. the method for operation of P type channel transistor structure as claimed in claim 1, wherein this second voltage is-3～-4 volts.
4. the method for operation of P type channel transistor structure as claimed in claim 1, wherein this tertiary voltage is-2.5～-3.5 volts.
5. as the method for operation of each described P type channel transistor structure of claim 1-4, wherein the 4th voltage is 2.8～3.4 volts.
6. the method for operation of P type channel transistor structure as claimed in claim 1, wherein when carrying out programming operations, also be included in this second source/drain and apply one the 5th voltage, this first source/drain applies one the 6th voltage, this grid applies one the 7th voltage, this substrate applies one the 8th voltage, electronics is injected this charge trapping structure of this first source/drain side, to deposit this first in this P type channel transistor structure, wherein, the 6th voltage is less than the 7th voltage, and the 7th voltage is greater than this tertiary voltage.
7. the method for operation of P type channel transistor structure as claimed in claim 6, wherein the 5th voltage is 0 volt.
8. the method for operation of P type channel transistor structure as claimed in claim 6, wherein the 6th voltage is-3～-4 volts.
9. the method for operation of P type channel transistor structure as claimed in claim 6, wherein the 7th voltage is-0.5～-1.5 volt.
10. the method for operation of P type channel transistor structure as claimed in claim 6, wherein the 8th voltage is 0～1 volt.
11. the method for operation of P type channel transistor structure as claimed in claim 6, the method for wherein electronics being injected this charge trapping structure comprises the channel hot electron injection way.
12. the method for operation of P type channel transistor structure as claimed in claim 6, wherein this method also comprises:
When carrying out programming operations, electronics is injected this charge trapping structure of this second source/drain side, to deposit one second in this P type channel transistor structure; And
When carrying out erase operation for use, apply this first voltage in this first source/drain, this second source/drain applies this second voltage, this grid applies this tertiary voltage, this substrate applies the 4th voltage, hot hole is injected this charge trapping structure of this second source/drain side, before deposit this second of this P type channel transistor structure to erase in.
13. the method for operation of P type channel transistor structure as claimed in claim 12, wherein when carrying out programming operations, also be included in this first source/drain and apply the 5th voltage, this second source/drain applies the 6th voltage, this grid applies the 7th voltage, this substrate applies the 8th voltage, electronics is injected this charge trapping structure of this second source/drain side, to deposit this second in this P type channel transistor structure.
14. the method for operation of P type channel transistor structure as claimed in claim 12, the method for wherein electronics being injected this charge trapping structure comprises the channel hot electron injection way.
15. the method for operation of P type channel transistor structure as claimed in claim 1, wherein this charge trapping structure comprises silicon oxide/silicon nitride/silicon oxide.
16. the method for operation of a P type channel transistor structure is applicable to a P type channel silicon-silicon oxide/silicon nitride/silicon oxide-silicon memory, this P type raceway groove SONOS memory comprises at least: a P type substrate; One ONO layer is positioned in this substrate; One P type doped polycrystalline silicon grid is positioned on this ONO layer; One first source/drain and one second source/drain be arranged in this substrate of these ONO layer both sides, and this method comprise:
When carrying out programming operations, apply one first voltage in this second source/drain, this first source/drain applies one second voltage, this P type doped polycrystalline silicon grid applies a tertiary voltage, this substrate applies one the 4th voltage, electronics is injected this ONO layer of this first source/drain side, to deposit one first in this P type raceway groove SONOS memory, wherein, this second voltage is less than this tertiary voltage; And
When carrying out erase operation for use, apply one the 5th voltage in this second source/drain, this first source/drain applies one the 6th voltage, this grid applies one the 7th voltage, this substrate applies one the 8th voltage, hot hole is injected this ONO layer of this first source/drain side to utilize three hot hole mechanism, before deposit this first of this P type raceway groove SONOS memory in to erase, wherein, the absolute value of the pressure reduction of the 7th voltage and the 8th voltage is less than or equal to 6 volts, the 6th voltage is less than the 7th voltage, and the 7th voltage is less than this tertiary voltage.
17. the method for operation of P type channel transistor structure as claimed in claim 16, wherein this method also comprises:
When carrying out programming operations, electronics is injected this ONO layer of this second source/drain side, to deposit one second in this P type raceway groove SONOS memory; And
When carrying out erase operation for use, apply the 5th voltage in this first source/drain, this second source/drain applies the 6th voltage, this grid applies the 7th voltage, this substrate applies the 8th voltage, hot hole is injected this ONO layer of this second source/drain side, before deposit this second of this P type raceway groove SONOS memory to erase in.
18. the method for operation of P type channel transistor structure as claimed in claim 17, wherein when carrying out programming operations, also be included in this first source/drain and apply this first voltage, this second source/drain applies this second voltage, this grid applies this tertiary voltage, this substrate applies the 4th voltage, electronics is injected this ONO layer of this second source/drain side, to deposit this second in this P type raceway groove SONOS memory.
19. the method for operation of P type channel transistor structure as claimed in claim 16, the method for wherein electronics being injected this charge trapping structure comprises the channel hot electron injection way.
20. the method for operation of P type channel transistor structure as claimed in claim 16, wherein this first voltage is that 0 volt, this second voltage are that-3～-4 volts, this tertiary voltage are that-0.5～-1.5 volt, the 5th voltage are that 0 volt, the 6th voltage are that-3～-4 volts, the 7th voltage are-2.5～-3.5 volts.
21. the method for operation of P type channel transistor structure as claimed in claim 16, wherein the 4th voltage is 0～1 volt, and the 8th voltage is 2.8～3.4 volts.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288943B1 (en) * | 2000-07-12 | 2001-09-11 | Taiwan Semiconductor Manufacturing Corporation | Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate |
| CN1407614A (en) * | 2001-08-22 | 2003-04-02 | 旺宏电子股份有限公司 | Operation of programmed and erasing P-channel SONOS memory unit |
| US6671209B2 (en) * | 2001-09-28 | 2003-12-30 | Macronix International Co., Ltd. | Erasing method for p-channel NROM |
| CN1577806A (en) * | 2003-06-27 | 2005-02-09 | 旺宏电子股份有限公司 | Non-volatile memory cell, and method for forming same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288943B1 (en) * | 2000-07-12 | 2001-09-11 | Taiwan Semiconductor Manufacturing Corporation | Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate |
| CN1407614A (en) * | 2001-08-22 | 2003-04-02 | 旺宏电子股份有限公司 | Operation of programmed and erasing P-channel SONOS memory unit |
| US6671209B2 (en) * | 2001-09-28 | 2003-12-30 | Macronix International Co., Ltd. | Erasing method for p-channel NROM |
| CN1577806A (en) * | 2003-06-27 | 2005-02-09 | 旺宏电子股份有限公司 | Non-volatile memory cell, and method for forming same |
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