CN100452057C - System and method for lithography simulation - Google Patents

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

Description

The system and method that is used for lithography simulation

Cross reference to relevant application

The application requires the right of priority of following application: U.S. Provisional Application sequence number 60/509,600, name is called " System and Method of Fast Lithography Simulation ", is filed on October 7th, 2003 (hereinafter referred to as " provisional application ").Content whole with this provisional application is incorporated into this by reference.

Background technology

The present invention relates to be used for measurement, inspection, characterization, emulation and/or estimate the system and the technology of the performance of offset printing (lithographic) system and technology; More specifically, relate to measurement, inspection, characterization, emulation and/or evaluation lithography system and the optical signature of treatment technology (for example system that in semiconductor manufacturing/processing environment, implements and technology) and the system and the technology of effect of being used on the one hand.

In brief, in semi-conductor industry, microplate printing (or abbreviating offset printing (lithography) as) is the technology that goes up printed circuit pattern at semiconductor wafer (for example silicon or GaAs wafer).At present, the optical flat printing is a used prevailing technology during a large amount of semiconductors are made.Such offset printing has utilized the light in can seeing the deep UV spectral range that the resist on the wafer is exposed.May utilize extreme ultraviolet line (EUV) and grenz ray future.After exposure, resist is developed with the output camegraph.

In the optical flat printing, at first use the direct writing tools of electron beam or laser beam to write photomask (often being called mask or graticule).The typical light mask that is used for the optical flat printing comprises six to eight inches glass (or quartzy) plate on a side, a surface-coated of this plate has the thin metal layer (for example chromium) of the about 100nm of thickness.Chip design is etched in this metal level, allow transmittance thus.The zone that does not etch away metal level hinders transmittance.In this way, can be to semiconductor wafer with graphic pattern projection.

Photomask comprises some pattern and the feature that is used for creating required circuit pattern on wafer.Be used for the instrument that mask images projects on the wafer is called ledex or scanner (hereinafter being referred to as " lithographic equipment ", " scanner " or " ledex ").With reference to Fig. 1, the schematic block diagram of the optical projection lithography system 10 of conventional ledex comprises light source 12, illumination pupil light filter 14, lens sub-system 16a-c, mask 18, projection pupil light filter 20 and wafer 22, and the aerial image of mask 18 (aerial image) projection is on this wafer 22.

With reference to Fig. 1, by background, light source 12 can be for example at the lasing light emitter of UV (ultraviolet ray) or DUV (deep UV) wavelength place work.Light beam had been expanded before inciding on the illumination pupil 14 and is mixed and disorderly.Illumination pupil 14 can be simple circular hole or have the custom-designed shape that is used for off-axis illumination.Off-axis illumination can comprise ring illumination for example (promptly this pupil is the ring that has through the interior and external radius of design), quadruple illumination (promptly having four openings in four quadrants of this pupil on the pupil plane) and to dipole other the similar shape of throwing light on.Fig. 2 A and Fig. 2 B illustrate exemplary annular and quadruple illumination respectively.

Continuation is with reference to Fig. 1, and after illumination pupil 14, light is by light optics spare (for example lens sub-system 16) and incide on the photomask (or mask) 18.Mask 18 comprises the circuit pattern by the imaging on wafer 22 of projection optics spare.Because the required pattern dimension on the wafer 22 becomes more and more littler, and pattern becomes close more and more mutually, has more challenge so lithography process becomes.In the effort that improves image quality, present treatment technology has utilized resolution enhance technology (" RET "), such as optical near-correction (" OPC "), phase shifting mask (" PSM "), off-axis illumination (" OAI "), condenser and outlet pupil light filter, and the technology of using multistage illumination (for example FLEX).

Many RET technology are used on mask 18 or are directly applied to mask 18.For example OPC and PSM, their revise light wave with the shortcoming of the imaging attribute of (1) compensation projection optics spare, and for example the OPC technology is used for compensating because the optical proximity effect that the interference of light causes; And/or (2) utilize the interference of light through design to come the Enhanced Imaging quality, for example the phase shifting mask technology is used for creating phase deviation between the adjacent patterns to strengthen resolution.

It should be noted that mask 18 may be because it self manufacturing process and not " perfection ".For example, may be not sharp keen and may be sphering in the turning on the mask 18; And/or live width may have a deviation with design load, wherein this deviation also may depend on the line width values and the adjacent patterns of design.These shortcomings on the mask 18 may influence final image quality.

Projection optics spare (for example lens sub-system 16b and 16c and projection pupil light filter 20) is imaged onto mask 18 on the wafer 22.In this, projection optics spare comprises projection pupil light filter 20.Pupil 20 has limited the maximum spatial frequency that can pass through the mask pattern of projection optical system.The numeral that is called " numerical aperture " or NA is usually with pupil 20 characterizations.Also proposed to revise the RET technology of pupil 20, be commonly referred to as pupil and filter.Pupil filters and can comprise for by the two the modulation of the amplitude on the light beam and phase place.

Because light wavelength is limited, and utilized, during imaging process, typically had the significant interference of light and diffraction than the current techniques that is printed on the bigger wavelength of minimum feature on the wafer 22.Imaging process is not that the perfection of the pattern on the mask 18 is duplicated.Current techniques has utilized physical theory to come this imaging process modeling.In addition, because the high NA value of current offset printing instrument, the different polarization of light provides different imaging attributes.To this technology modeling, can use model for more accurately based on vector.

Projection optics spare can be a diffraction limited.Yet the lens sub-system 16c in the projection optics spare is not " perfection " fully the most frequently.These shortcomings can be modeled as aberration, usually abstract some the undesirable phase modulation (PM) that turn to place, pupil plane of these aberrations, and usually by one group of Zernike coefficient representative.After light finally arrives the surface of wafer 22, they will be further with wafer 22 on coating (for example photoresist) interact.In this, different resist thickness, different resist optical properties (for example its refractive index) and the different material stacks (for example bottom anti-reflective coating or BARC) of resist below may further influence himself imaging features.In these effects some also can be come abstract by the modulation at place, pupil plane.

When resist by this image exposure and cure subsequently and when developing, resist trends towards standing complicated chemistry and physical change.First criterion and empirical model have been developed with these technologies of emulation.

In order to design and estimate the particular implementation of the mask that comprises mask enforcement RET, and the RET design that combines with ledex setting and feature of assessment has utilized Computer Simulation to imitate result expection and/or expectation for the influence of the printed patterns quality on the wafer.It should be noted that and developed physical model, comprise imaging path and the resist exposure and the development from the wafer epigraph that throws light on of mask manufacture, ledex for almost each step of lithography process.

At present, a large amount of computer software technologies at the lithography simulation demand are arranged.For example have based on the modeled simulation software of first criterion, this software carries out the concrete emulation of physics and chemical process, but operation very slowly and therefore is subject to minimum chip design area (number square micron level), for example from Sigma-C (Campbell, California, USA) " SOLID-C " and from KLA-Tencor (SanJose, California, " Prolith " USA).Although faster execution has been arranged and the computer software of simulation result is provided, such software has used the empirical model that is calibrated to experimental data (for example from Mentor-Graphics (Wilsonville, Oregon, " Calibre " USA)).Even for " fast " emulation of use experience model, the emulation of full chip-scale usually still needs tens of hours to many days.

And, in order to understand, design, analyze and/or estimate lithography process more completely, should maybe may need to analyze and/or emulation from the mask that throws light on to the whole technology that is imaged onto resist.Because calculating, complicated model and a large amount of design datas (VLSI design data of today can reach the every number of plies ten GB), the rough power on the general purpose microprocessor trend towards being difficult to handling and expending time in.In addition, utilize the mainframe computer of hyperspecialization may require a large amount of investments, make that thus this technology is uneconomical.

There is demand for such system and technology, this system and technology have been quickened the optical signature of lithography system and treatment technology and/or attribute and effect and/or interactional lithography simulation, inspection, characterization and/or evaluation, and it has overcome one, some or all defectives of conventional system and method.There is demand for such system and technology, this system and technology promote checking, characterization and/or the inspection to the RET design, and this RET design comprises that the concrete emulation of whole lithography process is so that checking RET design realizes and/or provide required result on final wafer pattern.

And, there is demand for such system and technology, the emulation apace of this system and technology, characterization, inspection, checking and/or realize the RET design and photolithography equipment optimization and technology (critical dimension (" CD " for example, be the live width of critical line in the integrated circuit (IC) design), line end pull back, one, one of some or each position, the edge placement error of some or each pattern, and/or for the printing sensitivity such as the process variations of mask error, focusing, dosage, numerical aperture, illumination aperture and/or aberration).

Summary of the invention

Here description and figure are shown with many inventions.In one aspect, the present invention is a kind of system and method, and this system and method has quickened the optical signature of lithography system and treatment technology and/or attribute and effect and/or interactional lithography simulation, inspection, characterization and/or evaluation.First main aspect in, the present invention is a kind of system and method that emulation is carried out in the offset printing design that comprises a plurality of polygons (can or can not comprise one or more resolution enhance technology) of arranging with predetermined configurations of being used for.The system of this aspect of the present invention comprises microprocessor subsystem, represent a plurality of polygons are converted to its bitmap based on pixel (multi-level images for example, such as 2,4,8 ... 64,128,256 or gray level).Should comprise pixel data based on the bitmap of pixel, wherein each pixel data has been represented the pixel with intended pixel size.

This system further comprises the accelerator subsystems that is coupled to microprocessor subsystem, represents to calculate at least a portion of the aerial image of offset printing design in order to the bitmap based on pixel that uses the offset printing design.Accelerator subsystems comprises a plurality of programmable gate arrays that are configured to this pixel data of parallel processing.

In one embodiment, Pixel Dimensions can be greater than the Nyquist frequency in the aerial image of offset printing design, and/or uses the numerical aperture and the wavelength of the projection optics spare of offset printing instrument to determine.

In another embodiment, this system comprises a plurality of accelerator subsystems, and each accelerator subsystems is coupled to microprocessor subsystem and is provided with a part based on the bitmap of pixel.Each accelerator subsystems uses related with it pixel data to calculate the aerial image that designs with the corresponding offset printing based on the part of the bitmap of pixel.Each of a plurality of accelerator subsystems uses pixel data to carry out fast fourier transform in one embodiment, to generate the counterpart of aerial image.Microprocessor subsystem that it should be noted that these embodiment can comprise a plurality of microprocessors, and wherein each microprocessor is coupled at least one related accelerator subsystems.

This accelerator subsystems also can be used the bitmap based on pixel of offset printing design to represent and represent the projection of offset printing instrument and the matrix of coefficients of light optics spare, calculates the aerial image in the resist that forms on the wafer.

This accelerator subsystems can be used the bitmap based on pixel of this offset printing design to represent and represent the projection of offset printing instrument and the matrix of coefficients of light optics spare, calculates the pattern that is formed on wafer by this offset printing design.

System of the present invention also can comprise the disposal system that is coupled to microprocessor subsystem and accelerator subsystems, in order to pattern that is calculated on the wafer and required predetermined pattern are made comparisons.This disposal system can additionally or replace the CD that its (1) determines the offset printing design, (2) in response to pattern that is calculated on the wafer and the comparison between required/predetermined pattern, detect the error in the offset printing design, and/or (3) use the pattern that is calculated on the wafer to determine the edge placement that offset printing designs.It should be noted that the correction that this disposal system can be determined offset printing is designed is to proofread and correct the error in the offset printing design in response to detecting this error.

And this disposal system can use the pattern on the wafer to determine printing sensitivity, and this sensitivity is in response to that the coefficient of the matrix that changes the projection represent the offset printing instrument and light optics spare calculates.Represent the coefficient of the matrix of the projection of offset printing instrument and light optics spare can represent one or more in focusing, dosage, numerical aperture, illumination aperture and the aberration.In fact, this disposal system can use this printing sensitivity to determine the projection of offset printing instrument and one group of parameter of light optics spare.

In aspect another is main, the present invention is a kind of system and method that emulation is carried out in offset printing design (comprising a plurality of polygons (it can comprise or can not comprise resolution enhance technology) of arranging with predetermined configurations) of being used for.This system comprises microprocessor subsystem, and it comprises a plurality of microprocessors, represent in order to offset printing design is converted to its bitmap based on pixel (multi-level images for example, such as 2,4,8...64,128,256 or gray level).Should comprise pixel data based on bitmap of pixel, wherein each pixel data has been represented pixel with intended pixel size (for example use that the numerical aperture of projection optics spare of offset printing instrument and wavelength are determined and/or greater than the Nyquist frequency in the aerial image of this offset printing design).

This system further comprises a plurality of accelerator subsystems, and wherein each accelerator subsystems comprises a plurality of programmable integrated circuits that are configured to the parallel processing pixel data.In addition, each accelerator subsystems is connected to related microprocessor, in order to the counterpart that the bitmap based on pixel that uses the offset printing design is represented, calculates the part of the aerial image of offset printing design.In certain embodiments, each accelerator subsystems uses pixel data to carry out fast fourier transform, to generate the counterpart of aerial image.

A plurality of accelerator subsystems are used the bitmap based on pixel of offset printing design to represent in one embodiment and are represented the projection of offset printing instrument and the matrix of coefficients of light optics spare, calculate the aerial image in the resist that is formed on wafer by the offset printing design.In another embodiment, accelerator subsystems is used the bitmap based on pixel of offset printing design to represent and is represented the projection of offset printing instrument and the matrix of coefficients of light optics spare, calculates the pattern that is formed on wafer by the offset printing design.

This system may further include the disposal system that is coupled to microprocessor subsystem and accelerator subsystems, in order to: (1) makes comparisons the pattern that is calculated on the wafer and required/predetermined pattern, and/or (2) use the pattern that is calculated on the wafer to determine the CD that offset printing designs, and/or (3) use the pattern that is calculated on the wafer to determine the edge placement that offset printing designs, and/or (4) use the pattern on the wafer calculated to determine printing sensitivity, and this sensitivity is in response to coefficient (for example focusing of projection and light optics spare that the matrix of the projection of offset printing instrument and light optics spare is represented in change, dosage, numerical aperture, one or more in illumination aperture and the aberration) calculate.In fact, this processing can use printing sensitivity to determine the projection of offset printing instrument and one group of parameter of light optics spare.

And, this disposal system can (additionally or replace it) in response to the comparison between pattern that is calculated on the wafer and the required predetermined pattern, detect the error in the offset printing design.In response to detecting this error, the correction that this disposal system is determined offset printing is designed is to proofread and correct the error in this offset printing design.

Again, description and figure are shown with many inventions here.The not exhaustive scope of the present invention of this summary of the invention.And this summary of the invention is not intended to limit the present invention, and should not understand in this mode.Although in this summary of the invention, described some embodiment of the present invention, feature, attribute and advantage, but should be appreciated that many other and different and/or similar embodiment, feature, attribute and/or advantage of the present invention are tangible according to following description, diagram and claims.

Description of drawings

In following specific descriptions process, will carry out reference to accompanying drawing.These illustrate different aspect of the present invention, and in suitable part, have marked label similarly, and these labels have shown similar structure, parts, material and/or unit at different picture in pictures.It should be understood that except that illustrating especially, the various combinations of structure, parts, material and/or unit be can conceive and fall within the scope of the present invention.

Fig. 1 be have the stepping of (hereinafter being called ledex) of dioptrics part-and-repeat or stepping-and-the schematically showing of light path in the scanning optical lithography system.This mask comprises the circuit pattern by the imaging on wafer of reduction lens combination;

Fig. 2 A and 2B illustrate exemplary conventional annular and quadruple illumination pupil respectively;

Fig. 3 is the schematic block diagram of lithography simulation system of some embodiment of some aspect according to the present invention;

Fig. 4 is the process flow diagram of the simulation process of some embodiment of some aspect according to the present invention;

Fig. 5 is the schematic block diagram of lithography simulation system of some embodiment of some aspect according to the present invention;

Fig. 6 is the schematic block diagram according to the accelerator subsystems framework of Fig. 5 of certain embodiments of the invention; And

Fig. 7 is the process flow diagram of D:T checking process of some embodiment of some aspect according to the present invention.

Embodiment

Here description and figure are shown with many inventions.In one aspect, present invention is directed at a kind of technology and system, this technology and system are used for emulation, checking, inspection, characterization, determine and/or estimate offset printing design, technology and/or system and/or independent function or the wherein used parts carried out thus.In one embodiment, the present invention is such system and method, and this system and method has quickened optical signature and/or attribute and effect and/or interactional lithography simulation, inspection, characterization and/or the evaluation of lithography system and treatment technology.In this, in one embodiment, the present invention utilizes a kind of lithography simulation system architecture that comprises dedicated hardware accelerators and a kind of acceleration and promotes for example treatment technology of checking, characterization and/or the inspection of RET design of mask design, comprise the concrete emulation and the characterization of whole lithography process, on final wafer pattern, realize and/or provide required result to verify this design.This system comprises: (1) one or more general-purpose computations devices, in data processing, have branch and complementary logic in order to carry out based on example, and (2) accelerator system, in order to carry out most computation-intensive tasks.

Specifically, with reference to Fig. 3, in one embodiment, one or more universal calculation elements 112 programmings and/or be configured to the task management of the integrated operation of disposal system 110, comprise and for example divide design database, be used for analysis and conversion by accelerator system 116.In addition, one or more universal calculation elements 112 promote mutual with user or operator (i.e. " external world ") via for example one or more client computers (not shown), this client computers provides visit to system 110 to operator or user, is used for operation setting and/or result's review/analysis.

Continuation is with reference to Fig. 3, and accelerator system 116 can be programmed for execution and have branch and complementary logic based on example in data processing.In this, accelerator system 116 comprises microprocessor subsystem, is typical polygon (or analog) pattern in order to handle and to handle for conventional lithography simulation and design system/technology.Because many polygons are arranged in modular design, and many different polygon type and examples are arranged, so system 110 utilize the microprocessor subsystem of accelerator system 116 implement in order to handle logic based on example (for example " if this case, then; Else if, then; And so on ") program or routine.

Accelerator system 116 further suitably comprises the accelerator subsystems (comprising dedicated hardware accelerators) through programming and configuration that is coupled to microprocessor subsystem, in order to carry out Flame Image Process based on the pixel grayscale image emulation of pixel (for example based on).Can comprise calculating based on pixel, for example filtration, mapping again, Fourier transform or other type conversion based on the Flame Image Process of pixel.In these calculating based on pixel, interdepending of data is minimized--and this has promoted to implement parallel and pipeline calculating.

With reference to Fig. 4, in one embodiment of the invention, lithography simulation, inspection, characterization and/or evaluation procedure comprise the lithography simulation based on pixel.In design database those examples based on polygon or analog, system 110 will convert one or more images based on pixel (seeing square frame 120 and 122) to based on polygonal database (comprising particular design).Have many technology be used for polygon (or analog) convert to multi-level images (for example 2,4,8 ... 64,128,256 or grayscale image).No matter all such technology are now known or later exploitation, all will fall within the scope of the present invention.For example, a kind of conversion method comprises two main processes:

(1) use scan-line process or technology to fill the sub-pixel binary bitmap.Sub-pixel size may be selected to be the mark of final Pixel Dimensions, and for example 1/8 of pixel.For each sub-pixel, if sub-pixel is in polygon, then sub-pixel is filled with 1, otherwise fills with 0.More complicated technology comprises shake, it can increase fills resolution and does not but reduce sub-pixel size, if but some adjacent subpixels on the polygon edge (therefore both not exclusively polygon with interior also not exclusively beyond polygon) then some sub-pixels are filled to 1 and other sub-pixel is filled to 0.Shake is the computer graphics techniques of standard; And/or

(2) anti-aliasing (anti-aliasing) filter application being arrived the sub-pixel binary bitmap, is the multi-level images (for example grayscale image) of Pixel Dimensions simultaneously with the bitmap images down-sampling.Antialiasing filter is a kind of standard technique in the Flame Image Process, is used for the spatial frequency band of before down-sampling limited images to avoid aliasing.The design of antialiasing filter need minimize the frequency content that will go back in the frequency band after down-sampling.

Use to the conversion of gray level image one of these two kinds of technology showing advantage and be then polygon to be overlapped automatically to handle at polygon.That is to say, when the overlapping of polygonized structure, sub-pixel when it is arranged in the overlapping zone by twice filling with 1 (if perhaps this overlapping comprise more than two polygon repeatedly " filling " with 1), final value of filling is still 1.Therefore, any overlapping is resolved in transfer process automatically.

Important decision in this image transitions step is the selection of Pixel Dimensions.In this, implementing big Pixel Dimensions may cause in the downstream or desired less calculated amount and the bigger Flame Image Process error of bringing out in aftertreatment.In one embodiment, Pixel Dimensions is chosen as and makes it aloft the Nyquist frequency in the image is above to image sampling.Well-knownly in optical flat printing science be, illumination, partial coherence and/or the RET (for example OPC and PSM) on the mask no matter, maximum spatial frequency in the light intensity distributions on the wafer plane is characterized as 2 * NA/ λ, wherein NA is the numerical aperture of ledex projection optics spare, and λ is a wavelength used in imaging.Be well known that also that in Flame Image Process if sample frequency is more than the twice of the maximum spatial frequency that exists, then the people can be from accurate reconstituting initial image through the image of sampling in original image.This is known as the Nyquist theory, and the maximum existing spatial frequency in 2 * original image then is called the Nyquist frequency.Therefore, utilize this relation, for the aerial image in the ledex, the Nyquist sampling rate is 4 * NA/ λ.Equally, Pixel Dimensions can be p=λ/(4 * NA) or littler.For example, for wavelength and the NA=0.65 of 193nm, Pixel Dimensions p can be 74nm or littler.For wavelength and the NA=0.65 of 248nm, Pixel Dimensions p can be 95nm or littler.

Should be noted that it is in the aerial image level of wafer that above-mentioned Pixel Dimensions is selected.Some ledex is being implemented the picture size reduction when mask is imaged onto wafer, and can adjust the Pixel Dimensions on the mask.For example, if the ledex scalage be 4 *, then the Nyquist sampled pixel size on the mask than on the wafer big by 4 *.Therefore, under these environment, can adjust the sampled pixel size.

The grayscale image based on pixel through conversion has been represented mask.Mask RET (for example OPC and PSM) can merge in this image, because the RET characteristic part in polygon data storehouse typically.For example, in the OPC situation, modify (decoration) extra typically polygon, so they automatically become the part of grayscale image.In the situation of PSM, if two types phase place " 0 " and " 180 " degree are only arranged, then sub-pixel bitmaps polygon to transition period of bitmap in 180 degree phase regions, fill with " 1 " and final grayscale image will comprise positive and negative values the two.In fact, when PSM comprised the phase differential that just exceeds 0 and 180 degree, bitmap values can comprise corresponding phase factor, and grayscale image also can be made of plural number, and wherein plural number comprises real part and imaginary part.

As mentioned above, design database (being made of polygon or analog) is carried out and/or is finished by the microprocessor subsystem of accelerator system 116 to the conversion of one or more images based on pixel (seeing square frame 120 and 122).

In one embodiment, can implement anti-aliasing filtering technique (seeing square frame 122).That is to say, because anti-aliasing filtration may be embodied as linear operation, so different phase layers can convert binary bitmap individually to, then convert multi-level images (for example grayscale image) to, then multiply each other, then obtained to have the final multi-level images (for example grayscale image) of plural pixel value mutually with their independent phase factors.Anti-aliasing filtering technique (square frame 122) can use the binary bitmap image (output of square frame 120) of polygon design database to be carried out and/or finished by accelerator system 116 in one embodiment.

Continuation is with reference to Fig. 4, and after design database converted grayscale image to, in one embodiment, this image can be applicable to handle so that the systematic mask errors modeling (is seen square frame 124) in image.For example, common mask error comprises by deviation that shortcoming caused and turning sphering in the mask-making technology of for example electron beam proximity effect and resist development.The turning sphering is meant the fact (for example being caused by finite size and the resist development low-pass effect of writing the bundle point) of the not sharp keen but sphering in the turning on the mask, and can come modeling by introducing edge sphering effects for all turnings, sharp-pointed 90 degree that for example use 1/4th circle to replace two straight flanges intersect.

Deviation is meant poor (this for example may be developed or underdevelop causing by crossing of resist) between actual linewidth and the design load.It should be noted that this difference may depend on line width values and the adjacent patterns (for example being caused by the electron beam proximity effect) through design.Deviation usually can be utilized expansion or erosion value, comes modeling by the gray-scale morphological operations on the image, and this expansion or erosion value depend on the neighborhood of the size of pattern and pattern to include proximity effect in consideration.These technology are well-known for the technician of image processing field.

It should be noted that mask error modeling function (square frame 124) can be optionally, as represented with dashed-lines format.The final effect on the wafer that mask error causes for example, utilizing high-quality technology to make in those examples of mask, owing to can be ignored.Therefore, need not to implement this mask error modeling.

In addition, mask error modeling function (square frame 124) can for example use as mentioned above the bitmap images of polygon design database to carry out and/or finish by the accelerator subsystems of accelerator system 116 in one embodiment.

Continuation is with reference to Fig. 4, and next process is to air-borne imagery path modeling (seeing square frame 126) process projection optics spare and under the illumination mechanism through designing.This physics imaging model is set up in the optics science well, can use scalar or vector imaging model.Because high NA system (high NA refers generally to the NA greater than 0.6) is shifted in the optical flat printing, it is more important that arrow pattern is just becoming.In the past decade, various technology have been developed in order to speed-up computation.

An example is that total imaging system is decomposed into a series of coherence imaging systems, this serial system has the importance of reduction, the more and more littler eigenvalue that promptly is called the matrix of transmission interaction coefficent (TCC), described matrix are to limit the matrix that still is independent of mask pattern itself by projection and light optics spare.Coherent system through decomposing usually is called the intrinsic system.Depend on the accuracy requirement, can comprise the intrinsic system of various numbers.Most aerial image calculation can utilize forward and fast Fourier transform (FFT) backward generates aerial image.Because the coherent optics imaging system of diffraction limited can easily be characterized as a series of Fourier transforms, so the aerial image that utilizes FFT to generate design can be favourable.All these conversion can be the calculating based on pixel of rule on being applied to based on the image of pixel the time.

In addition, aerial image generation (square frame 126) can for example use the bitmap images of the polygon design database of being revised by additional treatments (for example anti-aliasing filtering technique 122 and/or mask error modeling 124) (if there is) to carry out and/or finish by accelerator subsystems 116 in one embodiment.

During the image generation/calculating aloft 126, the wafer surface resist piles up parameter (for example thickness, BARC and/or refractive index) and can merge in the TCC equation.Also can merge various non-mask RET technology, for example off-axis illumination and pupil filter, as the part of TCC accounting equation.In addition, the shortcoming in the optical element, for example aberration and/or light scattering also can merge in the air-borne imagery equation by correspondingly revising pupil according to desirable example.

Continuation is with reference to Fig. 4, and the aerial image in the resist is responsible for making resist exposure itself.For the first criterion modeling (being resist emulation 128) of strictness, can utilize the 3D intensity distributions of the aerial image in the resist.For some embodiment of resist modeling, can utilize an aerial image distribution of the 2D on the plane, for example the aerial image of certain distance of wafer surface top.Utilize aerial image as calculated, can use many different resist models.The resist model carries out emulation and/or modeling and estimates final resist marginal position and/or resist profile through developing physics and chemical process.It should be noted that no matter model and modeling technique that all are such are now known or later exploitation, all will fall within the scope of the invention.

In one embodiment, marginal position and/or edge contour can be made comparisons with the SEM image of for example being measured by metering outfit (for example CD-SEM, optics CD instrument), the experimental result of CD value, with checking and calibration resist model parameter.

It should be noted that the resist modeling can be reduced to the calculating based on pixel of rule, for example filter, shine upon again, and therefore be suitable for hardware-accelerated.Equally, resist modeling or emulation (square frame 128) can for example directly be used the binary bitmap image (seeing square frame 120) of polygon design database or used the bitmap images of the polygon design database of being revised by additional treatments (for example anti-aliasing filtering technique 122 and/or mask error modeling 124) or directly the aerial image (seeing square frame 126) that generates is thus carried out and/or finished in one embodiment by accelerator subsystems 116.

Same next operation in frame of broken lines shown in Figure 4 is the modeling (seeing square frame 130) of substrate etch process.This operate in present lithography simulation and/or analyze in usually be unnecessary because etch process can be considered as separating with offset printing and technology independently.Yet etch process can merge among the present invention.

The emulation of substrate etch process also can taper to the processing based on pixel.Equally, etch process emulation (square frame 130) can for example directly be used the binary bitmap image (seeing square frame 120) of polygon design database or used the bitmap images of the polygon design database of being revised by additional treatments (for example anti-aliasing filtering technique 122, mask error modeling 124 and/or resist emulation 128) or directly the aerial image (seeing square frame 126) that generates is thus carried out and/or finished in one embodiment by accelerator subsystems 116.

Continuation is with reference to Fig. 4, determine and/or the marginal position of identification design after, can determine, inspection, characterization and/or estimate printed patterns (seeing square frame 132) on the wafer.By connecting the marginal point through identification, structure is through the wafer pattern of emulation.The wafer pattern of these expectations can be used for various application, for example compare with design object (being the required pattern on the wafer), with checking RET design really in purpose that realizes it and generated error not.The discussion of various and/or suitable application (square frame 134) is provided below particularly.

In one embodiment of the invention, hardware-accelerated finger uses the technology of hardware (electron plate that for example comprises computing engines, computing chip and/or storer), and this hardware is for more efficient than the calculation element based on universal microprocessor for the calculating of type of pixel.This accelerator hardware can utilize the universal calculation element (for example general purpose microprocessor and/or programmable logic device (PLD)) with dedicated programmed of high configuration to implement, and equally from the important computation process of microprocessor unloading.In this way, emulated data is calculated with more parallel and mode pipelineization by this system.

For example, with reference to Fig. 3, in one embodiment, the microprocessor subsystem of accelerator system 116 can be handled those calculating that depend critically upon based on the logic of example, for example polygon is converted to its bitmap and represents, and those calculating of the accelerator subsystems of accelerator system 116 less for having (or almost not having) data interdependent property are handled.Equally, in this configuration, the computation-intensive task of being carried out by accelerator subsystems can pipelined fashion parallelization and calculating, and for example image filtering (square frame 122 of Fig. 4), image transformation are such as Fourier transform (square frame 126 of Fig. 4) and/or resist modeling/emulation (square frame 128 of Fig. 4).

With reference to Fig. 5, in one embodiment, system 110 comprises one or more universal computing systems 112, for example application processing system 114a and front-end processing system 114b.Application processing system 114a suitably is configured to the task management of the integrated operation of disposal system 110.Specifically, in one embodiment, application processing system 114a comprises application treating apparatus 136 and uses SCSI RAID 138a.Use treating apparatus 136 management that provides the various operation of components of system 110 suitably is provided.In this, for example use treating apparatus 136 and can be programmed at the various parts of accelerator system 116 and divide design databases, specify separate operaton, function or the process carried out by the parts of accelerator system 116 thus.SCSI RAID hard disk array 138a provides storage for using treating apparatus 136 used program and data (for example design database).

Front-end processing system 114b comprises front end processing device 140, this device 140 suitably is programmed for via for example one or more client computers (not shown) and handles or execution and user or operator (i.e. " external world ") directly mutual, this client computers provides visit to system 110 to operator or user, is used for operation foundation and/or result's review/analysis.The SCSIRAID hard disk array 138b that is associated with front end processing device should be a high capacity storage device, because hard disk array 138b is used for storing the result and the image of many emulation jobs.Front-end processing system 114b also communicates by letter with application processing system 114a, with to or provide or fetch data from using SCSI RAID 138a (for example design database), and as indicated in user or the operator, indicate application processing system 114a to begin operation.

Continuation is with reference to Fig. 5, and application processing system 114a for example passes through high speed switch (for example gigabit-Ethernet switch 142a and 142b) with front-end processing system 114b and is connected with accelerator system 116.Switch 142a and 142b can be by Dell Computer (Austin, Texas, USA) the DELL 5224Power Connect that makes and provide.The enforcement of DELL 5224Power Connect and operate in concrete description is arranged in application note, technology/journal of writings and the tables of data all is incorporated into this with them by reference.

In one embodiment, all or all substantially actual computation intensive task can and particularly be to be undertaken by one or more accelerator components 116a-n by accelerator system 116.This framework of the present invention is realized scalable calculated capacity by the number that changes accelerator hardware component 116a-n.And this framework is also realized and has been strengthened the whole fault-tolerant of system.For example, suppose that given accelerator hardware component 116a-n lost efficacy, its operation can be redistributed to other accelerator hardware component 116a-n, and in this way, system 110 keeps its operational condition/state.

Specifically, accelerator system 116 can comprise one or more accelerator components 116a-n, this locality or resident memory storage 148a-n that each parts has among the microprocessor subsystem 144a-n (comprising one or more microprocessors) one, one or more accelerator subsystems 146a-n and is coupled to related microprocessor subsystem 144a-n.The degree of hardware-accelerated ability or amount can depend on the degree or the amount of pending calculating and come balanced mutually with microprocessor subsystem 144a-n.

In one embodiment, microprocessor subsystem 144a-n each comprise (Santa Clara, California, USA) two Xeon microprocessors of Zhi Zaoing by Intel.Each comprises a plurality of special ICs (ASIC), special DSP integrated circuit and/or programmable gate array (for example field programmable gate array (" FPGA ")) accelerator subsystems 146a-n.In fact, each accelerator subsystems 146a-n can comprise a plurality of accelerator subsystems, and for example accelerator subsystems 146a can comprise all accelerator subsystems 146a1-146ax, as shown in Figure 5.In this way, when fully utilizing, each among the accelerator subsystems 146a-n comprises the roughly calculated capacity of 25 Xeon microprocessors.

Bus 150a-n has promoted the high-speed communication between microprocessor subsystem 144a-n and the related one or more accelerator subsystems 146a-n.Communication protocol on the bus 150a-n and technology can be PCI, PCIX or other high-speed communication protocol and technology.In fact, no matter any high speed technology is now known or later exploitation, can implement on bus 150a-n.It should be noted that in one embodiment bus interface can use that (21P100BGC PCI-X bridge (64bit/133MHz) USA) is implemented for Armonk, New York from International Business MachinesCorporation.The enforcement of 21P100BGC and operate in concrete description is arranged in application note, technology/journal of writings and the tables of data all is incorporated into this with them by reference.

With reference to Fig. 6, in one embodiment, each accelerator subsystems 146a-n comprises a plurality of programming logic integrated circuit 152a-x, for example be coupled to related high-speed memory 154a-x (for example DDR SDRAM, MT46V2M32V1 via bus (for example 64bit/266MHz), from Boise, Idaho, the Micron Technologies of USA) high-end FPGA.In one embodiment, implemented four FPGA, each FPGA comprises 300 ten thousand doors.FPGA can be by Xilinx (San Jose, California, USA) XC2V3000 of Zhi Zaoing.The enforcement of XC2V3000 and operate in concrete description is arranged in application note, technology/journal of writings and the tables of data all is incorporated into this with them by reference.

FPGA (Field Programmable Gate Array) 152a-x suitably programmes and is configured to carry out all or all have the complementary calculating of less (or almost not having) data substantially, and for example anti-aliasing filtering technique (square frame 122 of Fig. 4), mask error modeling (square frame 124 of Fig. 4), aerial image generate (square frame 126 of Fig. 4), resist emulation (square frame 128 of Fig. 4) and/or wafer pattern and generate and handle (square frame 132 of Fig. 4).Like this, do not adopt FPGA (Field Programmable Gate Array) 152a-x to handle to depend critically upon based on those tasks of the logic of example for example polygon to the conversion (square frame 120 of Fig. 4) of binary bitmap.

Continuation is with reference to Fig. 6, each accelerator subsystems 146a-n further comprises FPGA (Field Programmable Gate Array) 156, for example be coupled to related nonvolatile memory 158 (for example from Intel (Santa Clara, California, flash memory TE28F128J3A-150 USA)) CPLD (" CPLD ").In one embodiment, CPLD can be by Xilinx (San Jose, California, USA) XCR3384XL-10TQ144 of Zhi Zaoing.In brief, CPLD is used for by sending from the FPGA of FLASH code to come FPGA is programmed.The enforcement of XCR3384XL-10TQ144 and operate in concrete description is arranged in application note, technology/journal of writings and the tables of data all is incorporated into this with them by reference.

In one embodiment, can by or comprise the thresholding operation of for example anti-aliasing filtration and down-sampling, the FFT that is used for aerial image calculation, image filtering and/or resist modeling by the calculating that accelerator subsystems 146a-n carries out.Can be comprised by the calculating that microprocessor subsystem 144a-n handles: polygon is to conversion, application program or the process (for example RET checking that merges by comparison, defective) of binary bitmap.The division of calculation task between microprocessor subsystem 144a-n and accelerator subsystems 146a-n depends on application, and can use or from the operation to the operation and change from being applied to.The division of optimizing be between accelerator subsystems 146a-n and microprocessor subsystem 144a-n balanced computing time, thereby two subsystems can not spend the result of plenty of time wait from other subsystem.

In one embodiment, the parts of system 100 comprise application processing system 114a, front-end processing system 114b and accelerator system 116, can be installed as frame installing type system together.

System 110 can carry out optical signature and/or attribute and effect and/or interactional quick lithography simulation, inspection, characterization and/or the evaluation of lithography system and treatment technology.System 110 can utilize in many application, the checking of for example offset printing design, technology and/or system, inspection, characterization and/or evaluation, and/or the independent function carried out thus or used unit wherein.Some kinds in these application have been listed and have described below.Should be noted that this list of application is not an exhaustive.In fact, during all of lithography simulation, inspection, characterization and/or evaluation that system 110 can be used for depending on semiconductor design and/or manufacturing are used, and no matter all application are now known or later exploitation like this, all will drop in the present invention.

In an application, can implementation system 110, be used for quick RET checking, inspection and/or characterization.The RET checking can refer to such process, and this process is used the concrete emulation of whole lithography process is verified that the RET design realizes required, expection and/or acceptable result in final wafer pattern.Required on the wafer 22, expection and/or acceptable result is the part of design database normally, is sometimes referred to as reference layer or design object layer.Back RET design database also is the part of design database.Obtain after the wafer pattern of emulation at RET design database after the use, wafer pattern can be made comparisons with reference layer, then can give prominence to, characterization and/or analysis depart from.

In addition, interlayer characterization and/or analysis can be used for determining overlapping nargin.For example, the overlapping between contact and polysilicon (poly) layer is crucial in IC makes.Very few or too small overlapping may cause lower chip yield.The present invention for example can be used for analyzing by the chip resist pattern of relatively their corresponding emulation the amount of the overlapping nargin between two relevant or irrelative layer.Place or position that it should be noted that the too small place of nargin can be given prominence to, for example in order to more specifically to analyze.

Use that the present invention comes that the speed of emulation and/or characterization RET design makes that the RET checking can be in process window one, some or all of difference (promptly focus on and exposure dose in acceptable lithography process change) locate to carry out.Although RET design some or the set point place in process window (combination of dosage and focusing) may be acceptable, its other some place in process window may produce excessive departing from.Therefore, more thorough and RET design verification exhaustive comprises the analysis and/or the emulation of being had a few in the lithography process window.

It should be noted that the present invention can be extended to process window comprises and focuses on and dosage many other technological parameters in addition for example illumination, mask error, ledex aberration and/or resist thickness.In this case, process window becomes the volume of super dimension space.

Except edge placement, line end layout, line disconnection/bridge joint, CD error and/or any other error of determining by the marginal position on the wafer, the present invention can be used for analyzing the printing sensitivity of wafer pattern for process variations, and these process variations for example are mask error, focusing, dosage, numerical aperture, illumination aperture, aberration or other technological parameter.This printing sensitivity refers to the derivative that the wafer pattern error changes technological parameter.This analysis can realize by introduce little change in technological parameter, and analyze consequent wafer pattern feature.Sensitivity is high more, and the robustness of design is poor more.

For example, in the situation of CD sensitivity, the present invention can be used for being analyzed as follows derivative, and these derivatives are as the sensitivity of CD to those corresponding technological parameters:

·dCD_on_wafer/dCD_error_on_mask。Wherein " d " instructs number.This specific sensitivity is " CD_on-wafer " derivative to " CD_error_on_mask ", promptly for the unit change amount in " CD_error_on_mask ", the change amount in " CD_on_wafer ".This sensitivity usually is called MEEF, i.e. the mask error enhancer.Can use two sub-examples:

ο overall situation mask error MEEF.In the case, the deviation to some extent simultaneously of all patterns on the mask.This sensitivity is relevant with the mask misalignment change of striding mask.

The local mask error MEEF of ο.In the case, only single local pattern is assumed to and has the CD error on the mask.This sensitivity is relevant with defects on mask.

DCD/dFocus_of_stepper, the i.e. sensitivity that CD focuses on ledex on the wafer.

DCD/dDose_of_stepper, promptly on the wafer CD to the sensitivity of ledex exposure dose.

DCD/dAberration_of_stepper, promptly on the wafer CD to the sensitivity of ledex aberration.

DCD/dlllumination_pupil_of_stepper, promptly on the wafer CD to the throw light on sensitivity of pupil (for example its size and dimension, and pupil in illumination profile) of ledex.

DCD/dNA_of_stepper, promptly on the wafer CD to the sensitivity of ledex numerical aperture.

DCD/dThickness_of_resist, promptly on the wafer CD to the sensitivity of the resist thickness on the wafer.

DCD/dRefractive_index_of_resist, promptly on the wafer CD to the sensitivity of the refractive index of resist on the wafer.

DCD/dResist_stack, the i.e. sensitivity that CD piles up parameter (for example thickness of BARC) on the wafer to resist.

DCD/dFlare_of_stepper, CD is to the sensitivity of the amount of flash of ledex on the wafer.

DCD/dResist_processing_parameters, promptly on the wafer CD to the sensitivity of resist processing parameter (for example resist cures time, resist development time).

Above-mentioned Sensitirity va1ue can be called manufacturability design or DFM specification.The present invention can utilize the DFM specification to carry out the technique sensitiveness inspection and determine technology weakness in the design.That is to say that the present invention can be used for discerning the design attitude with the above sensitivity of certain threshold value.Additional function in this DFM specification analysis can comprise:

ANOVA analyzes (it is to the standard technique in the statistical study of experimental result), in order to discern the interaction between crucial sensitivity contribution factor and these factors

Complete process window beyond dosage-focus window is determined

The design attitude that identification is limited process window

Provide the recommendation of the design modification of enhanced process window

Should be noted that analysis and checking/inspection above all can carry out at the uniqueness or the general features of concrete or specific ledex or scanner.For example, wafer fabrication facility can have a plurality of identical or different ledexs; Each ledex comprises the aberration of oneself or " signature " of feature.Like this, aberration or feature group can merge in the simulation process (during for example image generates (square frame 126 of Fig. 4)) aloft in order to analyze the appropriateness of this design for this independent ledex.Also can be used for ledex into specific one or more the bests of design alternative for the emulation of a plurality of ledexs.

Shall also be noted that plant point analysis, technique sensitiveness analysis and above-mentioned all other analyses of RET checking, multiplex (MUX) can depend on the user and need be applied in full chip design or the localized areas.Localized areas may be useful especially for interactive analysis and review.For example, circuit designers can use the localized areas analysis to come the design in storehouse, accurate adjustment zonule or accurate adjustment zonule design before full chip design is finished.

High-speed simulation can also be used in the optimization that offset printing is provided with, and for example searches (i) illumination that strengthens and/or optimize and NA setting, (ii) resist processing parameter (for example curing time, development time) and (iii) resist stack design (for example resist thickness, BARC layer structure).

In fact, high-speed simulation can be used in the RET design itself or during the RET design itself, RET that promptly search to strengthen and/or that optimize modifies, and this RET is modified to provide in the wafer patternization or produced and for example compares with the required pattern on the wafer in enhanced results to some extent aspect the edge displacement.The RET design can also be optimized process window size and DFM specification simultaneously.During the RET checking and/or checking, this designed capacity also can be used for producing the recommendatory modification for the RET design at defective design attitude place.

In addition, the present invention can be used for optimizing jointly or strengthening jointly RET modification and offset printing setting.For example, the OPC design can be optimized jointly with means of illumination.By select suitable illumination (promptly optimizing illumination and OPC design simultaneously) together with the OPC design, the present invention can simplify OPC and modify, and does not sacrifice final patterning quality and robustness.It should be noted that this method can reduce the mask manufacture complicacy and therefore reduce the mask cost.

The present invention can also be used to strengthening and/or optimizing for example enforcement of a plurality of exposures of other RET technology.A plurality of exposures refer to such technology, and this technology is decomposed into a plurality of exposure paths with pattern, thereby each exposure is in (for example because between the pattern distance that increases) under the interactional situation that reduces between the pattern part of printed patterns only.The existing technologies of a kind of being called " double exposure " is divided into the pattern of x-and y-orientation with pattern, and is respectively them and utilizes x-and the illumination of y-dipole.Suppose the exposure of two exposures or fixed number, the decomposition of optimization may separate so simple unlike x-with y-, and may depend on circuit pattern itself.The present invention can be used for searching for the optimization of analysis chip pattern at a plurality of exposures and decompose.For example, all exposures can utilize identical illumination, and perhaps illumination can be different for each exposure, so that strengthen and/or optimize this process.

The common optimization of illumination-decomposition can further improve offset printing quality and robustness.In addition, optimization can comprise the common optimization with other offset printing parameter, and these parameters for example are OPC design, NA, pupil filtration.It should be noted that all these are optimized and common optimization can use system of the present invention and technology to strengthen.

In addition, system of the present invention can play the effect of the chip design client from manufacturing plant to it " special envoy " when being equipped with technological parameter used in semiconductor manufacturing factory.That is to say, this system in package crucial technology and tool information, and make by makers' chip design client to be used for coming their design of assessment, measurement and optimization, and directly do not visit their makers' proprietary process details at they specific partners of manufacturing plant.

And system of the present invention and technology can be fed to metering outfit forward with its simulation result.That is to say that the result of this system offers different meterings and the checking tool in mask workshop and the wafer fabrication facility.For example, it can be of value to the mask design and the manufacturing of qualification " environment sensitive ", and for example the sensitizing range can have the inspection tolerance limit of loosening.It can also help to make existing metering and check that resource clustering is in wafer fabrication facility, thereby they concentrate in " nargin district ", for example, use the RET-design-inspection of the physics of metering outfit at those RET weakness of identification in inspection of many process window and technique sensitiveness inspection.

System of the present invention and technology can with the mask detection system of routine (TeraScan DUV graticule check system for example, from KLA-Tencor Corporation of San Jose, California USA) combines, in order to carry out the real-time wafer pattern inspection through emulation.For example, one or more high-definition pictures of Chang Gui offset printing and/or mask detection system acquisition mask.For mask pattern, the high-definition picture through catching can have than the higher resolution of aerial image that is printed on the mask pattern on the wafer; Like this, Chang Gui offset printing and/or mask detection system can provide be arranged in mask on relevant more multidata, details and/or the information of pattern.These high-definition pictures can offer the wafer pattern of system of the present invention in order to emulation, analysis and/or characterization expectation in resist and/or after the substrate etching, the pattern of this expectation and then make comparisons with the required circuit pattern on the wafer.When departing from, can defect recognition.Do like this and verified that not only mask is to design according to required back RET to make, and verified in the realization of the design of the RET on the mask and will on wafer, create required result.The practice that this checking mode is different from present mask detection industry is that D:D or D:DB check, because this checking mode will be in the resist on the wafer of emulation or etching after pattern and design object make comparisons, thereby realized that small pieces arrive target (D:T) checking mode.Fig. 7 illustrates the example procedure stream that D:T checks.

The D:T checking mode does not need to use back RET design database.Replace, the D:T checking mode can use the high-definition picture of being caught by mask inspection tool, as back RET data, with in the resist on the dummy wafer or etching after image or pattern.D:T inspection technology then can utilize in the resist of emulation or etching after pattern, with the wafer of this design on target pattern make comparisons.

The D:T checking mode is a kind of inspection method of dynamic every pixel impressionability of height for mask, because it only catches the influential defective of wafer circuit pattern to printing, and do not report that those that be known as disruptive defective (promptly not influencing the defective of chip output) do not change the defective of wafer circuit pattern.By eliminating the disruptive defective, D:T checks can be reduced unnecessary mask " waste material ", improves the mask output and/or reduce the mask cost.When combining with offset printing optical element (for example ledex or scanner) and the processing of wafer resist, but D:T also can catch, detects and/or be identified in the detection threshold " following " that D:D or D:DB check influence the defects on mask of wafer circuit pattern, reduces the possibility of wafer output loss thus.

It should be noted that D:T inspection technology can check that technology is integrated with D:DB and/or combine, with defective additional in the identification RET design, false and/or that do not detect.For example, when D:T checks technology for detection and/or discerns remarkable defective, and D:DB checks that technology does not detect and/or discern this defective or the defect area (promptly this mask designs according to back RET database just) on the mask, the RET design at possible defect area place comprises error or in error (i.e. this design can not produce required wafer pattern, makes even this mask designs according to this).

In another aspect, D:T checks the auditability that also can improve mask.OPC feature little and complexity makes traditional D:D or D:DB check and is subjected to very big challenge.Many little OPC features can be labeled as " defective " (being false defect), have reduced auditability and have therefore created constraint in the OPC design.Utilize D:T to check, high-definition picture directly be used in the resist on the dummy wafer or etching after pattern, wherein all little OPC features are filtered.Therefore the OPC feature little with more no longer comprising of design object also can reduce the false defect rate.

It should be noted that by reference and will be incorporated into this from product document, application note, technology/journal of writings and the operator's manual of the TeraScan DUV graticule check system of KLA-Tencor company.

At another embodiment that is used for according to mask detection technology of the present invention, be filed on March 18th, 2003, assigned serial number is middle the description and illustrated system of non-temporary patent application " System and Method for Lithography ProcessMonitoring and Control " of 10/390,806 (hereinafter referred to as " lithography process monitors and the control patented claim "), device and/or technology can be used in combination measuring with one or more inventions of the present invention, check, characterization and/or evaluation optical flat printing equipment, method and/or relevant with it subsystem (for example optical subsystem of this equipment and control system and the photomask of use therewith).In this, use lithography process to monitor and the system of control patented claim and technology are sampled and/or the one or more aerial image gathered can offer system of the present invention, with make comparisons through wafer pattern emulation and/or that estimate.In this pattern, the optics setting of RET database and lithographic apparatus provided through the aerial image of emulation and (it should be noted that after system of the present invention used, if only need aerial image, omit then that resist develops and the substrate etch simulation), and lithography process monitors and the system of control patented claim and technology provide actual image in the air from the lithographic apparatus trapped inside.This can carry out on the basis of individual element with identification departing from/defective therebetween.

Specifically, this mask detection technology uses the aerial image through measuring through the offset printing design of emulation and dull and stereotyped printed design to detect or discern the defective of offset printing in designing.This method comprises that the bitmap based on pixel that generates this offset printing design represents, wherein should comprise pixel data based on bitmap of pixel, and each pixel data has been represented the pixel (as mentioned above) with intended pixel size.This method uses the bitmap based on pixel of offset printing design to represent to generate the aerial image through emulation of offset printing design.

This method further comprises the aerial image through measure of measurement image data with generation offset printing design, and wherein the aerial image through measuring is that the bitmap based on pixel that is designed by the offset printing of offset printing instrument generation at the wafer plane place is represented.Subsequently, this method is made comparisons the aerial image through measuring of offset printing design and the aerial image through emulation of dull and stereotyped printed design, to detect the potential error in the offset printing design.And this method also can be made comparisons the required predetermined pattern that comprises of offset printing design in the aerial image of emulation and database.

As mentioned above, the bitmap based on pixel of offset printing design represents to comprise that a plurality of polygons that will arrange with predetermined configurations convert its bitmap based on pixel to and represent.Bitmap based on pixel can be a plurality of polygonal grayscale images of representative.

In addition, Pixel Dimensions can be determined as described above.In one embodiment, Pixel Dimensions can and/or use the numerical aperture and the wavelength of the projection optics spare of offset printing instrument to determine greater than the Nyquist frequency in the aerial image of offset printing design.

Certainly, this method can be implemented on one or more embodiment of system of the present invention.In fact, all embodiment, invention, feature and/or the technology of describing with respect to other inspection technology can be with the mask detection technology implementation above, and this mask detection technology uses the aerial image through measuring through the offset printing design of emulation and dull and stereotyped printed design to detect or discern the defective of offset printing in designing.For simplicity, will not repeat those discussion.

It should be noted that as mentioned above description and illustrated invention can be used for gathering actual wafer pattern to be used for mask detection in aforementioned patent applications.For simplicity, will not repeat those discussion here; Yet what should spell out is that the whole content with aforementioned patent applications is incorporated into this by reference, comprises feature, attribute, substitute, material, technology and the advantage of for example all inventions.

Here description and figure are shown with many inventions.Although described and illustrated some embodiment, feature, material, configuration, attribute and the advantage of these inventions, but should be appreciated that many other and different and/or similar embodiment, feature, material, configuration, attribute, structure and advantage of the present invention are according to describing, illustrate and what is claimed is significantly.Equally, here description and illustrated inventive embodiment, feature, material, configuration, attribute, structure and advantage are not exhaustive, and should be appreciated that these other similar and different embodiment, feature, material, configuration, attribute, structure and advantage of the present invention within the scope of the invention.

Specifically, in an application, this system promotes and has realized the quick checking or the inspection of RET design.This is meant such process, and this process is used the concrete emulation of whole lithography process, comprises with respect to required on the final wafer pattern/desired result, verifies, characterization and/or analyze the RET design.

Claims (34)

1. one kind is used for system that the offset printing design of being made up of a plurality of polygons of arranging with predetermined configurations is carried out emulation, and this system comprises:

Microprocessor subsystem represents that in order to described a plurality of polygons are converted to described a plurality of polygonal bitmap based on pixel wherein said bitmap based on pixel comprises pixel data, and wherein each pixel data is represented the pixel with intended pixel size; And

Accelerator subsystems, be coupled to described microprocessor subsystem, represent in order to the bitmap that uses described offset printing design based on pixel, calculate at least a portion of the aerial image of described offset printing design, wherein said accelerator subsystems comprises a plurality of programmable gate arrays that are configured to the described pixel data of parallel processing.

2. the system of claim 1, wherein said bitmap based on pixel is the described a plurality of polygonal grayscale images of representative.

3. the system of claim 1, wherein said intended pixel size is greater than the Nyquist frequency in the aerial image of described offset printing design.

4. the system of claim 1, wherein said intended pixel size are to use the numerical aperture of projection optics spare of offset printing instrument and wavelength to determine.

5. the system of claim 1, wherein said offset printing design utilizes resolution enhance technology, and wherein said microprocessor subsystem will utilize a plurality of polygons of resolution enhance technology to convert described a plurality of polygonal bitmap based on pixel to represent.

6. the system of claim 1, wherein said accelerator subsystems comprises a plurality of accelerator subsystems, each accelerator subsystems is coupled to described microprocessor subsystem and is provided with the part of described bitmap based on pixel, calculates the aerial image of the described offset printing design corresponding with the described part of described bitmap based on pixel to use related with it pixel data.

7. the system of claim 6, wherein said microprocessor subsystem comprises a plurality of microprocessors, and wherein each microprocessor is coupled at least one related accelerator subsystems.

8. the system of claim 7, wherein said a plurality of accelerator subsystems each use pixel data to carry out fast fourier transform, to generate the counterpart of described aerial image.

9. the system of claim 1, wherein said accelerator subsystems is calculated the aerial image in the resist that is formed by described offset printing design on wafer, wherein said accelerator subsystems uses the described bitmap based on pixel of described offset printing design to represent and represent the projection of offset printing instrument and the matrix of coefficients of light optics spare, calculates the described aerial image in the resist.

10. the system of claim 9, wherein said accelerator subsystems is calculated the pattern that is formed by described offset printing design on described wafer, wherein said accelerator subsystems uses the described bitmap based on pixel of described offset printing design to represent and represent the projection of offset printing instrument and the described matrix of coefficients of light optics spare, calculates the described pattern on the described wafer.

11. the system of claim 10 further comprises the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, in order to pattern that is calculated on the described wafer and required predetermined pattern are made comparisons.

12. the system of claim 10 further comprises the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, determines the critical dimension that described offset printing designs in order to use the pattern that is calculated on the described wafer.

13. the system of claim 10 further comprises the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, determines the edge placement that described offset printing designs in order to use the pattern that is calculated on the described wafer.

14. the system of claim 10, further comprise the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, in order to using pattern on the described wafer to determine printing sensitivity, described sensitivity is in response to that the coefficient of the described matrix that changes the projection of representing the offset printing instrument and light optics spare calculates.

15. on behalf of the described coefficient of the described matrix of the projection of offset printing instrument and light optics spare, the system of claim 14 wherein represent one or more in focusing, dosage, numerical aperture, illumination aperture and the aberration.

16. the system of claim 15, wherein said disposal system use described printing sensitivity to determine the described projection of described offset printing instrument and one group of parameter of light optics spare.

17. the system of claim 10, further comprise the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, in order in response to the comparison between pattern that is calculated on the described wafer and the required predetermined pattern, detect the error in the described offset printing design.

18. the system of claim 17, wherein in response to detecting described error, the correction that described disposal system is determined described offset printing is designed is to proofread and correct the described error in the described offset printing design.

19. one kind is used for system that the offset printing design of being made up of a plurality of polygons of arranging with predetermined configurations is carried out emulation, this system comprises:

Microprocessor subsystem, comprise a plurality of microprocessors, represent that in order to convert described offset printing design to its bitmap wherein said bitmap based on pixel comprises pixel data, and wherein each pixel data is represented the pixel with intended pixel size based on pixel; And

A plurality of accelerator subsystems, each accelerator subsystems comprises a plurality of programmable integrated circuits that are configured to the described pixel data of parallel processing, and each accelerator subsystems is connected to related microprocessor, calculates the part of the aerial image of described offset printing design in order to the described counterpart of representing based on the bitmap of pixel that uses described offset printing design.

20. the system of claim 19, wherein said bitmap based on pixel is the described a plurality of polygonal grayscale images of representative.

21. the system of claim 19, wherein said intended pixel size is greater than the Nyquist frequency in the aerial image of described offset printing design.

22. the system of claim 19, wherein said intended pixel size are to use the numerical aperture of projection optics spare of offset printing instrument and wavelength to determine.

23. the system of claim 19, resolution enhance technology is used in wherein said offset printing design, and wherein said microprocessor subsystem will use a plurality of polygons of resolution enhance technology to convert described a plurality of polygonal bitmap based on pixel to represent.

24. the system of claim 19, each of wherein said a plurality of accelerator subsystems all use pixel data to carry out fast fourier transform, to generate the counterpart of described aerial image.

25. the system of claim 19, wherein said a plurality of accelerator subsystems is calculated the aerial image in the resist that is formed by described offset printing design on wafer, wherein said accelerator subsystems is used the described bitmap based on pixel of described offset printing design to represent and is represented the projection of offset printing instrument and the matrix of coefficients of light optics spare, calculates the described aerial image in the resist.

26. the system of claim 25, wherein said accelerator subsystems is calculated the pattern that is formed by described offset printing design on described wafer, wherein said accelerator subsystems is used the described bitmap based on pixel of described offset printing design to represent and is represented the projection of offset printing instrument and the described matrix of coefficients of light optics spare, calculates the described pattern on the described wafer.

27. the system of claim 26 further comprises the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, in order to pattern that is calculated on the described wafer and required predetermined pattern are made comparisons.

28. the system of claim 26 further comprises the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, determines the critical dimension that described offset printing designs in order to use the pattern that is calculated on the described wafer.

29. the system of claim 26 further comprises the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, determines the edge placement that described offset printing designs in order to use the pattern that is calculated on the described wafer.

30. the system of claim 26, further comprise the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, in order to using pattern on the described wafer to determine printing sensitivity, described sensitivity is in response to that the coefficient of the described matrix that changes the projection of representing the offset printing instrument and light optics spare calculates.

31. on behalf of the described coefficient of the described matrix of the projection of offset printing instrument and light optics spare, the system of claim 30 wherein represent one or more in focusing, dosage, numerical aperture, illumination aperture and the aberration.

32. the system of claim 31, wherein said disposal system use described printing sensitivity to determine the described projection of described offset printing instrument and one group of parameter of light optics spare.

33. the system of claim 26, further comprise the disposal system that is coupled to described microprocessor subsystem and described accelerator subsystems, in order in response to the comparison between pattern that is calculated on the described wafer and the required predetermined pattern, detect the error in the described offset printing design.

34. the system of claim 33, wherein in response to detecting described error, the correction that described disposal system is determined described offset printing is designed is to proofread and correct the error in the described offset printing design.

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