CN100433271C - Manufacture of dielectric layers between polycrystal silicon - Google Patents
Manufacture of dielectric layers between polycrystal silicon Download PDFInfo
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- CN100433271C CN100433271C CNB021047804A CN02104780A CN100433271C CN 100433271 C CN100433271 C CN 100433271C CN B021047804 A CNB021047804 A CN B021047804A CN 02104780 A CN02104780 A CN 02104780A CN 100433271 C CN100433271 C CN 100433271C
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Abstract
The present invention relates to a method for making an interjacent dielectric layer of polycrystalline silicon, which comprises the following steps: firstly, providing a substrate, and a first polycrystalline silicon layer is formed on the substrate; then forming an interjacent dielectric layer of polycrystalline silicon, and the method for forming the interjacent dielectric layer of polycrystalline silicon is to utilize plasma of argon /oxygen /ammonia gas, plasma of krypton gas/oxygen /ammonia gas, plasma of argon / oxygen, or plasma of krypton gas/ oxygen; then forming a second polycrystalline silicon layer on the interjacent dielectric layer of the polycrystalline silicon.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor element, and particularly relevant for a kind of manufacture method of dielectric layers between polycrystal silicon (Interpoly Dielectric Layer) of flash element.
Background technology
Flash memory is a kind of electric formula programmable read only memory (EEPROM) of erasing, and it has the advantage that still can preserve data after can writing, can erasing and cut off the power supply, be personal computer and electronic equipment a kind of memory component of extensively adopting.In addition, flash memory is nonvolatile memory (Non-Volatile Memory; NVM) a kind of, it has the advantage that the nonvolatile memory volume is little, access speed is fast, power consumption is low, and the mode that adopts " one one " (Block by Block) to erase when erasing (Erasing) because of its data is so have more the fast advantage of service speed.
Shown in Figure 1A to Fig. 1 C, it is known flash memory manufacturing process generalized section.
Please refer to Figure 1A, a substrate 100 at first is provided, and in substrate 100, form a tunnel oxide 102.Then, form the polysilicon layer 104 of a patterning on tunnel oxide 102, it is used as floating grid.Afterwards, in polysilicon layer 104 substrate on two sides 100, form flush type drain electrode 106.
Afterwards, please refer to Figure 1B to Fig. 1 C, form a dielectric layer 108 in substrate 100, it is used as dielectric layers between polycrystal silicon.Afterwards, form another polysilicon layer 110 on the dielectric layer above the polysilicon layer 104 108, it is used as the control grid.
Wherein, the method for formation dielectric layer 108 forms in the mode of a thermal process.And this thermal process is to be controlled at about 900 degree Celsius temperature and aerating oxygen, so that the reaction of the silicon atom of oxygen molecule and polysilicon layer 104, and the dielectric layer 108 of formation silicon monoxide material.Yet, with the formed dielectric layer 108 of the mode of known thermal process, its surface comparatively coarse (Rough), this coarse surface easily makes between two polysilicon layers 104,110 and produces leakage current.In addition, when known mode with thermal process forms dielectric layer 108, because oxygen molecule has the characteristic of lattice direction, what meaning was an oxygen molecule for a certain lattice direction in the polysilicon layer 104 is reactive preferable, and reactive relatively poor for another lattice direction in the polysilicon layer 104, therefore the uniformity of formed dielectric layer 108 is relatively poor.Moreover known mode with thermal process forms dielectric layer 108 and needs high temperature about 900 degree Celsius, under the condition of high temperature like this, may make that the diffusion of impurities in the flush type drain electrode 106 enter tunnel oxide 102 in the substrate 100, and then cause the situation of leakage current.
In addition, in known method,, can be used as the dielectric layers between polycrystal silicon 108 of flash memory usually with the form of silica-silicon-nitride and silicon oxide (ONO) stack layer or silica-silicon nitride (ON) stack layer in order to improve the proof voltage character of dielectric layer 108.Yet the method for known formation silica-silicon-nitride and silicon oxide stack layer or silica-silicon nitride stack layer must just be formed through many processing steps, therefore will improve the complexity of technology.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of dielectric layers between polycrystal silicon is being provided, and has more coarse situation to avoid known mode with thermal process to be formed the dielectric layers between polycrystal silicon surface.
Another object of the present invention provides a kind of manufacture method of dielectric layers between polycrystal silicon, forms when having the dielectric layers between polycrystal silicon of high withstand voltage characteristic to solve in the known method desire, has the problem that increases process complexity.
A further object of the present invention provides a kind of manufacture method of flash element, avoiding in the process that forms its dielectric layers between polycrystal silicon, and Yin Gaowen and cause diffusion of impurities in the flush type drain electrode to tunnel oxide.
Another purpose of the present invention provides a kind of manufacture method of dielectric layers between polycrystal silicon of flash element, takes place with the situation that reduces leakage current, so as to improving the reliability of element.
The present invention proposes a kind of manufacture method of dielectric layers between polycrystal silicon, and the method at first provides a substrate, and has been formed with one first polysilicon layer in the substrate.Then on first polysilicon layer, form a dielectric layers between polycrystal silicon, and the method that forms this dielectric layers between polycrystal silicon be in temperature be Celsius 400 the degree conditions under, utilize one argon gas/oxygen/ammonia plasmas, a krypton gas/oxygen/ammonia plasmas to form.Wherein the proportion of composing of argon gas/oxygen/ammonia is 96.5: 3: 0.5 in this argon gas/oxygen/ammonia plasmas.The proportion of composing of krypton gas/oxygen/ammonia is 96.5: 3: 0.5 in this krypton gas/oxygen/ammonia plasmas.Afterwards, on dielectric layers between polycrystal silicon, form one second polysilicon layer again.
The present invention proposes a kind of manufacture method of flash element, and the method at first provides a substrate, and forms a tunnel oxide on the surface of substrate.Then, form one first polysilicon layer of patterning on tunnel oxide, it is as the usefulness of floating grid.Afterwards, in the first polysilicon layer substrate on two sides, form flush type drain electrode.Then, form a dielectric layer on first polysilicon layer, it is used as dielectric layers between polycrystal silicon.Wherein, the method that forms this dielectric layer be in temperature be Celsius 400 the degree conditions under, utilize one argon gas/oxygen/ammonia plasmas, a krypton gas/oxygen/ammonia plasmas to form.Wherein the proportion of composing of argon gas/oxygen/ammonia is 96.5: 3: 0.5 in this argon gas/oxygen/ammonia plasmas.The proportion of composing of krypton gas/oxygen/ammonia is 96.5: 3: 0.5 in this krypton gas/oxygen/ammonia plasmas.Afterwards, on dielectric layer, form one second polysilicon layer again, to use as the control grid.
The manufacture method of dielectric layers between polycrystal silicon of the present invention because the oxonium ion in the plasma does not have the character of lattice direction, therefore can make formed polysilicon dielectric layer have the preferable uniformity.
The manufacture method of dielectric layers between polycrystal silicon of the present invention, because the oxonium ion in the plasma can penetrate silicon layer fast, and generate dielectric layers between polycrystal silicon with silicon atom reaction, therefore can and promptly form the dielectric layers between polycrystal silicon of desired thickness in the short period in lower temperature.
The manufacture method of dielectric layers between polycrystal silicon of the present invention only needs single processing step, can form the dielectric layers between polycrystal silicon with high withstand voltage characteristic, therefore can reduce the complexity of technology.
The manufacture method of flash element of the present invention owing to form the temperature conditions that its dielectric layers between polycrystal silicon only need 400 degree Celsius approximately, therefore can be avoided the impurity Yin Gaowen of flush type drain electrode and diffuses to tunnel oxide.
The manufacture method of the dielectric layers between polycrystal silicon of flash element of the present invention can reduce the chance that leakage current takes place, and then improves the reliability of element.
Description of drawings
Figure 1A to Fig. 1 C is the manufacturing process generalized section of known a kind of flash element;
Fig. 2 A to Fig. 2 C is the manufacturing process generalized section according to the flash element of a preferred embodiment of the present invention.
100,200: substrate
102,202: tunnel oxide
104,204: polysilicon layer (floating grid)
106,206: the flush type drain electrode
108,208: dielectric layer (dielectric layers between polycrystal silicon)
110,210: polysilicon layer (control grid)
207: plasma
Embodiment
Fig. 2 A to Fig. 2 C, it is the manufacturing process generalized section according to the flash element of a preferred embodiment of the present invention.
Please refer to Fig. 2 A, the manufacture method of flash element of the present invention at first provides a substrate 200.Afterwards, in substrate 200, form a tunnel oxide 202.Then, on tunnel oxide 202, form the polysilicon layer 204 of a patterning, to use as floating grid.Afterwards, serve as to inject mask with polysilicon layer 204, carry out an ion implantation step, in polysilicon layer 204 substrate on two sides 200, to form flush type drain electrode 206.
Afterwards, please refer to Fig. 2 B, in substrate 200, form a dielectric layer 208, cover polysilicon layer 204.And dielectric layer 208 is used as dielectric layers between polycrystal silicon.
Wherein, the method that forms dielectric layer 208 is utilized the gas source of the mist of an inert gas and oxygen and ammonia as a plasma 207, and with temperature be controlled at Celsius 400 spend about and form.In the present embodiment, employed inert gas can be argon gas or krypton gas.And when with argon gas/oxygen/ammonia during as the gas source of plasma 207, the proportion of composing of argon gas/oxygen/ammonia for example is 96.5: 3: 0.5.When with krypton gas/oxygen/ammonia during as the gas source of plasma 207, the proportion of composing of krypton gas/oxygen/ammonia for example is 96.5: 3: 0.5.At this, inert gas (for example being argon gas or krypton gas) is to be used for bump (Bombard) oxygen and ammonia, so that oxygen and ammonia molecular ion change into oxonium ion and nitrogen ion.By the reaction of the silicon atom in oxonium ion and nitrogen ion and the polysilicon layer 204, can form the dielectric layer 208 of polysilicon nitrogen oxygen material (Polyoxynitride).The dielectric layer 208 of formed polysilicon nitrogen oxygen material is the same with known silica-silicon-nitride and silicon oxide stack layer or silica-silicon nitride stack layer to have high withstand voltage character.And, only need single processing step to form with the method for the present invention's dielectric layer 208.This kind mode pushes away lamination or silica-silicon nitride compared to known formation silica-silicon-nitride and silicon oxide, and to push away the method for lamination simply many.
In addition, the method for the formation dielectric layer 208 of present embodiment also can only be utilized the gas source of the mist of an inert gas and oxygen as plasma 207, and with temperature be controlled at Celsius 400 the degree about and form.In the present embodiment, employed inert gas can be argon gas or krypton gas.And when with argon gas/oxygen during as the gas source of plasma 207, the proportion of composing of argon gas/oxygen for example is 97: 3.When with krypton gas/oxygen during as the gas source of plasma 207, the proportion of composing of krypton gas/oxygen for example is 97: 3.At this, inert gas (for example being argon gas or krypton gas) is to be used for clashing into oxygen, so that oxygen molecule is ionized into oxonium ion.By the reaction of oxonium ion and silicon atom, can form the dielectric layer 208 of polycrystalline silica material (Polyoxide).
Then, please refer to Fig. 2 C, on the dielectric layer above the polysilicon layer 204 208, form another polysilicon layer 210, to use as the control grid.So, promptly finish the making of a flash element.
What is particularly worth mentioning is that the temperature conditions when the present invention forms dielectric layer 208 in the mode of plasma only needs about 400 degree Celsius.Need the temperature conditions of 900 degree Celsius compared to known mode with thermal process, the present invention not only can reduce the heat budget of technology, and can prevent the impurity Yin Gaowen in the flush type drain electrode 206 and diffuse in the tunnel oxide 202.Moreover the present invention utilizes oxonium ion/nitrogen ion and silicon atom reaction, because oxonium ion and nitrogen ion do not have the character of lattice direction, therefore has the preferable uniformity with the formed dielectric layer 208 of the present invention.In addition, the present invention is with the dielectric layer that mode is formed 208 of plasma, and the formed oxide layer of more known mode with thermal process has more level and smooth surface.Therefore, the formed dielectric layer 208 of the present invention can reduce between two polysilicon layers 204,210 and can produce the situation that leakage current is arranged.
Comprehensive the above, the present invention has following advantages:
1. the manufacture method of dielectric layers between polycrystal silicon of the present invention since the oxygen in the plasma from Son does not have the character of lattice direction, therefore formed dielectric layers between polycrystal silicon is had The better uniformity.
2. the manufacture method of dielectric layers between polycrystal silicon of the present invention since the oxygen in the plasma from Son can penetrate silicon layer fast, and generates this polysilicon dielectric layer with the silicon atom reaction, therefore can In lower temperature and namely form the dielectric layers between polycrystal silicon of desired thickness in the short period.
3. the manufacture method of the present invention's dielectric layers between polycrystal silicon only needs single processing step, namely Can form the dielectric layers between polycrystal silicon with high withstand voltage characteristic, therefore can reduce the complexity of technology The property.
4. the manufacture method of flash element of the present invention is owing to only form its dielectric layers between polycrystal silicon Need the temperature conditions of 400 degree approximately Celsius, therefore can avoid impurity Yin Gaowen that flush type drains and Diffuse to tunnel oxide.
5. the manufacture method of flash element of the present invention and dielectric layers between polycrystal silicon can reduce leakage The chance that electric current takes place, and then the reliability of raising element.
Claims (12)
1. the manufacture method of a dielectric layers between polycrystal silicon is characterized in that, this method comprises the following steps:
One substrate is provided, has been formed with one first polysilicon layer in this substrate;
Form a dielectric layers between polycrystal silicon on this first polysilicon layer, the mist that the method that wherein forms this dielectric layers between polycrystal silicon is utilized an inert gas and oxygen and ammonia forms as the gas source of a plasma; And
On this dielectric layers between polycrystal silicon, form one second polysilicon layer.
2. the manufacture method of dielectric layers between polycrystal silicon as claimed in claim 1 is characterized in that, the temperature that forms this dielectric layers between polycrystal silicon is 400 degree Celsius.
3. the manufacture method of dielectric layers between polycrystal silicon as claimed in claim 1 is characterized in that, this inert gas comprises argon gas.
4. the manufacture method of dielectric layers between polycrystal silicon as claimed in claim 3 is characterized in that, during as the gas source of this plasma, the proportion of composing of argon gas/oxygen/ammonia is 96.5: 3: 0.5 with the mist of argon gas/oxygen/ammonia.
5. the manufacture method of dielectric layers between polycrystal silicon as claimed in claim 1 is characterized in that, this inert gas comprises krypton gas.
6. the manufacture method of dielectric layers between polycrystal silicon as claimed in claim 5 is characterized in that, during as the gas source of this plasma, the proportion of composing of krypton gas/oxygen/ammonia is 96.5: 3: 0.5 with the mist of krypton gas/oxygen/ammonia.
7. a flash memory making method is characterized in that, this method comprises the following steps:
One tunnel oxide is provided in a substrate that is provided;
On this tunnel oxide, form a floating grid;
In this substrate of these floating grid both sides, form flush type drain electrode;
Form a dielectric layer on this floating grid, the mist that the method that wherein forms dielectric layer is utilized an inert gas and oxygen and ammonia forms as the gas source of a plasma; And
On this dielectric layer, form a control grid.
8. flash memory making method as claimed in claim 7 is characterized in that, the temperature that forms this dielectric layer is 400 degree Celsius.
9. flash memory making method as claimed in claim 7 is characterized in that this inert gas comprises argon gas.
10. flash memory making method as claimed in claim 9 is characterized in that, during as the gas source of this plasma, the proportion of composing of argon gas/oxygen/ammonia is 96.5: 3: 0.5 with the mist of argon gas/oxygen/ammonia.
11. flash memory making method as claimed in claim 7 is characterized in that, this inert gas comprises krypton gas.
12. flash memory making method as claimed in claim 11 is characterized in that, during as the gas source of this plasma, the proportion of composing of krypton gas/oxygen/ammonia is 96.5: 3: 0.5 with the mist of krypton gas/oxygen/ammonia.
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| CNB021047804A CN100433271C (en) | 2002-02-21 | 2002-02-21 | Manufacture of dielectric layers between polycrystal silicon |
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| CNB021047804A CN100433271C (en) | 2002-02-21 | 2002-02-21 | Manufacture of dielectric layers between polycrystal silicon |
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| CN1440056A CN1440056A (en) | 2003-09-03 |
| CN100433271C true CN100433271C (en) | 2008-11-12 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1210899A (en) * | 1997-06-26 | 1999-03-17 | 通用电气公司 | Silicon dioxide deposition by plasma activated evaporation process |
| US6297103B1 (en) * | 2000-02-28 | 2001-10-02 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
| US6303481B2 (en) * | 1999-12-29 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Method for forming a gate insulating film for semiconductor devices |
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2002
- 2002-02-21 CN CNB021047804A patent/CN100433271C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1210899A (en) * | 1997-06-26 | 1999-03-17 | 通用电气公司 | Silicon dioxide deposition by plasma activated evaporation process |
| US6303481B2 (en) * | 1999-12-29 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Method for forming a gate insulating film for semiconductor devices |
| US6297103B1 (en) * | 2000-02-28 | 2001-10-02 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
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| CN1440056A (en) | 2003-09-03 |
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