CA2676132A1 - Fpga lookup table with high speed read decoder - Google Patents

Fpga lookup table with high speed read decoder Download PDF

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Publication number
CA2676132A1
CA2676132A1 CA002676132A CA2676132A CA2676132A1 CA 2676132 A1 CA2676132 A1 CA 2676132A1 CA 002676132 A CA002676132 A CA 002676132A CA 2676132 A CA2676132 A CA 2676132A CA 2676132 A1 CA2676132 A1 CA 2676132A1
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CA
Canada
Prior art keywords
multiplexer
lookup table
input
lut
multiplexers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002676132A
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French (fr)
Other versions
CA2676132C (en
Inventor
Richard A. Carberry (Deceased)
Steven P. Young
Trevor J. Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx, Inc.
Richard A. Carberry (Deceased)
Steven P. Young
Trevor J. Bauer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx, Inc., Richard A. Carberry (Deceased), Steven P. Young, Trevor J. Bauer filed Critical Xilinx, Inc.
Publication of CA2676132A1 publication Critical patent/CA2676132A1/en
Application granted granted Critical
Publication of CA2676132C publication Critical patent/CA2676132C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

Abstract

A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and second LUT.

Claims (6)

1. A lookup table comprising:

a plurality of memory cells; and a tree multiplexer for accessing the memory cells, the tree multiplexer comprising:

a plurality of multiplexer stages including a next-to-last stage, each stage having a plurality of multiplexers; and a last multiplexer stage having a multiplexer with more than two inputs, wherein:

two of the inputs come from two of the multiplexers of the next-to-last stage; and one input comes from a source independent of the plurality of multiplexer stages.
2. The lookup table of claim 1, further comprising a multiplexer for selectively forwarding one of the input coming from the source independent of the plurality of multiplexer stages and an XOR output signal derived from an arithmetic function.
3. The lookup table of claim 2, wherein the XOR output signal is provided by an XOR gate having a first input derived from the arithmetic function and a second input derived from the two of the inputs from the two of the multiplexers of the next-to-last stage.
4. The lookup table of claim 3, wherein the second input derived from the two of the inputs from the two of the multiplexers of the next-to-last stage is derived by a multiplexer receiving the two inputs from the two of the multiplexers of the next-to-last stage and providing the second input.
5. The lookup table of claim 2, wherein the multiplexer for selectively forwarding receives a further input signal from another circuit not part of the tree multiplexer.
6. The lookup table of claim 5, wherein the multiplexer for selectively forwarding receives an input signal generated from two output signals from the next-to-last stage.
CA2676132A 2000-05-05 2001-04-06 Fpga lookup table with high speed read decoder Expired - Lifetime CA2676132C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/566,052 2000-05-05
US09/566,052 US6529040B1 (en) 2000-05-05 2000-05-05 FPGA lookup table with speed read decoder
CA2411650A CA2411650C (en) 2000-05-05 2001-04-06 Fpga lookup table with high speed read decoder

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CA2411650A Division CA2411650C (en) 2000-05-05 2001-04-06 Fpga lookup table with high speed read decoder

Publications (2)

Publication Number Publication Date
CA2676132A1 true CA2676132A1 (en) 2001-11-15
CA2676132C CA2676132C (en) 2012-01-03

Family

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Family Applications (2)

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CA2676132A Expired - Lifetime CA2676132C (en) 2000-05-05 2001-04-06 Fpga lookup table with high speed read decoder
CA2411650A Expired - Lifetime CA2411650C (en) 2000-05-05 2001-04-06 Fpga lookup table with high speed read decoder

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CA2411650A Expired - Lifetime CA2411650C (en) 2000-05-05 2001-04-06 Fpga lookup table with high speed read decoder

Country Status (5)

Country Link
US (2) US6529040B1 (en)
EP (2) EP1489745B1 (en)
CA (2) CA2676132C (en)
DE (2) DE60136974D1 (en)
WO (1) WO2001086812A2 (en)

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Also Published As

Publication number Publication date
US6621296B2 (en) 2003-09-16
EP1287615B1 (en) 2007-10-24
WO2001086812A3 (en) 2002-06-27
DE60131078T2 (en) 2008-08-07
DE60131078D1 (en) 2007-12-06
CA2411650C (en) 2012-11-27
US6529040B1 (en) 2003-03-04
EP1489745B1 (en) 2008-12-10
US20030071653A1 (en) 2003-04-17
EP1287615A2 (en) 2003-03-05
EP1489745A2 (en) 2004-12-22
CA2676132C (en) 2012-01-03
EP1489745A3 (en) 2006-06-28
CA2411650A1 (en) 2001-11-15
WO2001086812A2 (en) 2001-11-15
DE60136974D1 (en) 2009-01-22

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