CA2508041A1 - Processor virtualization mechanism via an enhanced restoration of hard architected states - Google Patents
Processor virtualization mechanism via an enhanced restoration of hard architected states Download PDFInfo
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- CA2508041A1 CA2508041A1 CA002508041A CA2508041A CA2508041A1 CA 2508041 A1 CA2508041 A1 CA 2508041A1 CA 002508041 A CA002508041 A CA 002508041A CA 2508041 A CA2508041 A CA 2508041A CA 2508041 A1 CA2508041 A1 CA 2508041A1
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- processor
- architected state
- hard architected
- storing
- hard
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- 238000000034 method Methods 0.000 claims abstract 42
- 230000004044 response Effects 0.000 claims 5
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000012163 sequencing technique Methods 0.000 claims 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30116—Shadow registers, e.g. coupled registers, not forming part of the register space
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/462—Saving or restoring of program or task context with multiple register sets
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
- Electrotherapy Devices (AREA)
- Multi Processors (AREA)
- Control Of Multiple Motors (AREA)
- Hardware Redundancy (AREA)
Abstract
A method and system are disclosed for pre-loading a hard architected state o f a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stor ed in the processor, are determined based on priorities assigned to the waiting processes.
Claims (15)
1. A method of operating a processor, said method comprising:
storing in a first set of storage locations in the processor a first hard architected state of a first process currently undergoing execution by the processor;
storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
in response to receiving a process interrupt at the processor, loading the second hard architected state from the second set of storage locations into the first set of storage locations; and executing the second process.
storing in a first set of storage locations in the processor a first hard architected state of a first process currently undergoing execution by the processor;
storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
in response to receiving a process interrupt at the processor, loading the second hard architected state from the second set of storage locations into the first set of storage locations; and executing the second process.
2. The method of claim 1, further comprising dynamically replacing the second hard architected state with a third architected state of another idle process while the first process is executing.
3. The method of claim 1, further comprising:
selecting the second process, from a pool of idle processes, for storage of the second hard architected state into the processor, based on a priority of said second process.
selecting the second process, from a pool of idle processes, for storage of the second hard architected state into the processor, based on a priority of said second process.
4. The method of claim 1, further comprising:
saving the first hard architected state in response to receiving the process interrupt.
saving the first hard architected state in response to receiving the process interrupt.
5. The method of claim 1, further comprising:
storing a shadow copy of the first hard architected state within the processor; and in response to receiving the process interrupt in the processor, storing the shadow copy of the first hard architected state in a memory.
storing a shadow copy of the first hard architected state within the processor; and in response to receiving the process interrupt in the processor, storing the shadow copy of the first hard architected state in a memory.
6. A processor comprising:
at least one execution unit;
an instruction sequencing unit coupled to the at least one execution unit;
a first set of storage locations for storing a first hard architected state of a first process currently undergoing execution by the processor; and a second set of storage locations for storing a second hard architected state of a second process that is idle, wherein the second process is from a pool of idle processes, and wherein the second hard architected state that is stored in the second set of storage locations is selected based on a priority assignment of the processing in the pool of idle processes.
at least one execution unit;
an instruction sequencing unit coupled to the at least one execution unit;
a first set of storage locations for storing a first hard architected state of a first process currently undergoing execution by the processor; and a second set of storage locations for storing a second hard architected state of a second process that is idle, wherein the second process is from a pool of idle processes, and wherein the second hard architected state that is stored in the second set of storage locations is selected based on a priority assignment of the processing in the pool of idle processes.
7. The processor of claim 6, further comprising means for updating the second hard architected state in response to a process interrupt.
8. The processor of claim 6, further comprising:
execution circuitry for executing memory access instructions, whereby the processor is capable of storing the second architected state independently of execution of memory access instructions by the execution circuitry.
execution circuitry for executing memory access instructions, whereby the processor is capable of storing the second architected state independently of execution of memory access instructions by the execution circuitry.
9. The processor of claim 6, further comprising:
a corresponding shadow register coupled to the first set of storage locations, the shadow register containing a shadow copy of at least a portion of the first hard architected state; and a memory coupled to the shadow register, wherein the processor, in receipt of a process interrupt, stores the shadow copy of the first hard architected state to the memory.
a corresponding shadow register coupled to the first set of storage locations, the shadow register containing a shadow copy of at least a portion of the first hard architected state; and a memory coupled to the shadow register, wherein the processor, in receipt of a process interrupt, stores the shadow copy of the first hard architected state to the memory.
10. A data processing system comprising:
a plurality of processors including a processor in accordance with claim 6;
a volatile memory hierarchy coupled to the plurality of processors; and an interconnect coupling the plurality of processors.
a plurality of processors including a processor in accordance with claim 6;
a volatile memory hierarchy coupled to the plurality of processors; and an interconnect coupling the plurality of processors.
11. A processor comprising:
means for storing in a first set of storage location in the processor a first hard architected state of a first process currently undergoing execution by the processor;
means for storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
means, responsive to receiving a process interrupt at the processor, for loading the second hard architected state from the second set of storage locations into the first set of storage locations; and means for executing the second process.
means for storing in a first set of storage location in the processor a first hard architected state of a first process currently undergoing execution by the processor;
means for storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle;
means, responsive to receiving a process interrupt at the processor, for loading the second hard architected state from the second set of storage locations into the first set of storage locations; and means for executing the second process.
12. The processor of claim 11, further comprising means for dynamically replacing the second hard architected state with a third architected state of another idle process while the first process is executing.
13. The processor of claim 11, further comprising:
means for selecting the second process, from a pool of idle processes, for storage in the processor, based on a priority of said second process.
means for selecting the second process, from a pool of idle processes, for storage in the processor, based on a priority of said second process.
14. The processor of claim 11, further comprising:
means for saving the first hard architected state in response to receiving the process interrupt.
means for saving the first hard architected state in response to receiving the process interrupt.
15. The processor of claim 11, further comprising:
means for storing a shadow copy of the first hard architected state within the processor; and means, responsive to receiving the process interrupt in the processor, for storing the shadow copy of the first hard architected state in a memory.
means for storing a shadow copy of the first hard architected state within the processor; and means, responsive to receiving the process interrupt in the processor, for storing the shadow copy of the first hard architected state in a memory.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/313,320 US6981083B2 (en) | 2002-12-05 | 2002-12-05 | Processor virtualization mechanism via an enhanced restoration of hard architected states |
| US10/313,320 | 2002-12-05 | ||
| PCT/EP2003/014863 WO2004051463A2 (en) | 2002-12-05 | 2003-11-14 | Method and apparatus for switching between processes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2508041A1 true CA2508041A1 (en) | 2004-06-17 |
| CA2508041C CA2508041C (en) | 2011-06-07 |
Family
ID=32468218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2508041A Expired - Fee Related CA2508041C (en) | 2002-12-05 | 2003-11-14 | Processor virtualization mechanism via an enhanced restoration of hard architected states |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US6981083B2 (en) |
| EP (1) | EP1570352B1 (en) |
| KR (1) | KR100615775B1 (en) |
| CN (1) | CN1726469A (en) |
| AT (1) | ATE487180T1 (en) |
| AU (1) | AU2003298240A1 (en) |
| CA (1) | CA2508041C (en) |
| DE (1) | DE60334835D1 (en) |
| TW (1) | TWI263938B (en) |
| WO (1) | WO2004051463A2 (en) |
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-
2002
- 2002-12-05 US US10/313,320 patent/US6981083B2/en not_active Expired - Fee Related
-
2003
- 2003-10-31 TW TW092130386A patent/TWI263938B/en not_active IP Right Cessation
- 2003-11-05 KR KR1020030078050A patent/KR100615775B1/en not_active IP Right Cessation
- 2003-11-14 CA CA2508041A patent/CA2508041C/en not_active Expired - Fee Related
- 2003-11-14 AU AU2003298240A patent/AU2003298240A1/en not_active Abandoned
- 2003-11-14 WO PCT/EP2003/014863 patent/WO2004051463A2/en not_active Application Discontinuation
- 2003-11-14 DE DE60334835T patent/DE60334835D1/en not_active Expired - Lifetime
- 2003-11-14 EP EP03795964A patent/EP1570352B1/en not_active Expired - Lifetime
- 2003-11-14 AT AT03795964T patent/ATE487180T1/en not_active IP Right Cessation
- 2003-11-14 CN CNA2003801064655A patent/CN1726469A/en active Pending
Also Published As
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|---|---|
| EP1570352A2 (en) | 2005-09-07 |
| EP1570352B1 (en) | 2010-11-03 |
| TW200422949A (en) | 2004-11-01 |
| AU2003298240A1 (en) | 2004-06-23 |
| KR100615775B1 (en) | 2006-08-25 |
| WO2004051463A2 (en) | 2004-06-17 |
| WO2004051463A3 (en) | 2005-06-02 |
| US6981083B2 (en) | 2005-12-27 |
| KR20040049256A (en) | 2004-06-11 |
| ATE487180T1 (en) | 2010-11-15 |
| DE60334835D1 (en) | 2010-12-16 |
| CA2508041C (en) | 2011-06-07 |
| US20040111548A1 (en) | 2004-06-10 |
| TWI263938B (en) | 2006-10-11 |
| AU2003298240A8 (en) | 2004-06-23 |
| CN1726469A (en) | 2006-01-25 |
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