CA2471231A1 - Power factor controller - Google Patents
Power factor controller Download PDFInfo
- Publication number
- CA2471231A1 CA2471231A1 CA002471231A CA2471231A CA2471231A1 CA 2471231 A1 CA2471231 A1 CA 2471231A1 CA 002471231 A CA002471231 A CA 002471231A CA 2471231 A CA2471231 A CA 2471231A CA 2471231 A1 CA2471231 A1 CA 2471231A1
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- line
- power
- power supply
- power factor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A power factor controller or corrector is provided in a regulated power supp ly circuit, in which the load and line regulation circuitry is separate from on e another and in which the line regulation is provided with a 1/x2 modulator i n which the switching frequency is inversely proportional to the square of the line voltage.
Description
POWER FACTOR CONTROLLER
FIELD OF THE IN VENTION
The present invention relates to an electronic power supply and more particularly to a power factor controller or corrector (PFC). This invention is related to U.S. Patent No. 5,357,418 issued October 18, 1994 ofthe same inventor, which concerns a hybrid power supply with improved regulation.
BACKGROUND OF THE INVENTION
Presently known PFCs have the following drawbacks:
They use a double 'Feedback loop, i.e. one to sense the line current and the other to sense the output voltage. This arrangement requires heavy calculating power in the chips that generate the driving pulse width to the power FETs;
These chips have important Limitations that end up in incoherent system equations for calculations of the chokes and power FETs characteristics, thus requiring a lot of empirical testing from the designer or trouble shooter.
Besides, it still remains unclear whether these chips are usable above 500 watts. All these factors lead to very substantial development and maintenance costs.
This is probably the major reason why the U.S. Government has been reluctant to adopt the IEC 555-2 norm for the last decade.
An objective ofthe invention is to eliminate the above deficiencies and provide a simple system allowing use of a single basic equation and to increase predictability of the circuitry.
Another objective of the invention is to provide a system which is applicable to any power output (watts to kilowatts).
SLfMMARY OF THE I1~VENTION
In essence, the power factor controller or corrector of the present invention comprises separating load and line regulations in the powex supply circuit and providing a 1/x2 modulator module for the line regulation in which switching frequency is inversely proportional to the square of the line voltage.
Furthermore, the load regulation is preferably achieved by a 1/v pulsewidth generator which generates a pulse duration that is inversely proportional to the voltage from a differential gain circuitry that produces a control voltagewhich is proportional to the difference between a fraction of output voltage and a fixed reference voltage. Also, a loop delay may be provided between the differential gain circuitry and the 1/v pulse generator.
The power factor controller of the present invention may be advantageously combined with a hybrid power supply, such as disclosed and claimed in U. S.
Patent No. 5,357,418 and having a 1/x frequency modulating module. The combination comprises cascading the 1/x2 module with the 1/x module.
According to the present invention, the PFC boost circuit will exhibit the following properties:
The AC line current will be sinusoidal, i.e. will look like the AC line voltage, thus bringing the power factor close to 1 and the harmonic content of AC
current will be close to 0. Such characteristics would meet IEC 555-2 requirements and other subsequent IEC norms;
The output DC voltage will be about 450 VDC for AC line variations from 85 VAC to 265 VAC.
FIELD OF THE IN VENTION
The present invention relates to an electronic power supply and more particularly to a power factor controller or corrector (PFC). This invention is related to U.S. Patent No. 5,357,418 issued October 18, 1994 ofthe same inventor, which concerns a hybrid power supply with improved regulation.
BACKGROUND OF THE INVENTION
Presently known PFCs have the following drawbacks:
They use a double 'Feedback loop, i.e. one to sense the line current and the other to sense the output voltage. This arrangement requires heavy calculating power in the chips that generate the driving pulse width to the power FETs;
These chips have important Limitations that end up in incoherent system equations for calculations of the chokes and power FETs characteristics, thus requiring a lot of empirical testing from the designer or trouble shooter.
Besides, it still remains unclear whether these chips are usable above 500 watts. All these factors lead to very substantial development and maintenance costs.
This is probably the major reason why the U.S. Government has been reluctant to adopt the IEC 555-2 norm for the last decade.
An objective ofthe invention is to eliminate the above deficiencies and provide a simple system allowing use of a single basic equation and to increase predictability of the circuitry.
Another objective of the invention is to provide a system which is applicable to any power output (watts to kilowatts).
SLfMMARY OF THE I1~VENTION
In essence, the power factor controller or corrector of the present invention comprises separating load and line regulations in the powex supply circuit and providing a 1/x2 modulator module for the line regulation in which switching frequency is inversely proportional to the square of the line voltage.
Furthermore, the load regulation is preferably achieved by a 1/v pulsewidth generator which generates a pulse duration that is inversely proportional to the voltage from a differential gain circuitry that produces a control voltagewhich is proportional to the difference between a fraction of output voltage and a fixed reference voltage. Also, a loop delay may be provided between the differential gain circuitry and the 1/v pulse generator.
The power factor controller of the present invention may be advantageously combined with a hybrid power supply, such as disclosed and claimed in U. S.
Patent No. 5,357,418 and having a 1/x frequency modulating module. The combination comprises cascading the 1/x2 module with the 1/x module.
According to the present invention, the PFC boost circuit will exhibit the following properties:
The AC line current will be sinusoidal, i.e. will look like the AC line voltage, thus bringing the power factor close to 1 and the harmonic content of AC
current will be close to 0. Such characteristics would meet IEC 555-2 requirements and other subsequent IEC norms;
The output DC voltage will be about 450 VDC for AC line variations from 85 VAC to 265 VAC.
-2-Shown input/output relationship represents a theoretical view on the present power factor corrected power supplies.
BRIEF DESCRIPTION OF DRAWINGS
In the appended drawings:
~ Fig. 1 shows a previously used electronic power supply which is neither regulated nor PFC controlled;
Fig. 2 shows a block-diagram of the PFC control system of the present invention;
Fig. 3 shows an electronic circuitry illustrations of block-diagram of Fig. 2;
Fig. 4 shows a cascade arrangement of module of the present invention with module of U.S. Patent No. 5,357,418.
Fig. 5 shows a diagram of voltage/current phases of the present invention;
Fig. 6 shows a diagram of voltage%urrent phases of known power supply systems which are not PCF controlled.
DETAILED DESCRIPTION OF THE INVENTION
An electronic power supply can be defined as a power converter converting AC line voltage ( 115 VAC or 220 VAC) into a DC voltage necessary to feed any electronic circuitry. The simplest electronic power supply is shown on Fig. 1 and includes a very primitive transformer (TR), rectifying bridge (BR) of capacitor (G) type. However, such a simple arrangement is seldom used due to'the following reasons:
~ output DC voltage will change whenever the line voltage changes, thus not providing any reliable line regulation;
BRIEF DESCRIPTION OF DRAWINGS
In the appended drawings:
~ Fig. 1 shows a previously used electronic power supply which is neither regulated nor PFC controlled;
Fig. 2 shows a block-diagram of the PFC control system of the present invention;
Fig. 3 shows an electronic circuitry illustrations of block-diagram of Fig. 2;
Fig. 4 shows a cascade arrangement of module of the present invention with module of U.S. Patent No. 5,357,418.
Fig. 5 shows a diagram of voltage/current phases of the present invention;
Fig. 6 shows a diagram of voltage%urrent phases of known power supply systems which are not PCF controlled.
DETAILED DESCRIPTION OF THE INVENTION
An electronic power supply can be defined as a power converter converting AC line voltage ( 115 VAC or 220 VAC) into a DC voltage necessary to feed any electronic circuitry. The simplest electronic power supply is shown on Fig. 1 and includes a very primitive transformer (TR), rectifying bridge (BR) of capacitor (G) type. However, such a simple arrangement is seldom used due to'the following reasons:
~ output DC voltage will change whenever the line voltage changes, thus not providing any reliable line regulation;
-3-~ even if the Line voltage is stable, DC voltage will change if current is drawn by the load changes, thus not providing any load regulation;
~ at 60 Hz, weight and size of transformer will become prohibitive;
~ capacitor charging and discharging will produce a high peak current demands, i.e. harmonics of 60 Hz. Such generation of harmonics was tolerated until January 1-, 2001, but is ~o longer tolerated in Europe and soon will not be tolerated in North America.
The above deficiencies are particularly addressed by the system of the present invention. Electronic industry needs power supplies having much better performances than the circuit shown in Fig. 1 can offer, since modern power supplies are much more complex.
The typical power supply users will expect their electronic power supply to fulfill not only one but all of the following conditions:
~ high quality regulations;
~ high efficiency;
~ small size and weight;
~ high power factor.
High quality regulations means that:
~ generated output voltage essentially does not change when line voltage or Ioad changes (typically less than 0.1%);
~ no noise is essentially superimposed on the output voltage (typically less than 1 millivolt);
~ output impedance of the supply is negligible (typically 10 milliohms);
~ transient response is fast (typically 10 microseconds).
~ at 60 Hz, weight and size of transformer will become prohibitive;
~ capacitor charging and discharging will produce a high peak current demands, i.e. harmonics of 60 Hz. Such generation of harmonics was tolerated until January 1-, 2001, but is ~o longer tolerated in Europe and soon will not be tolerated in North America.
The above deficiencies are particularly addressed by the system of the present invention. Electronic industry needs power supplies having much better performances than the circuit shown in Fig. 1 can offer, since modern power supplies are much more complex.
The typical power supply users will expect their electronic power supply to fulfill not only one but all of the following conditions:
~ high quality regulations;
~ high efficiency;
~ small size and weight;
~ high power factor.
High quality regulations means that:
~ generated output voltage essentially does not change when line voltage or Ioad changes (typically less than 0.1%);
~ no noise is essentially superimposed on the output voltage (typically less than 1 millivolt);
~ output impedance of the supply is negligible (typically 10 milliohms);
~ transient response is fast (typically 10 microseconds).
-4-Effects of low quality regulations are:
~ Output voltage varying too much, which is not too critical for digital circuitry, but is very annoying for analog circuitry such as timers, A/D
converters, multipliers, integrators, etc.
S ~ Noise will randomly trigger flip-flops and provoke intermittent and unexpected breakdown in digital circuitry;
~ Transient response is too low and severely limits the frequency response of user's power circuitry, such as power amplifiers, plasma electrodes, etc.
High eff ciency means the following:
I O ~ All power which is not used in the load is going to generate heat in the power supply of the user's circuitry. In the past, 7S% to 80% e~ciency was considered to be acceptable, but in the future, it may be insufficient in view of the following reasons:
~ simple mathematics show that a power supply having 7S% efficiency will 15 heat up not 20%, but 500% more if compared with a 9S% efficiency power supply;
~ there is a strong correlation between e~ciency and other parameters, such as size, weight, noise content and reliability.
Effect of poor efficiency is:
Above all, loss of reliability, which is a highly non-linear function of 20 temperature. If temperature increases 10°C, MTBF decreases several times.
Small size and weight means the following:
At the present time, size/weight proportions are about 2-3 cubic inches /1 lb (70-100 cubic cm/1 kg) per regulated I watt produced. The proportion could be even more if the user can handle the heat dissipation problem with which he does not feel
~ Output voltage varying too much, which is not too critical for digital circuitry, but is very annoying for analog circuitry such as timers, A/D
converters, multipliers, integrators, etc.
S ~ Noise will randomly trigger flip-flops and provoke intermittent and unexpected breakdown in digital circuitry;
~ Transient response is too low and severely limits the frequency response of user's power circuitry, such as power amplifiers, plasma electrodes, etc.
High eff ciency means the following:
I O ~ All power which is not used in the load is going to generate heat in the power supply of the user's circuitry. In the past, 7S% to 80% e~ciency was considered to be acceptable, but in the future, it may be insufficient in view of the following reasons:
~ simple mathematics show that a power supply having 7S% efficiency will 15 heat up not 20%, but 500% more if compared with a 9S% efficiency power supply;
~ there is a strong correlation between e~ciency and other parameters, such as size, weight, noise content and reliability.
Effect of poor efficiency is:
Above all, loss of reliability, which is a highly non-linear function of 20 temperature. If temperature increases 10°C, MTBF decreases several times.
Small size and weight means the following:
At the present time, size/weight proportions are about 2-3 cubic inches /1 lb (70-100 cubic cm/1 kg) per regulated I watt produced. The proportion could be even more if the user can handle the heat dissipation problem with which he does not feel
-5-comfortable unless he is a heat transfer expert.
High power factor means the following:
Power supply should consider the hydro line as a pure ohmic resistor, i.e.
current drawn from the grid is sinusoidal with less than 3 amps of harmonic 3 content. Ideally, the power factor should be around 99%. However, nearly all power supplies designed before 1990, and quite a few now have a power factor of around 66%.
Effect of poor power factor is:
Non-compliance.with IEC 555-2 norm issued in 1990, which is compulsory in Europe since January 1, 2001, and is expected to become compulsory by the CSA
(Canadian Standard Association) in 2002 and in the U.S. in 2003.
Present state of the art:
Major power supply makers (Kepco, Lambda, Power One, Acopian, etc.) might satisfy one or two of the above four factors, but none of them satisfy aI1 four.
This may be explained as being due to the following problems:
Satisfying all four factors together is extremely difficult due to conflicting requirements between efficiency and quality of regulations;
Paradoxically, power supply development has been considered for a long time a non-glamorous technology and relatively little R&D has been done when compared with the field of communications and computers.
In view of the above, the user still has to choose between bad regulation and efficiency with some risk of malfunctions always present. Cost of regulated supplies has not come down, like the rest of electronic gear. A custom power supply of average complexity can take more than 1 year of development and cost around
High power factor means the following:
Power supply should consider the hydro line as a pure ohmic resistor, i.e.
current drawn from the grid is sinusoidal with less than 3 amps of harmonic 3 content. Ideally, the power factor should be around 99%. However, nearly all power supplies designed before 1990, and quite a few now have a power factor of around 66%.
Effect of poor power factor is:
Non-compliance.with IEC 555-2 norm issued in 1990, which is compulsory in Europe since January 1, 2001, and is expected to become compulsory by the CSA
(Canadian Standard Association) in 2002 and in the U.S. in 2003.
Present state of the art:
Major power supply makers (Kepco, Lambda, Power One, Acopian, etc.) might satisfy one or two of the above four factors, but none of them satisfy aI1 four.
This may be explained as being due to the following problems:
Satisfying all four factors together is extremely difficult due to conflicting requirements between efficiency and quality of regulations;
Paradoxically, power supply development has been considered for a long time a non-glamorous technology and relatively little R&D has been done when compared with the field of communications and computers.
In view of the above, the user still has to choose between bad regulation and efficiency with some risk of malfunctions always present. Cost of regulated supplies has not come down, like the rest of electronic gear. A custom power supply of average complexity can take more than 1 year of development and cost around
-6-
7 PCT/CA03/00009 $200,000. Some recent special 1 kw power supplies development had taken 5 years and 1. S million dollars.
The PFC controller of the present invention was designed with a view of the following factors:
S ~ to satisfy impending compulsory PFC requirements for all power supplies above 300 watts in view of IEC SSS-2 and other IEC norms;
~ need for PFC for 5 kilowatts power supply for plasma electrodes;
~ failure to find a reliable design information and off the-shelf chips for power above S00 watts;
~ knowledge of tremendous difficulties of developers to achieve PFC at only 1 kilowatt;
~ finding that some principles used in U.S. Patent No. S,3S7,418 could also be used for the system of the present invention, such as clear separation of line and load regulations and hyperbolic modulations.
1S The PFC controller of the 'present invention uses the same philosophy as U.S.
Patent No. S,3S7,418 clearly separating the line regulation (open loop) from the load regulation (closed loop). This feature allows the use of a single basic equation and to increase predictability of the circuitry. Such approach is general and may be applicable to any power output (watts to kilowatts).
It can be shown both mathematically and experimentally that the power output of the basic boost circuitry of Fig. 1 is:
P-KF~(PW-)2 L
Wherein:
_7_ P is wanted output power in watts;
K is constant;
F is frequency of switching of power FETs in kilohertz;
V is line RMS voltage in volts;
PW is pulsewidth in microseconds;
L is value of power inductance in millihenries.
Referring now to Fig. 2 of the drawings which shows a block-diagram of the PFC controller of the present invention, it provides the following:
Line regulation step . For a given constant power, if line varies for example from 1 lOv to 220v (factor of 2), choke will tend to force four times more power into the load by raising output DC voltage two times. To prevent this, frequency has to be decreased four times. Consequently, switching frequency has to be inversely proportional to the square of the Iine voltage. This process is achieved by block 1 representing 1/x2 modulator which is assigned to regulate the line variations. It produces a frequency proportional to the inverse of the square of the line voltage. For example, if the line voltage is 115 VAC, frequency generated by block 1 will be 80 kilohertz. If the line voltage is 230 VAC, frequency generated by block 1 will be 20 kilohertz.
Load regulation step In case the load demand varies abruptly, for example from S KW to 0 watts, choke will tend to force SKW into an open circuit, which will raise the output voltage to infinity if pulsewidth is not decreased rapidly to about 0 microseconds. In other words, pulsewidth has to be decreased very fast when output voltages increase.
Block 2 represents a 1/v pulsewidth generator which will generate a pulse _g_ duration which is inversely proportional to V, wherein V comes from differential gain represented by block 4. Block 4 produces a control voltage which is proportional to the difference between a fraction of the output voltage and a fixed reference voltage.
Loop delay represented by block 3 is analogous to a time lag circuitry used in analog control loops, such as Bode or Nyquist criterion techniques.
In conclusion, block 1 is provided fox line regulation and blocks 2, 3 and 4 are provided for the load regulation. For example, if the load varies from 5 kilowatts to 0 .
kilowatts (open circuit), pulsewidth will vary from 5 microseconds to 0 microseconds.
Fig. 3 shows a preferred embodiment of the circuit representing blocks 1-4 of Fig. 2 which are operating in the following manner:
U3 of block 1 is a simple logic CMOS standard (CD 4007) dual complementary pair plus inverter logic gate used for its analog properties.
This chip contains one P-channel FET and one N channel FET which can be used as a non-linear voltage controlled resistor. When connected to inverters of the same chip through R9, R10 and R11, a non-linear voltage controlled oscillator is formed, the frequency of which can be made varying like the inverse of the square of the control voltage applied to pin 3 of U3. Pin 12 of U3 outputs a varying frequency which is applied to U4 of block 2, which is a standard CMOS (CD4047). U4 is producing fixed duration pulses 100 nanoseconds wide. These short pulses are applied to US
FET driver (TC 427) which puts element Ql (IRFZ40) of block 2 "ON" in about 30 nanoseconds. Whenever Ql conducts, capacitor C1 of block 2 is discharging in about 100 nanoseconds for each period of the frequency produced by U3. Whenever pulse from U4 is low, Q1 is "OFF" and C1 starts to charge up as a ramp due to a constant -9_ current applied by Ul of block 2 current source. Voltage of Cl is applied to input 1 of U6 comparator of block 2. Input 2 of the comparator U6 receives a varying DC
reference produced by element US of block 4. Whenever voltage at C1 reaches the value of the DC reference, comparator U6 switches to a logic "1" state. With subsequent proper gating, net result is a pulse of duration proportional to the voltage coming from pin 1 of U8 and is occurnng at each period of frequencies produced by U3.
Voltage appearing on the load side is firstly divided in block 4 into 7.8 VDC
corresponding to 350 VDC and 10 VDC corresponding to 450 VDC. Difference between this voltage and a fixed reference voltage of 10 V is amplified by a factor of 4.7. Thus, if 10 VDC corresponding to 450 VDC appears at divider, output pin 1 of U8 will be "0" V. This will produce a pulsewidth of 0 microseconds at U6, i.e.
no energy will be transferred to the load. In this case, a voltage of 450 VDC at the load means that the circuit is open. In case the voltage at the divider is 7.8 VDC
corresponding to 350 VDC as full load situation, output at pin 1 of U8 will be maximum, and subsequently, pulsewidth produced at U6 will be maximum, thus allowing transfer of energy to the load and increasing the output voltage back to 450 VDC. Practically, loading process will not vary so abruptly as "no load" -"full load", and pulsewidth will be adjusted by control loop continuoulsy and slowly. In this case, variations from "no load" to "full load" (or the reverse) occurs only at start-up or when the load is accidentally removed (for example, broken connection).
Feedback loop will react in both cases, but with some transient effect. Following regulation stages will absorb this transient effect. Such basic principle is valid even in the case of abrupt variations. In view of this fact, pulse width will be adjusted by control loop in any loading circumstances. Elements of block 3, such as R19, C8 and buffer will introduce some delay in the in loop in order to avoid oscillations. The buffer of block 3 comprises amplifier Lm324/2 element, wherein pin 7 strapped to pin 6 provides infinite input impedance at pin S and near "0" output impedance at pin 7.
S It should be emphasized that the PFC system of the present invention could be used with any "boost circuitry" whose requirements could be stated as follows:
Output should be a high value (450V to 1000V) regulated DC voltage. Boost circuit can output DC voltage several times higher than the peak voltage;
Input should look to the grid line (110 VAC, 220 VAC, SSO VAC, etc.) like a pure ohmic resistor;
The current drawn should be pure sinusoid (see Fig. S), in phase with the AC
line voltage. The voltage/current relationship shown in Fig. S is present in any PFC
controlled power supply, including that of the present invention.
In contrast, Fig. 6 shows a configuration of the current line which is not useful 1 S for the PFC system of the present invention. It is normally present in any power supply that has no PFC. The high peak currents of this configuration produce problems in the hydro lines.
All electronic components shown on Fig. 3 represent a preferred embodiment only and had been chosen mainly due to their immediate availability. Any other equivalent elements could be used to provide the same function for the same result.
Fig. 4 represents an arrangement according to U.S. Patent No. S,3S7,418 in combination with the PFC controller of the present invention. When cascading one 1/x2 PFC module of the present invention and one 1/x module of the U.S. Patent No.
S,3S7,418, as shown in Fig. 4, it is possible to realize, for example, a 0-100V, 10 amps (1 kilowatt) adjustable regulated power supply.
In this case, the combined performance will be:
Regulation: linear grade, i.e. line + load of 0.01%; transient response - 20 microseconds and output impedance - 20 milliohms;
Ripple + noise of 1 millivolt peak to peak;
Efficiency: 92.5%;
Power factor: 99%;
Size and weight: 500 cubic inches, 10 Ib (2w/cubic inch,100w11b).
Presently available "linear type" regulated power supplies have the following characteristics:
Regulation: linear grade, i.e. line + load of 0.01%, transient response - 20 microseconds, output impedance - 20 milliohms;
Ripple + noise: 1 millivolt peak to peak;
Effciency: 30-40% (2 kilowatts of heat to dissipate internally);
Power factor: 66%;
Size and weight: 2000 cubic inches, 100 Ib (0.5 w/cubic inch, 10 w/lb) Presently available "switching type" regulated supplies have the following characteristics:
Efficiency: 75% (250 watts of heat to dissipate internally);
Power factor: 99%;
Size and weight: 500 cubic inches, l2 lbs (2 w/cubic inch, 80 w/lb) Regulation: line + load of 0.1%, 0.5%, transient response - 2000 to 5000 microseconds, output impedance - unknown;
Ripple + noise: 150 millivolt peak to peak.
:12-In view of the above data, in the presently available regulated power supplies, the customer has to make a difficult choice between a well regulated, but very hot power supply and a cool, but badly regulated power supply. In practice, the customer has to pick the lesser of two evils; ~ liut always will have non-negligible risks.
Separate PFC modules do exist, which will deliver 450 VDC outputs, but the customer is left with the problem of converting the 450 VDC to lower voltages.
Usually, he adds a switching supply in cascade, which is likely double the RFI
output.
Besides, such modules axe not currently available above 500 watts. Such technology is not very mature even in Europe.
Other advantages of cascading shown in Fig. 4 allows to decrease the development costs of power supplies by a factor of 10 considering the fact that development cost of a medium complexity power supply is about $250,000 with the development time of 18 months. This factor reflects the sale price, since a typical price for a well regulated 1 KW power supply is $5000.00.
1S The reason for such excessive costs is the fact that most technologies used up to date do not separate the line regulation and the load regulation. Having lines varying by factor of four (85 VAC - 265 VAC) and load varying by a factor of infinity (0 watts to 1 kilowatt) make the performance of the feedback loop almost unpredictable, especially since complex magnetic components, such as high frequency transformers and chokers, are in the feedback loops. Net result is that numerous iterations and breadboards have to be built before wanted performances are achieved. In this case, magnetic components very often have to be designed by cut and try guesswork. It all results in expensive debugging time when testing the circuitry.
As a conclusion, it is clear that separating load and line regulation used in the present invention makes analysis coherent and predictable. In this case, equation for determining values of components; especially magnetic components, are numerous, but easily implemented on an Excel spread sheet.
As a result, cascade arrangement of Fig. 4 is the most commercially advantageous for realizations of regulated electronic power supplies, which represent probably over 90% in the market of all power supplies.
A similar, or at least very close arrangement, may be used for efficient, high power battery chargers (kilowatts), e~cient, high power current sources (kilowatts) and efficient, high power sinewave inverters (kilowatts).
The PFC controller of the present invention was designed with a view of the following factors:
S ~ to satisfy impending compulsory PFC requirements for all power supplies above 300 watts in view of IEC SSS-2 and other IEC norms;
~ need for PFC for 5 kilowatts power supply for plasma electrodes;
~ failure to find a reliable design information and off the-shelf chips for power above S00 watts;
~ knowledge of tremendous difficulties of developers to achieve PFC at only 1 kilowatt;
~ finding that some principles used in U.S. Patent No. S,3S7,418 could also be used for the system of the present invention, such as clear separation of line and load regulations and hyperbolic modulations.
1S The PFC controller of the 'present invention uses the same philosophy as U.S.
Patent No. S,3S7,418 clearly separating the line regulation (open loop) from the load regulation (closed loop). This feature allows the use of a single basic equation and to increase predictability of the circuitry. Such approach is general and may be applicable to any power output (watts to kilowatts).
It can be shown both mathematically and experimentally that the power output of the basic boost circuitry of Fig. 1 is:
P-KF~(PW-)2 L
Wherein:
_7_ P is wanted output power in watts;
K is constant;
F is frequency of switching of power FETs in kilohertz;
V is line RMS voltage in volts;
PW is pulsewidth in microseconds;
L is value of power inductance in millihenries.
Referring now to Fig. 2 of the drawings which shows a block-diagram of the PFC controller of the present invention, it provides the following:
Line regulation step . For a given constant power, if line varies for example from 1 lOv to 220v (factor of 2), choke will tend to force four times more power into the load by raising output DC voltage two times. To prevent this, frequency has to be decreased four times. Consequently, switching frequency has to be inversely proportional to the square of the Iine voltage. This process is achieved by block 1 representing 1/x2 modulator which is assigned to regulate the line variations. It produces a frequency proportional to the inverse of the square of the line voltage. For example, if the line voltage is 115 VAC, frequency generated by block 1 will be 80 kilohertz. If the line voltage is 230 VAC, frequency generated by block 1 will be 20 kilohertz.
Load regulation step In case the load demand varies abruptly, for example from S KW to 0 watts, choke will tend to force SKW into an open circuit, which will raise the output voltage to infinity if pulsewidth is not decreased rapidly to about 0 microseconds. In other words, pulsewidth has to be decreased very fast when output voltages increase.
Block 2 represents a 1/v pulsewidth generator which will generate a pulse _g_ duration which is inversely proportional to V, wherein V comes from differential gain represented by block 4. Block 4 produces a control voltage which is proportional to the difference between a fraction of the output voltage and a fixed reference voltage.
Loop delay represented by block 3 is analogous to a time lag circuitry used in analog control loops, such as Bode or Nyquist criterion techniques.
In conclusion, block 1 is provided fox line regulation and blocks 2, 3 and 4 are provided for the load regulation. For example, if the load varies from 5 kilowatts to 0 .
kilowatts (open circuit), pulsewidth will vary from 5 microseconds to 0 microseconds.
Fig. 3 shows a preferred embodiment of the circuit representing blocks 1-4 of Fig. 2 which are operating in the following manner:
U3 of block 1 is a simple logic CMOS standard (CD 4007) dual complementary pair plus inverter logic gate used for its analog properties.
This chip contains one P-channel FET and one N channel FET which can be used as a non-linear voltage controlled resistor. When connected to inverters of the same chip through R9, R10 and R11, a non-linear voltage controlled oscillator is formed, the frequency of which can be made varying like the inverse of the square of the control voltage applied to pin 3 of U3. Pin 12 of U3 outputs a varying frequency which is applied to U4 of block 2, which is a standard CMOS (CD4047). U4 is producing fixed duration pulses 100 nanoseconds wide. These short pulses are applied to US
FET driver (TC 427) which puts element Ql (IRFZ40) of block 2 "ON" in about 30 nanoseconds. Whenever Ql conducts, capacitor C1 of block 2 is discharging in about 100 nanoseconds for each period of the frequency produced by U3. Whenever pulse from U4 is low, Q1 is "OFF" and C1 starts to charge up as a ramp due to a constant -9_ current applied by Ul of block 2 current source. Voltage of Cl is applied to input 1 of U6 comparator of block 2. Input 2 of the comparator U6 receives a varying DC
reference produced by element US of block 4. Whenever voltage at C1 reaches the value of the DC reference, comparator U6 switches to a logic "1" state. With subsequent proper gating, net result is a pulse of duration proportional to the voltage coming from pin 1 of U8 and is occurnng at each period of frequencies produced by U3.
Voltage appearing on the load side is firstly divided in block 4 into 7.8 VDC
corresponding to 350 VDC and 10 VDC corresponding to 450 VDC. Difference between this voltage and a fixed reference voltage of 10 V is amplified by a factor of 4.7. Thus, if 10 VDC corresponding to 450 VDC appears at divider, output pin 1 of U8 will be "0" V. This will produce a pulsewidth of 0 microseconds at U6, i.e.
no energy will be transferred to the load. In this case, a voltage of 450 VDC at the load means that the circuit is open. In case the voltage at the divider is 7.8 VDC
corresponding to 350 VDC as full load situation, output at pin 1 of U8 will be maximum, and subsequently, pulsewidth produced at U6 will be maximum, thus allowing transfer of energy to the load and increasing the output voltage back to 450 VDC. Practically, loading process will not vary so abruptly as "no load" -"full load", and pulsewidth will be adjusted by control loop continuoulsy and slowly. In this case, variations from "no load" to "full load" (or the reverse) occurs only at start-up or when the load is accidentally removed (for example, broken connection).
Feedback loop will react in both cases, but with some transient effect. Following regulation stages will absorb this transient effect. Such basic principle is valid even in the case of abrupt variations. In view of this fact, pulse width will be adjusted by control loop in any loading circumstances. Elements of block 3, such as R19, C8 and buffer will introduce some delay in the in loop in order to avoid oscillations. The buffer of block 3 comprises amplifier Lm324/2 element, wherein pin 7 strapped to pin 6 provides infinite input impedance at pin S and near "0" output impedance at pin 7.
S It should be emphasized that the PFC system of the present invention could be used with any "boost circuitry" whose requirements could be stated as follows:
Output should be a high value (450V to 1000V) regulated DC voltage. Boost circuit can output DC voltage several times higher than the peak voltage;
Input should look to the grid line (110 VAC, 220 VAC, SSO VAC, etc.) like a pure ohmic resistor;
The current drawn should be pure sinusoid (see Fig. S), in phase with the AC
line voltage. The voltage/current relationship shown in Fig. S is present in any PFC
controlled power supply, including that of the present invention.
In contrast, Fig. 6 shows a configuration of the current line which is not useful 1 S for the PFC system of the present invention. It is normally present in any power supply that has no PFC. The high peak currents of this configuration produce problems in the hydro lines.
All electronic components shown on Fig. 3 represent a preferred embodiment only and had been chosen mainly due to their immediate availability. Any other equivalent elements could be used to provide the same function for the same result.
Fig. 4 represents an arrangement according to U.S. Patent No. S,3S7,418 in combination with the PFC controller of the present invention. When cascading one 1/x2 PFC module of the present invention and one 1/x module of the U.S. Patent No.
S,3S7,418, as shown in Fig. 4, it is possible to realize, for example, a 0-100V, 10 amps (1 kilowatt) adjustable regulated power supply.
In this case, the combined performance will be:
Regulation: linear grade, i.e. line + load of 0.01%; transient response - 20 microseconds and output impedance - 20 milliohms;
Ripple + noise of 1 millivolt peak to peak;
Efficiency: 92.5%;
Power factor: 99%;
Size and weight: 500 cubic inches, 10 Ib (2w/cubic inch,100w11b).
Presently available "linear type" regulated power supplies have the following characteristics:
Regulation: linear grade, i.e. line + load of 0.01%, transient response - 20 microseconds, output impedance - 20 milliohms;
Ripple + noise: 1 millivolt peak to peak;
Effciency: 30-40% (2 kilowatts of heat to dissipate internally);
Power factor: 66%;
Size and weight: 2000 cubic inches, 100 Ib (0.5 w/cubic inch, 10 w/lb) Presently available "switching type" regulated supplies have the following characteristics:
Efficiency: 75% (250 watts of heat to dissipate internally);
Power factor: 99%;
Size and weight: 500 cubic inches, l2 lbs (2 w/cubic inch, 80 w/lb) Regulation: line + load of 0.1%, 0.5%, transient response - 2000 to 5000 microseconds, output impedance - unknown;
Ripple + noise: 150 millivolt peak to peak.
:12-In view of the above data, in the presently available regulated power supplies, the customer has to make a difficult choice between a well regulated, but very hot power supply and a cool, but badly regulated power supply. In practice, the customer has to pick the lesser of two evils; ~ liut always will have non-negligible risks.
Separate PFC modules do exist, which will deliver 450 VDC outputs, but the customer is left with the problem of converting the 450 VDC to lower voltages.
Usually, he adds a switching supply in cascade, which is likely double the RFI
output.
Besides, such modules axe not currently available above 500 watts. Such technology is not very mature even in Europe.
Other advantages of cascading shown in Fig. 4 allows to decrease the development costs of power supplies by a factor of 10 considering the fact that development cost of a medium complexity power supply is about $250,000 with the development time of 18 months. This factor reflects the sale price, since a typical price for a well regulated 1 KW power supply is $5000.00.
1S The reason for such excessive costs is the fact that most technologies used up to date do not separate the line regulation and the load regulation. Having lines varying by factor of four (85 VAC - 265 VAC) and load varying by a factor of infinity (0 watts to 1 kilowatt) make the performance of the feedback loop almost unpredictable, especially since complex magnetic components, such as high frequency transformers and chokers, are in the feedback loops. Net result is that numerous iterations and breadboards have to be built before wanted performances are achieved. In this case, magnetic components very often have to be designed by cut and try guesswork. It all results in expensive debugging time when testing the circuitry.
As a conclusion, it is clear that separating load and line regulation used in the present invention makes analysis coherent and predictable. In this case, equation for determining values of components; especially magnetic components, are numerous, but easily implemented on an Excel spread sheet.
As a result, cascade arrangement of Fig. 4 is the most commercially advantageous for realizations of regulated electronic power supplies, which represent probably over 90% in the market of all power supplies.
A similar, or at least very close arrangement, may be used for efficient, high power battery chargers (kilowatts), e~cient, high power current sources (kilowatts) and efficient, high power sinewave inverters (kilowatts).
Claims (4)
1. A power factor controller or corrector in a regulated power supply circuit, which comprises separating load and line regulations in the power supply circuit and providing a 1/x2 modulator module for the line regulation in which switching frequency is inversely proportional to the square of the line voltage.
2. A power factor controller or corrector according to claim 1, in which the load regulation is achieved by a 1/v pulsewidth generator which generates a pulse duration that is inversely proportional to the voltage from a differential gain circuitry that produces a control voltage which is proportional to the difference between a fraction of output voltage and a fixed reference voltage.
3. A power factor controller or corrector according to claim 2, in which a loop delay is provided between the differential gain circuitry and the 1/v pulse generator.
4. A power factor controller or corrector according to claim 1, 2 or 3, combined with a hybrid power supply having a 1/x frequency modulating module, said combination comprising cascading the 1/x2 module with the 1/x module.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US34705202P | 2002-01-11 | 2002-01-11 | |
| US60/347,052 | 2002-01-11 | ||
| PCT/CA2003/000009 WO2003058797A1 (en) | 2002-01-11 | 2003-01-09 | Power factor controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2471231A1 true CA2471231A1 (en) | 2003-07-17 |
Family
ID=23362119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002471231A Abandoned CA2471231A1 (en) | 2002-01-11 | 2003-01-09 | Power factor controller |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7006367B2 (en) |
| AU (1) | AU2003201234A1 (en) |
| CA (1) | CA2471231A1 (en) |
| WO (1) | WO2003058797A1 (en) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004025597B4 (en) * | 2004-05-25 | 2014-08-21 | Tridonic Gmbh & Co Kg | Power Factor Correction Method and Circuit (PFC) |
| ATE469459T1 (en) * | 2005-10-28 | 2010-06-15 | Nxp Bv | POWER FACTOR CORRECTION BOOST CIRCUIT |
| WO2008022656A1 (en) * | 2006-08-25 | 2008-02-28 | Tte Germany Gmbh | Switched mode power supply |
| US7852017B1 (en) | 2007-03-12 | 2010-12-14 | Cirrus Logic, Inc. | Ballast for light emitting diode light sources |
| US8018171B1 (en) | 2007-03-12 | 2011-09-13 | Cirrus Logic, Inc. | Multi-function duty cycle modifier |
| US7667408B2 (en) * | 2007-03-12 | 2010-02-23 | Cirrus Logic, Inc. | Lighting system with lighting dimmer output mapping |
| US8076920B1 (en) | 2007-03-12 | 2011-12-13 | Cirrus Logic, Inc. | Switching power converter and control system |
| US7554473B2 (en) | 2007-05-02 | 2009-06-30 | Cirrus Logic, Inc. | Control system using a nonlinear delta-sigma modulator with nonlinear process modeling |
| US8102127B2 (en) | 2007-06-24 | 2012-01-24 | Cirrus Logic, Inc. | Hybrid gas discharge lamp-LED lighting system |
| US7804697B2 (en) * | 2007-12-11 | 2010-09-28 | Cirrus Logic, Inc. | History-independent noise-immune modulated transformer-coupled gate control signaling method and apparatus |
| US8008898B2 (en) * | 2008-01-30 | 2011-08-30 | Cirrus Logic, Inc. | Switching regulator with boosted auxiliary winding supply |
| US8022683B2 (en) | 2008-01-30 | 2011-09-20 | Cirrus Logic, Inc. | Powering a power supply integrated circuit with sense current |
| US7755525B2 (en) * | 2008-01-30 | 2010-07-13 | Cirrus Logic, Inc. | Delta sigma modulator with unavailable output values |
| US8576589B2 (en) | 2008-01-30 | 2013-11-05 | Cirrus Logic, Inc. | Switch state controller with a sense current generated operating voltage |
| US7759881B1 (en) | 2008-03-31 | 2010-07-20 | Cirrus Logic, Inc. | LED lighting system with a multiple mode current control dimming strategy |
| US8008902B2 (en) * | 2008-06-25 | 2011-08-30 | Cirrus Logic, Inc. | Hysteretic buck converter having dynamic thresholds |
| US8014176B2 (en) * | 2008-07-25 | 2011-09-06 | Cirrus Logic, Inc. | Resonant switching power converter with burst mode transition shaping |
| US8212491B2 (en) | 2008-07-25 | 2012-07-03 | Cirrus Logic, Inc. | Switching power converter control with triac-based leading edge dimmer compatibility |
| US8344707B2 (en) | 2008-07-25 | 2013-01-01 | Cirrus Logic, Inc. | Current sensing in a switching power converter |
| US8487546B2 (en) * | 2008-08-29 | 2013-07-16 | Cirrus Logic, Inc. | LED lighting system with accurate current control |
| US8222872B1 (en) | 2008-09-30 | 2012-07-17 | Cirrus Logic, Inc. | Switching power converter with selectable mode auxiliary power supply |
| US8179110B2 (en) | 2008-09-30 | 2012-05-15 | Cirrus Logic Inc. | Adjustable constant current source with continuous conduction mode (“CCM”) and discontinuous conduction mode (“DCM”) operation |
| US8288954B2 (en) * | 2008-12-07 | 2012-10-16 | Cirrus Logic, Inc. | Primary-side based control of secondary-side current for a transformer |
| US8299722B2 (en) | 2008-12-12 | 2012-10-30 | Cirrus Logic, Inc. | Time division light output sensing and brightness adjustment for different spectra of light emitting diodes |
| US8362707B2 (en) * | 2008-12-12 | 2013-01-29 | Cirrus Logic, Inc. | Light emitting diode based lighting system with time division ambient light feedback response |
| US7994863B2 (en) * | 2008-12-31 | 2011-08-09 | Cirrus Logic, Inc. | Electronic system having common mode voltage range enhancement |
| US8482223B2 (en) | 2009-04-30 | 2013-07-09 | Cirrus Logic, Inc. | Calibration of lamps |
| US8248145B2 (en) | 2009-06-30 | 2012-08-21 | Cirrus Logic, Inc. | Cascode configured switching using at least one low breakdown voltage internal, integrated circuit switch to control at least one high breakdown voltage external switch |
| US8198874B2 (en) * | 2009-06-30 | 2012-06-12 | Cirrus Logic, Inc. | Switching power converter with current sensing transformer auxiliary power supply |
| US8212493B2 (en) | 2009-06-30 | 2012-07-03 | Cirrus Logic, Inc. | Low energy transfer mode for auxiliary power supply operation in a cascaded switching power converter |
| US8963535B1 (en) | 2009-06-30 | 2015-02-24 | Cirrus Logic, Inc. | Switch controlled current sensing using a hall effect sensor |
| US9155174B2 (en) | 2009-09-30 | 2015-10-06 | Cirrus Logic, Inc. | Phase control dimming compatible lighting systems |
| US9178415B1 (en) | 2009-10-15 | 2015-11-03 | Cirrus Logic, Inc. | Inductor over-current protection using a volt-second value representing an input voltage to a switching power converter |
| US8487591B1 (en) | 2009-12-31 | 2013-07-16 | Cirrus Logic, Inc. | Power control system with power drop out immunity and uncompromised startup time |
| US8654483B2 (en) * | 2009-11-09 | 2014-02-18 | Cirrus Logic, Inc. | Power system having voltage-based monitoring for over current protection |
| US8912781B2 (en) | 2010-07-30 | 2014-12-16 | Cirrus Logic, Inc. | Integrated circuit switching power supply controller with selectable buck mode operation |
| US8866452B1 (en) | 2010-08-11 | 2014-10-21 | Cirrus Logic, Inc. | Variable minimum input voltage based switching in an electronic power control system |
| US9510401B1 (en) | 2010-08-24 | 2016-11-29 | Cirrus Logic, Inc. | Reduced standby power in an electronic power control system |
| DE102011100005A1 (en) * | 2011-04-29 | 2012-10-31 | Tridonic Gmbh & Co. Kg | Method and circuit for power factor correction |
| CN103583082B (en) | 2011-06-03 | 2016-11-02 | 皇家飞利浦有限公司 | For controlling method and apparatus and the power conversion equipment of switching power converter |
| CN103636109B (en) | 2011-06-03 | 2016-08-17 | 塞瑞斯逻辑公司 | For operating method and apparatus and the electric power distribution system of switched power transducer |
| EP2792037A2 (en) | 2011-12-14 | 2014-10-22 | Cirrus Logic, Inc. | Multi-mode flyback control for a switching power converter with dimmer |
| EP2605103B1 (en) * | 2011-12-15 | 2016-12-14 | Silergy Corp. | A controller for a switched mode power converter, a switched mode power converter and method of controlling the same |
| US9520794B2 (en) | 2012-07-25 | 2016-12-13 | Philips Lighting Holding B.V | Acceleration of output energy provision for a load during start-up of a switching power converter |
| US9024541B2 (en) | 2013-03-07 | 2015-05-05 | Cirrus Logic, Inc. | Utilizing secondary-side conduction time parameters of a switching power converter to provide energy to a load |
| WO2014186776A1 (en) | 2013-05-17 | 2014-11-20 | Cirrus Logic, Inc. | Charge pump-based circuitry for bjt power supply |
| US9253833B2 (en) | 2013-05-17 | 2016-02-02 | Cirrus Logic, Inc. | Single pin control of bipolar junction transistor (BJT)-based power stage |
| WO2015017315A1 (en) | 2013-07-29 | 2015-02-05 | Cirrus Logic, Inc. | Compensating for a reverse recovery time period of a bipolar junction transistor (bjt) in switch-mode operation of a light-emitting diode (led)-based bulb |
| WO2015017317A2 (en) | 2013-07-29 | 2015-02-05 | Cirrus Logic, Inc. | Two terminal drive of bipolar junction transistor (bjt) for switch-mode operation of a light emitting diode (led)-based bulb |
| US9214862B2 (en) | 2014-04-17 | 2015-12-15 | Philips International, B.V. | Systems and methods for valley switching in a switching power converter |
| US9325236B1 (en) | 2014-11-12 | 2016-04-26 | Koninklijke Philips N.V. | Controlling power factor in a switching power converter operating in discontinuous conduction mode |
| US9504118B2 (en) | 2015-02-17 | 2016-11-22 | Cirrus Logic, Inc. | Resistance measurement of a resistor in a bipolar junction transistor (BJT)-based power stage |
| US9609701B2 (en) | 2015-02-27 | 2017-03-28 | Cirrus Logic, Inc. | Switch-mode drive sensing of reverse recovery in bipolar junction transistor (BJT)-based power converters |
| US9603206B2 (en) | 2015-02-27 | 2017-03-21 | Cirrus Logic, Inc. | Detection and control mechanism for tail current in a bipolar junction transistor (BJT)-based power stage |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5357418A (en) | 1991-05-02 | 1994-10-18 | Robert Clavel | Hybrid power supply for converting an alternating input signal into a direct output signal |
| DE69206613T2 (en) | 1992-07-28 | 1996-05-02 | Sgs Thomson Microelectronics | Frequency-modulated switching power supply. |
| US5450029A (en) | 1993-06-25 | 1995-09-12 | At&T Corp. | Circuit for estimating a peak or RMS value of a sinusoidal voltage waveform |
| US5602465A (en) * | 1994-08-30 | 1997-02-11 | International Rectifier Corporation | Method and circuit to improve output voltage regulation and noise rejection of a power factor control stage |
| US6191676B1 (en) * | 1994-10-21 | 2001-02-20 | Spinel Llc | Apparatus for suppressing nonlinear current drawing characteristics |
| US6373734B1 (en) * | 2000-09-15 | 2002-04-16 | Artesyn Technologies, Inc. | Power factor correction control circuit and power supply including same |
| US6900623B2 (en) * | 2003-07-10 | 2005-05-31 | System General Corp. | Power supply having multi-vector error amplifier for power factor correction |
-
2003
- 2003-01-09 US US10/500,164 patent/US7006367B2/en not_active Expired - Fee Related
- 2003-01-09 WO PCT/CA2003/000009 patent/WO2003058797A1/en not_active Application Discontinuation
- 2003-01-09 CA CA002471231A patent/CA2471231A1/en not_active Abandoned
- 2003-01-09 AU AU2003201234A patent/AU2003201234A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| AU2003201234A1 (en) | 2003-07-24 |
| WO2003058797A1 (en) | 2003-07-17 |
| US20050057237A1 (en) | 2005-03-17 |
| US7006367B2 (en) | 2006-02-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7006367B2 (en) | Power factor controller | |
| Lai et al. | A family of continuous-conduction-mode power-factor-correction controllers based on the general pulse-width modulator | |
| CN108631578B (en) | Control unit for switching converter operating in continuous conduction and peak current control mode | |
| Qian et al. | Charge pump power-factor-correction technologies. I. Concept and principle | |
| Maksimovic | Design of the clamped-current high-power-factor boost rectifier | |
| Yang et al. | A novel switch-mode DC-to-AC inverter with nonlinear robust control | |
| Zhang et al. | Single-stage input-current-shaping technique with voltage-doubler-rectifier front end | |
| JPH11178216A (en) | Uninterruptible power unit | |
| Hirachi et al. | Cost-effective bidirectional chopper-based battery link UPS with common input-output bus line and its control scheme | |
| Guo et al. | A power-factor-corrected AC-AC inverter topology using a unified controller for high-frequency power distribution architecture | |
| Yang | Bidirectional DC-to-AC inverter with improved performance | |
| Siu et al. | Analysis and experimental evaluation of single-switch fast-response switching regulators with unity power factor | |
| Lee et al. | Integrated ZCS quasi-resonant power factor correction converter based on flyback topology | |
| Hernandez et al. | Comparative analysis of boost and buck-boost derived topologies used as power factor correctors | |
| Chang et al. | A novel forward AC/DC converter with input current shaping and fast output voltage regulation via reset winding | |
| Wu et al. | High-power-factor single-stage converter with robust controller for universal off-line applications | |
| Ho et al. | A new single-phase on-line UPS structure pre-staged with PFC-and-boost converter | |
| Srinivasan et al. | Single-phase parallel power processing scheme with power factor control | |
| Gangavarapu et al. | Analysis and design of three phase single stage isolated flyback based PFC converter with a novel clamping circuit | |
| US20120218782A1 (en) | Method and apparatus for signal conversion | |
| Ganesh et al. | Design and simulation of closed loop controller for SEPIC converter to improve power factor | |
| More et al. | Power Quality Improved Bridgeless Multiple Output Switched Mode Power Supply | |
| Rahulkrishnan et al. | Implementation of Enhanced Power Quality Electric Vehicle Charging System with Zeta Topology | |
| Rajini | A novel control scheme to improve the spectral quality of a single-phase bridgeless boost rectifier | |
| Yalcin et al. | Buck-type Single-phase AC-AC Active Tracking Voltage Regulator Controlled by an Enhanced Hybrid Control Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |