CA2391792A1 - Sram controller for parallel processor architecture - Google Patents

Sram controller for parallel processor architecture Download PDF

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Publication number
CA2391792A1
CA2391792A1 CA002391792A CA2391792A CA2391792A1 CA 2391792 A1 CA2391792 A1 CA 2391792A1 CA 002391792 A CA002391792 A CA 002391792A CA 2391792 A CA2391792 A CA 2391792A CA 2391792 A1 CA2391792 A1 CA 2391792A1
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CA
Canada
Prior art keywords
memory
read
controller
memory references
queue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002391792A
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French (fr)
Other versions
CA2391792C (en
Inventor
Matthew J. Adiletta
William Wheeler
James Redfield
Daniel Cutter
Gilbert Wolrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corporation
Matthew J. Adiletta
William Wheeler
James Redfield
Daniel Cutter
Gilbert Wolrich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Intel Corporation, Matthew J. Adiletta, William Wheeler, James Redfield, Daniel Cutter, Gilbert Wolrich filed Critical Intel Corporation
Publication of CA2391792A1 publication Critical patent/CA2391792A1/en
Application granted granted Critical
Publication of CA2391792C publication Critical patent/CA2391792C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Abstract

A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
CA002391792A 1999-08-31 2000-08-17 Sram controller for parallel processor architecture Expired - Fee Related CA2391792C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/387,110 1999-08-31
US09/387,110 US6427196B1 (en) 1999-08-31 1999-08-31 SRAM controller for parallel processor architecture including address and command queue and arbiter
PCT/US2000/022653 WO2001016769A1 (en) 1999-08-31 2000-08-17 Sram controller for parallel processor architecture

Publications (2)

Publication Number Publication Date
CA2391792A1 true CA2391792A1 (en) 2001-03-08
CA2391792C CA2391792C (en) 2004-12-07

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Family Applications (1)

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CA002391792A Expired - Fee Related CA2391792C (en) 1999-08-31 2000-08-17 Sram controller for parallel processor architecture

Country Status (9)

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US (3) US6427196B1 (en)
EP (1) EP1214660B1 (en)
CN (1) CN1192314C (en)
AT (1) ATE267420T1 (en)
AU (1) AU6646100A (en)
CA (1) CA2391792C (en)
DE (1) DE60010907T2 (en)
HK (1) HK1053728A1 (en)
WO (1) WO2001016769A1 (en)

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