CA2349344A1 - Reducing waiting time jitter - Google Patents

Reducing waiting time jitter Download PDF

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Publication number
CA2349344A1
CA2349344A1 CA002349344A CA2349344A CA2349344A1 CA 2349344 A1 CA2349344 A1 CA 2349344A1 CA 002349344 A CA002349344 A CA 002349344A CA 2349344 A CA2349344 A CA 2349344A CA 2349344 A1 CA2349344 A1 CA 2349344A1
Authority
CA
Canada
Prior art keywords
waiting time
bit
data stream
time jitter
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002349344A
Other languages
French (fr)
Other versions
CA2349344C (en
Inventor
Michael J. Rude
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commscope Connectivity LLC
Original Assignee
Adc Telecommunications, Inc.
Michael J. Rude
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Adc Telecommunications, Inc., Michael J. Rude filed Critical Adc Telecommunications, Inc.
Publication of CA2349344A1 publication Critical patent/CA2349344A1/en
Application granted granted Critical
Publication of CA2349344C publication Critical patent/CA2349344C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a "sub-bit" comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term "sub-bit" means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.
CA002349344A 1998-11-02 1999-11-02 Reducing waiting time jitter Expired - Fee Related CA2349344C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/184,627 1998-11-02
US09/184,627 US6229863B1 (en) 1998-11-02 1998-11-02 Reducing waiting time jitter
PCT/US1999/025801 WO2000027059A1 (en) 1998-11-02 1999-11-02 Reducing waiting time jitter

Publications (2)

Publication Number Publication Date
CA2349344A1 true CA2349344A1 (en) 2000-05-11
CA2349344C CA2349344C (en) 2003-07-08

Family

ID=22677692

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002349344A Expired - Fee Related CA2349344C (en) 1998-11-02 1999-11-02 Reducing waiting time jitter

Country Status (8)

Country Link
US (2) US6229863B1 (en)
EP (1) EP1125387A1 (en)
CN (1) CN1338165A (en)
AU (1) AU1604600A (en)
BR (1) BR9914992A (en)
CA (1) CA2349344C (en)
TW (1) TW454393B (en)
WO (1) WO2000027059A1 (en)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI965072A (en) * 1996-12-17 1998-08-13 Nokia Telecommunications Oy Method for damping transients caused by smoothing events in a desynchronizer
US6747983B1 (en) * 1998-10-02 2004-06-08 Thomson Licensing S.A. Transport packet rate conversion
US6888840B1 (en) * 1998-10-02 2005-05-03 Thomson Licensing S.A. Output symbol rate control in a packet transport rate conversion system
JP3478228B2 (en) * 2000-03-07 2003-12-15 日本電気株式会社 Speed conversion circuit and control method thereof
JP2001345791A (en) * 2000-05-30 2001-12-14 Hitachi Ltd Clock generating circuit and semiconductor integrated circuit for communication
US7042908B1 (en) * 2000-07-10 2006-05-09 Nortel Networks Limited Method and apparatus for transmitting arbitrary electrical signals over a data network
EP1204276A3 (en) * 2000-10-10 2007-01-03 Matsushita Electric Industrial Co., Ltd. Apparatus for processing a digital Audio Video signal
US7366270B2 (en) * 2000-12-20 2008-04-29 Primarion, Inc. PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator
US20020075981A1 (en) * 2000-12-20 2002-06-20 Benjamim Tang PLL/DLL dual loop data synchronization
DE60108728T2 (en) * 2001-06-15 2006-05-11 Lucent Technologies Inc. Method and device for transmitting and receiving multiplexed subordinate signals
US6873195B2 (en) * 2001-08-22 2005-03-29 Bigband Networks Bas, Inc. Compensating for differences between clock signals
US7027547B1 (en) * 2001-10-05 2006-04-11 Crest Microsystems Method and apparatus for matching transmission rates across a single channel
US7286487B2 (en) * 2002-11-18 2007-10-23 Infinera Corporation Optical transmission network with asynchronous mapping and demapping and digital wrapper frame for the same
US7023942B1 (en) * 2001-10-09 2006-04-04 Nortel Networks Limited Method and apparatus for digital data synchronization
US8274892B2 (en) * 2001-10-09 2012-09-25 Infinera Corporation Universal digital framer architecture for transport of client signals of any client payload and format type
NO20016328D0 (en) * 2001-12-21 2001-12-21 Ericsson Telefon Ab L M Method and arrangement for transmitting bit streams through a data anode
DE10231648B4 (en) * 2002-07-12 2007-05-03 Infineon Technologies Ag Method and device for stuffing control
US7369578B2 (en) * 2003-07-01 2008-05-06 Nortel Networks Limited Digital processing of SONET pointers
US8019035B2 (en) * 2003-08-05 2011-09-13 Stmicroelectronics Nv Noise shaped interpolator and decimator apparatus and method
ATE352912T1 (en) * 2005-01-07 2007-02-15 Cit Alcatel RECEIVER FOR IMPROVEMENT OF POLARIZATION MODE DISPERSION USING POLARIZATION SCROLLING
US7346793B2 (en) * 2005-02-10 2008-03-18 Northrop Grumman Corporation Synchronization of multiple operational flight programs
US7646836B1 (en) * 2005-03-01 2010-01-12 Network Equipment Technologies, Inc. Dynamic clock rate matching across an asynchronous network
JP2007096822A (en) * 2005-09-29 2007-04-12 Fujitsu Ltd Signal multiplxer and its stuff control method
US8135285B2 (en) * 2005-12-22 2012-03-13 Ntt Electronics Corporation Optical transmission system and method
US8681917B2 (en) 2010-03-31 2014-03-25 Andrew Llc Synchronous transfer of streaming data in a distributed antenna system
US9807207B2 (en) * 2015-03-26 2017-10-31 Adtran, Inc. Timing preservation for network communications
CN111190089B (en) 2018-11-14 2022-01-11 长鑫存储技术有限公司 Method and device for determining jitter time, storage medium and electronic equipment

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4397017A (en) 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
CA1262173A (en) 1986-05-29 1989-10-03 James Angus Mceachern Synchronization of asynchronous data signals
US4764941A (en) 1987-05-22 1988-08-16 American Telephone And Telegraph Company, At&T Bell Laboratories Digital frame synchronizer
US4791652A (en) 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals
US4862485A (en) 1987-10-14 1989-08-29 National Semiconductor Corporation Quotient phase-shift processor for digital phase-locked-loops
US4928275A (en) 1989-05-26 1990-05-22 Northern Telecom Limited Synchronization of asynchronous data signals
CA1326719C (en) 1989-05-30 1994-02-01 Thomas E. Moore Ds3 to 28 vt1.5 sonet interface circuit
US5359605A (en) 1989-06-22 1994-10-25 U.S. Philips Corporation Circuit arrangement for adjusting the bit rates of two signals
DE3922897A1 (en) 1989-07-12 1991-01-17 Philips Patentverwaltung PLUG DECISION CIRCUIT FOR A BITRATE ADJUSTMENT ARRANGEMENT
DE3942885A1 (en) 1989-12-23 1991-06-27 Philips Patentverwaltung BITRATE ADJUSTMENT CIRCUIT
DE3942883A1 (en) 1989-12-23 1991-06-27 Philips Patentverwaltung BITRATE ADJUSTMENT CIRCUIT
DE4013317A1 (en) 1990-04-26 1990-08-23 Ant Nachrichtentech STAMPING METHOD FOR REDUCING THE WAITING PERIOD AND ARRANGEMENT FOR IMPLEMENTING THE METHOD
US5111485A (en) 1990-05-18 1992-05-05 Northern Telecom Limited Method of and circuit for synchronizing data
US5276688A (en) 1990-06-09 1994-01-04 U.S. Philips Corporation Circuit arrangement for bit rate adjustment
US5052025A (en) 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
DE4027968A1 (en) 1990-09-04 1992-03-05 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR BITRATE ADJUSTMENT OF TWO DIGITAL SIGNALS
DE4027967A1 (en) 1990-09-04 1992-03-05 Philips Patentverwaltung PLUG DECISION CIRCUIT FOR A BITRATE ADJUSTMENT ARRANGEMENT
DE4035438A1 (en) 1990-11-08 1992-05-14 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR REMOVING STOPBITS
DE4101270A1 (en) 1991-01-17 1992-07-23 Siemens Ag METHOD FOR TRANSMITTING DIGITAL SIGNALS
DE4108429A1 (en) 1991-03-15 1992-09-17 Philips Patentverwaltung TRANSMISSION SYSTEM FOR THE DIGITAL SYNCHRONOUS HIERARCHY
DE4110933A1 (en) 1991-04-04 1992-10-08 Philips Patentverwaltung TRANSMISSION SYSTEM FOR THE SYNCHRONOUS DIGITAL HIERACHIE
US5268935A (en) 1991-12-20 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
JPH05199199A (en) 1992-01-20 1993-08-06 Fujitsu Ltd Stuff synchronization control system
JP3066690B2 (en) * 1993-09-20 2000-07-17 富士通株式会社 Phase-locked oscillation circuit
FR2711435B1 (en) 1993-10-20 1995-12-29 Cit Alcatel Device to justify a digital train at regular intervals.
DE4339586B4 (en) 1993-11-20 2006-04-13 Philips Intellectual Property & Standards Gmbh transmission system
US5539785A (en) 1994-07-27 1996-07-23 Adtran Jitter/wander reduction circuit for pulse-stuffed, synchronized digital communications
JP2616731B2 (en) 1994-12-27 1997-06-04 日本電気株式会社 Transmission signal processing circuit
US5619506A (en) 1995-04-27 1997-04-08 Adtran, Inc. Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US5680422A (en) 1995-04-27 1997-10-21 Adtran Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US5563891A (en) 1995-09-05 1996-10-08 Industrial Technology Research Institute Waiting time jitter reduction by synchronizer stuffing threshold modulation
US5889781A (en) 1996-06-11 1999-03-30 Vlsi Technology Asynchronous timing generator
US6266385B1 (en) * 1997-12-23 2001-07-24 Wireless Facilities, Inc. Elastic store for wireless communication systems

Also Published As

Publication number Publication date
TW454393B (en) 2001-09-11
CA2349344C (en) 2003-07-08
CN1338165A (en) 2002-02-27
WO2000027059A1 (en) 2000-05-11
AU1604600A (en) 2000-05-22
BR9914992A (en) 2001-07-24
EP1125387A1 (en) 2001-08-22
US20010022826A1 (en) 2001-09-20
US6229863B1 (en) 2001-05-08
US6415006B2 (en) 2002-07-02

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Effective date: 20131104