CA2293602A1 - Bus interface system and method - Google Patents

Bus interface system and method Download PDF

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Publication number
CA2293602A1
CA2293602A1 CA002293602A CA2293602A CA2293602A1 CA 2293602 A1 CA2293602 A1 CA 2293602A1 CA 002293602 A CA002293602 A CA 002293602A CA 2293602 A CA2293602 A CA 2293602A CA 2293602 A1 CA2293602 A1 CA 2293602A1
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CA
Canada
Prior art keywords
peripheral device
bus
port
bus interface
interface system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002293602A
Other languages
French (fr)
Other versions
CA2293602C (en
Inventor
Ronald H. Sartore
Steven P. Larky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corporation
Ronald H. Sartore
Steven P. Larky
Anchor Chips Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25390093&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CA2293602(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Cypress Semiconductor Corporation, Ronald H. Sartore, Steven P. Larky, Anchor Chips Incorporated filed Critical Cypress Semiconductor Corporation
Publication of CA2293602A1 publication Critical patent/CA2293602A1/en
Application granted granted Critical
Publication of CA2293602C publication Critical patent/CA2293602C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A system and method for reconfiguring a peripheral device (54) connected by a computer bus (60) and port to a host (52) from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device (76) for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.
CA002293602A 1997-07-02 1998-06-26 Bus interface system and method Expired - Fee Related CA2293602C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US886,923 1997-07-02
US08/886,923 US6012103A (en) 1997-07-02 1997-07-02 Bus interface system and method
PCT/US1998/013397 WO1999001820A1 (en) 1997-07-02 1998-06-26 Bus interface system and method

Publications (2)

Publication Number Publication Date
CA2293602A1 true CA2293602A1 (en) 1999-01-14
CA2293602C CA2293602C (en) 2006-11-07

Family

ID=25390093

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002293602A Expired - Fee Related CA2293602C (en) 1997-07-02 1998-06-26 Bus interface system and method

Country Status (8)

Country Link
US (3) US6012103A (en)
EP (1) EP0992000B1 (en)
JP (2) JP4051094B2 (en)
KR (1) KR100580965B1 (en)
AU (1) AU8173298A (en)
CA (1) CA2293602C (en)
DE (1) DE69834401T2 (en)
WO (1) WO1999001820A1 (en)

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