CA2256222A1 - Content addressable memory fifo with and without purging - Google Patents

Content addressable memory fifo with and without purging

Info

Publication number
CA2256222A1
CA2256222A1 CA002256222A CA2256222A CA2256222A1 CA 2256222 A1 CA2256222 A1 CA 2256222A1 CA 002256222 A CA002256222 A CA 002256222A CA 2256222 A CA2256222 A CA 2256222A CA 2256222 A1 CA2256222 A1 CA 2256222A1
Authority
CA
Canada
Prior art keywords
data
fifo
read
content addressable
purging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002256222A
Other languages
French (fr)
Other versions
CA2256222C (en
Inventor
John T. Pedicone
Thomas A. Chiacchira
Andres Alvarez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2256222A1 publication Critical patent/CA2256222A1/en
Application granted granted Critical
Publication of CA2256222C publication Critical patent/CA2256222C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Abstract

A content-addressable, first-in/first-out memory (CAM-FIFO), as used to provide a read-modify-write buffer for data between two processes, includes: a Content Addressable Memory (CAM) which stores flag data; a FIFO memory portion for providing data storage; a write/read address counting section for providing write/read addresses of data to be stored in/read from the FIFO; and logic to determine and is used to query data on the queue to determine if the FIFO data should still be sent to the receiving process, or replaced with at least part of the flag data.
CA002256222A 1997-12-18 1998-12-16 Content addressable memory fifo with and without purging Expired - Fee Related CA2256222C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/993,513 1997-12-18
US08/993,513 US6052757A (en) 1997-12-18 1997-12-18 Content addressable memory FIFO with and without purging

Publications (2)

Publication Number Publication Date
CA2256222A1 true CA2256222A1 (en) 1999-06-18
CA2256222C CA2256222C (en) 2007-06-26

Family

ID=25539625

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002256222A Expired - Fee Related CA2256222C (en) 1997-12-18 1998-12-16 Content addressable memory fifo with and without purging

Country Status (10)

Country Link
US (1) US6052757A (en)
EP (1) EP0924598B1 (en)
JP (1) JP4519213B2 (en)
CA (1) CA2256222C (en)
DE (1) DE69817990T2 (en)
HK (1) HK1019101A1 (en)
IL (1) IL127590A (en)
MY (1) MY116310A (en)
SG (1) SG81948A1 (en)
TW (1) TW426823B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6591332B1 (en) * 2000-04-28 2003-07-08 Hewlett-Packard Development Company, L.P. Apparatus and method for tracking flushes of cache entries in a data processing system
JP3542943B2 (en) * 2000-04-28 2004-07-14 松下電器産業株式会社 Data transfer device and data transfer method
US6784892B1 (en) * 2000-10-05 2004-08-31 Micron Technology, Inc. Fully associative texture cache having content addressable memory and method for use thereof
TWI325532B (en) * 2006-09-14 2010-06-01 Novatek Microelectronics Corp Controlling circuit and method for power saving
US7594047B2 (en) * 2007-07-09 2009-09-22 Hewlett-Packard Development Company, L.P. Buffer circuit
US9189199B2 (en) 2012-12-06 2015-11-17 Nvidia Corporation Folded FIFO memory generator
US11036427B2 (en) 2019-04-04 2021-06-15 International Business Machines Corporation Using content addressable memory to perform read-modify-write operations in non-volatile random access memory (NVRAM)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3601809A (en) * 1968-11-04 1971-08-24 Univ Pennsylvania Addressable list memory systems
US4873665A (en) * 1988-06-07 1989-10-10 Dallas Semiconductor Corporation Dual storage cell memory including data transfer circuits
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5088061A (en) * 1990-07-24 1992-02-11 Vlsi Technology, Inc. Routing independent circuit components
US5301141A (en) * 1992-05-01 1994-04-05 Intel Corporation Data flow computer with an articulated first-in-first-out content addressable memory
US5513376A (en) * 1993-11-02 1996-04-30 National Semiconductor Corporation Method of operating an extension FIFO in another device when it is full by periodically re-initiating a write operation until data can be transferred
US5438535A (en) * 1994-03-29 1995-08-01 Panasonic Technologies, Inc. Content addressable memory system
US5696930A (en) * 1996-02-09 1997-12-09 Advanced Micro Devices, Inc. CAM accelerated buffer management

Also Published As

Publication number Publication date
EP0924598A2 (en) 1999-06-23
DE69817990T2 (en) 2004-07-22
MY116310A (en) 2003-12-31
EP0924598A3 (en) 2000-05-24
JP4519213B2 (en) 2010-08-04
CA2256222C (en) 2007-06-26
IL127590A0 (en) 1999-10-28
JPH11317070A (en) 1999-11-16
HK1019101A1 (en) 2000-01-21
US6052757A (en) 2000-04-18
DE69817990D1 (en) 2003-10-16
IL127590A (en) 2004-05-12
TW426823B (en) 2001-03-21
EP0924598B1 (en) 2003-09-10
SG81948A1 (en) 2001-07-24

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKLA Lapsed

Effective date: 20111216